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Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glass2e7d35d2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070011
Simon Glass00606d72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070025 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020026 remoteproc0 = &rproc_1;
27 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060047 };
48
Simon Glassce6d99a2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Simon Glasse96fa6c2018-12-10 10:37:34 -070054 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060055 reg = <0 0>;
56 compatible = "google,cros-ec-sandbox";
57
58 /*
59 * This describes the flash memory within the EC. Note
60 * that the STM32L flash erases to 0, not 0xff.
61 */
62 flash {
63 image-pos = <0x08000000>;
64 size = <0x20000>;
65 erase-value = <0>;
66
67 /* Information for sandbox */
68 ro {
69 image-pos = <0>;
70 size = <0xf000>;
71 };
72 wp-ro {
73 image-pos = <0xf000>;
74 size = <0x1000>;
75 };
76 rw {
77 image-pos = <0x10000>;
78 size = <0x10000>;
79 };
80 };
81 };
82
Yannick Fertré23f965a2019-10-07 15:29:05 +020083 dsi_host: dsi_host {
84 compatible = "sandbox,dsi-host";
85 };
86
Simon Glass2e7d35d2014-02-26 15:59:21 -070087 a-test {
Simon Glass0503e822015-07-06 12:54:36 -060088 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070089 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -060090 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070091 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -060092 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010093 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
94 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -070095 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010096 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
97 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
98 <&gpio_b 7 GPIO_IN 3 2 1>,
99 <&gpio_b 8 GPIO_OUT 3 2 1>,
100 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100101 test3-gpios =
102 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
103 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
104 <&gpio_c 2 GPIO_OUT>,
105 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
106 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200107 <&gpio_c 5 GPIO_IN>,
108 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
109 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700110 int-value = <1234>;
111 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200112 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200113 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600114 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700115 interrupts-extended = <&irq 3 0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700116 };
117
118 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600119 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700120 compatible = "not,compatible";
121 };
122
123 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600124 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700125 };
126
Simon Glass5d9a88f2018-10-01 12:22:40 -0600127 backlight: backlight {
128 compatible = "pwm-backlight";
129 enable-gpios = <&gpio_a 1>;
130 power-supply = <&ldo_1>;
131 pwms = <&pwm 0 1000>;
132 default-brightness-level = <5>;
133 brightness-levels = <0 16 32 64 128 170 202 234 255>;
134 };
135
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200136 bind-test {
137 bind-test-child1 {
138 compatible = "sandbox,phy";
139 #phy-cells = <1>;
140 };
141
142 bind-test-child2 {
143 compatible = "simple-bus";
144 };
145 };
146
Simon Glass2e7d35d2014-02-26 15:59:21 -0700147 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600148 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700149 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600150 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700151 ping-add = <3>;
152 };
153
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200154 phy_provider0: gen_phy@0 {
155 compatible = "sandbox,phy";
156 #phy-cells = <1>;
157 };
158
159 phy_provider1: gen_phy@1 {
160 compatible = "sandbox,phy";
161 #phy-cells = <0>;
162 broken;
163 };
164
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200165 phy_provider2: gen_phy@2 {
166 compatible = "sandbox,phy";
167 #phy-cells = <0>;
168 };
169
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200170 gen_phy_user: gen_phy_user {
171 compatible = "simple-bus";
172 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
173 phy-names = "phy1", "phy2", "phy3";
174 };
175
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200176 gen_phy_user1: gen_phy_user1 {
177 compatible = "simple-bus";
178 phys = <&phy_provider0 0>, <&phy_provider2>;
179 phy-names = "phy1", "phy2";
180 };
181
Simon Glass2e7d35d2014-02-26 15:59:21 -0700182 some-bus {
183 #address-cells = <1>;
184 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600185 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600186 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600187 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700188 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600189 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700190 compatible = "denx,u-boot-fdt-test";
191 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600192 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700193 ping-add = <5>;
194 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600195 c-test@0 {
196 compatible = "denx,u-boot-fdt-test";
197 reg = <0>;
198 ping-expect = <6>;
199 ping-add = <6>;
200 };
201 c-test@1 {
202 compatible = "denx,u-boot-fdt-test";
203 reg = <1>;
204 ping-expect = <7>;
205 ping-add = <7>;
206 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700207 };
208
209 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600210 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600211 ping-expect = <6>;
212 ping-add = <6>;
213 compatible = "google,another-fdt-test";
214 };
215
216 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600217 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600218 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700219 ping-add = <6>;
220 compatible = "google,another-fdt-test";
221 };
222
Simon Glass9cc36a22015-01-25 08:27:05 -0700223 f-test {
224 compatible = "denx,u-boot-fdt-test";
225 };
226
227 g-test {
228 compatible = "denx,u-boot-fdt-test";
229 };
230
Bin Meng2786cd72018-10-10 22:07:01 -0700231 h-test {
232 compatible = "denx,u-boot-fdt-test1";
233 };
234
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200235 i-test {
236 compatible = "mediatek,u-boot-fdt-test";
237 #address-cells = <1>;
238 #size-cells = <0>;
239
240 subnode@0 {
241 reg = <0>;
242 };
243
244 subnode@1 {
245 reg = <1>;
246 };
247
248 subnode@2 {
249 reg = <2>;
250 };
251 };
252
Simon Glassdc12ebb2019-12-29 21:19:25 -0700253 devres-test {
254 compatible = "denx,u-boot-devres-test";
255 };
256
Simon Glassf50cc952020-04-08 16:57:34 -0600257 acpi-test {
258 compatible = "denx,u-boot-acpi-test";
Simon Glass1361a532020-07-07 13:11:39 -0600259 child {
260 compatible = "denx,u-boot-acpi-test";
261 };
Simon Glassf50cc952020-04-08 16:57:34 -0600262 };
263
Simon Glass93f7f822020-04-26 09:19:46 -0600264 acpi-test2 {
265 compatible = "denx,u-boot-acpi-test";
266 };
267
Patrice Chotardee87a092017-09-04 14:55:57 +0200268 clocks {
269 clk_fixed: clk-fixed {
270 compatible = "fixed-clock";
271 #clock-cells = <0>;
272 clock-frequency = <1234>;
273 };
Anup Patelb630d572019-02-25 08:14:55 +0000274
275 clk_fixed_factor: clk-fixed-factor {
276 compatible = "fixed-factor-clock";
277 #clock-cells = <0>;
278 clock-div = <3>;
279 clock-mult = <2>;
280 clocks = <&clk_fixed>;
281 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200282
283 osc {
284 compatible = "fixed-clock";
285 #clock-cells = <0>;
286 clock-frequency = <20000000>;
287 };
Stephen Warren135aa952016-06-17 09:44:00 -0600288 };
289
290 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600291 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600292 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200293 assigned-clocks = <&clk_sandbox 3>;
294 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600295 };
296
297 clk-test {
298 compatible = "sandbox,clk-test";
299 clocks = <&clk_fixed>,
300 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200301 <&clk_sandbox 0>,
302 <&clk_sandbox 3>,
303 <&clk_sandbox 2>;
304 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600305 };
306
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200307 ccf: clk-ccf {
308 compatible = "sandbox,clk-ccf";
309 };
310
Simon Glass171e9912015-05-22 15:42:15 -0600311 eth@10002000 {
312 compatible = "sandbox,eth";
313 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500314 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600315 };
316
317 eth_5: eth@10003000 {
318 compatible = "sandbox,eth";
319 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500320 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600321 };
322
Bin Meng71d79712015-08-27 22:25:53 -0700323 eth_3: sbe5 {
324 compatible = "sandbox,eth";
325 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500326 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700327 };
328
Simon Glass171e9912015-05-22 15:42:15 -0600329 eth@10004000 {
330 compatible = "sandbox,eth";
331 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500332 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600333 };
334
Rajan Vaja31b82172018-09-19 03:43:46 -0700335 firmware {
336 sandbox_firmware: sandbox-firmware {
337 compatible = "sandbox,firmware";
338 };
339 };
340
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100341 pinctrl-gpio {
342 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700343
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100344 gpio_a: base-gpios {
345 compatible = "sandbox,gpio";
346 gpio-controller;
347 #gpio-cells = <1>;
348 gpio-bank-name = "a";
349 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200350 hog_input_active_low {
351 gpio-hog;
352 input;
353 gpios = <0 GPIO_ACTIVE_LOW>;
354 };
355 hog_input_active_high {
356 gpio-hog;
357 input;
358 gpios = <1 GPIO_ACTIVE_HIGH>;
359 };
360 hog_output_low {
361 gpio-hog;
362 output-low;
363 gpios = <2 GPIO_ACTIVE_HIGH>;
364 };
365 hog_output_high {
366 gpio-hog;
367 output-high;
368 gpios = <3 GPIO_ACTIVE_HIGH>;
369 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100370 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600371
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100372 gpio_b: extra-gpios {
373 compatible = "sandbox,gpio";
374 gpio-controller;
375 #gpio-cells = <5>;
376 gpio-bank-name = "b";
377 sandbox,gpio-count = <10>;
378 };
379
380 gpio_c: pinmux-gpios {
381 compatible = "sandbox,gpio";
382 gpio-controller;
383 #gpio-cells = <2>;
384 gpio-bank-name = "c";
385 sandbox,gpio-count = <10>;
386 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100387 };
388
Simon Glassecc2ed52014-12-10 08:55:55 -0700389 i2c@0 {
390 #address-cells = <1>;
391 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600392 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700393 compatible = "sandbox,i2c";
394 clock-frequency = <100000>;
395 eeprom@2c {
396 reg = <0x2c>;
397 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700398 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700399 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200400
Simon Glass52d3bc52015-05-22 15:42:17 -0600401 rtc_0: rtc@43 {
402 reg = <0x43>;
403 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700404 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600405 };
406
407 rtc_1: rtc@61 {
408 reg = <0x61>;
409 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700410 sandbox,emul = <&emul1>;
411 };
412
413 i2c_emul: emul {
414 reg = <0xff>;
415 compatible = "sandbox,i2c-emul-parent";
416 emul_eeprom: emul-eeprom {
417 compatible = "sandbox,i2c-eeprom";
418 sandbox,filename = "i2c.bin";
419 sandbox,size = <256>;
420 };
421 emul0: emul0 {
422 compatible = "sandbox,i2c-rtc";
423 };
424 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600425 compatible = "sandbox,i2c-rtc";
426 };
427 };
428
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200429 sandbox_pmic: sandbox_pmic {
430 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700431 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200432 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200433
434 mc34708: pmic@41 {
435 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700436 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200437 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700438 };
439
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100440 bootcount@0 {
441 compatible = "u-boot,bootcount-rtc";
442 rtc = <&rtc_1>;
443 offset = <0x13>;
444 };
445
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100446 adc@0 {
447 compatible = "sandbox,adc";
448 vdd-supply = <&buck2>;
449 vss-microvolts = <0>;
450 };
451
Simon Glass02554352020-02-06 09:55:00 -0700452 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700453 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700454 interrupt-controller;
455 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700456 };
457
Simon Glass3c97c4f2016-01-18 19:52:26 -0700458 lcd {
459 u-boot,dm-pre-reloc;
460 compatible = "sandbox,lcd-sdl";
461 xres = <1366>;
462 yres = <768>;
463 };
464
Simon Glass3c43fba2015-07-06 12:54:34 -0600465 leds {
466 compatible = "gpio-leds";
467
468 iracibble {
469 gpios = <&gpio_a 1 0>;
470 label = "sandbox:red";
471 };
472
473 martinet {
474 gpios = <&gpio_a 2 0>;
475 label = "sandbox:green";
476 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200477
478 default_on {
479 gpios = <&gpio_a 5 0>;
480 label = "sandbox:default_on";
481 default-state = "on";
482 };
483
484 default_off {
485 gpios = <&gpio_a 6 0>;
486 label = "sandbox:default_off";
487 default-state = "off";
488 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600489 };
490
Stephen Warren8961b522016-05-16 17:41:37 -0600491 mbox: mbox {
492 compatible = "sandbox,mbox";
493 #mbox-cells = <1>;
494 };
495
496 mbox-test {
497 compatible = "sandbox,mbox-test";
498 mboxes = <&mbox 100>, <&mbox 1>;
499 mbox-names = "other", "test";
500 };
501
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900502 cpus {
503 cpu-test1 {
504 compatible = "sandbox,cpu_sandbox";
505 u-boot,dm-pre-reloc;
506 };
Mario Sixfa44b532018-08-06 10:23:44 +0200507
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900508 cpu-test2 {
509 compatible = "sandbox,cpu_sandbox";
510 u-boot,dm-pre-reloc;
511 };
Mario Sixfa44b532018-08-06 10:23:44 +0200512
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900513 cpu-test3 {
514 compatible = "sandbox,cpu_sandbox";
515 u-boot,dm-pre-reloc;
516 };
Mario Sixfa44b532018-08-06 10:23:44 +0200517 };
518
Simon Glasse96fa6c2018-12-10 10:37:34 -0700519 i2s: i2s {
520 compatible = "sandbox,i2s";
521 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700522 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700523 };
524
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200525 nop-test_0 {
526 compatible = "sandbox,nop_sandbox1";
527 nop-test_1 {
528 compatible = "sandbox,nop_sandbox2";
529 bind = "True";
530 };
531 nop-test_2 {
532 compatible = "sandbox,nop_sandbox2";
533 bind = "False";
534 };
535 };
536
Mario Six004e67c2018-07-31 14:24:14 +0200537 misc-test {
538 compatible = "sandbox,misc_sandbox";
539 };
540
Simon Glasse48eeb92017-04-23 20:02:07 -0600541 mmc2 {
542 compatible = "sandbox,mmc";
543 };
544
545 mmc1 {
546 compatible = "sandbox,mmc";
547 };
548
549 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600550 compatible = "sandbox,mmc";
551 };
552
Simon Glassb45c8332019-02-16 20:24:50 -0700553 pch {
554 compatible = "sandbox,pch";
555 };
556
Tom Rini42c64d12020-02-11 12:41:23 -0500557 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700558 compatible = "sandbox,pci";
559 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500560 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700561 #address-cells = <3>;
562 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600563 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700564 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700565 pci@0,0 {
566 compatible = "pci-generic";
567 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600568 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700569 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300570 pci@1,0 {
571 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600572 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
573 reg = <0x02000814 0 0 0 0
574 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600575 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300576 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700577 p2sb-pci@2,0 {
578 compatible = "sandbox,p2sb";
579 reg = <0x02001010 0 0 0 0>;
580 sandbox,emul = <&p2sb_emul>;
581
582 adder {
583 intel,p2sb-port-id = <3>;
584 compatible = "sandbox,adder";
585 };
586 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700587 pci@1e,0 {
588 compatible = "sandbox,pmc";
589 reg = <0xf000 0 0 0 0>;
590 sandbox,emul = <&pmc_emul1e>;
591 acpi-base = <0x400>;
592 gpe0-dwx-mask = <0xf>;
593 gpe0-dwx-shift-base = <4>;
594 gpe0-dw = <6 7 9>;
595 gpe0-sts = <0x20>;
596 gpe0-en = <0x30>;
597 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700598 pci@1f,0 {
599 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600600 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
601 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600602 sandbox,emul = <&swap_case_emul0_1f>;
603 };
604 };
605
606 pci-emul0 {
607 compatible = "sandbox,pci-emul-parent";
608 swap_case_emul0_0: emul0@0,0 {
609 compatible = "sandbox,swap-case";
610 };
611 swap_case_emul0_1: emul0@1,0 {
612 compatible = "sandbox,swap-case";
613 use-ea;
614 };
615 swap_case_emul0_1f: emul0@1f,0 {
616 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700617 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700618 p2sb_emul: emul@2,0 {
619 compatible = "sandbox,p2sb-emul";
620 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700621 pmc_emul1e: emul@1e,0 {
622 compatible = "sandbox,pmc-emul";
623 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700624 };
625
Tom Rini42c64d12020-02-11 12:41:23 -0500626 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700627 compatible = "sandbox,pci";
628 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500629 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700630 #address-cells = <3>;
631 #size-cells = <2>;
632 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
633 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700634 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200635 0x0c 0x00 0x1234 0x5678
636 0x10 0x00 0x1234 0x5678>;
637 pci@10,0 {
638 reg = <0x8000 0 0 0 0>;
639 };
Bin Mengdee4d752018-08-03 01:14:41 -0700640 };
641
Tom Rini42c64d12020-02-11 12:41:23 -0500642 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700643 compatible = "sandbox,pci";
644 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500645 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700646 #address-cells = <3>;
647 #size-cells = <2>;
648 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
649 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
650 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
651 pci@1f,0 {
652 compatible = "pci-generic";
653 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600654 sandbox,emul = <&swap_case_emul2_1f>;
655 };
656 };
657
658 pci-emul2 {
659 compatible = "sandbox,pci-emul-parent";
660 swap_case_emul2_1f: emul2@1f,0 {
661 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700662 };
663 };
664
Ramon Friedbb413332019-04-27 11:15:23 +0300665 pci_ep: pci_ep {
666 compatible = "sandbox,pci_ep";
667 };
668
Simon Glass98561572017-04-23 20:10:44 -0600669 probing {
670 compatible = "simple-bus";
671 test1 {
672 compatible = "denx,u-boot-probe-test";
673 };
674
675 test2 {
676 compatible = "denx,u-boot-probe-test";
677 };
678
679 test3 {
680 compatible = "denx,u-boot-probe-test";
681 };
682
683 test4 {
684 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100685 first-syscon = <&syscon0>;
686 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100687 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600688 };
689 };
690
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600691 pwrdom: power-domain {
692 compatible = "sandbox,power-domain";
693 #power-domain-cells = <1>;
694 };
695
696 power-domain-test {
697 compatible = "sandbox,power-domain-test";
698 power-domains = <&pwrdom 2>;
699 };
700
Simon Glass5d9a88f2018-10-01 12:22:40 -0600701 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600702 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600703 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600704 };
705
706 pwm2 {
707 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600708 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600709 };
710
Simon Glass64ce0ca2015-07-06 12:54:31 -0600711 ram {
712 compatible = "sandbox,ram";
713 };
714
Simon Glass5010d982015-07-06 12:54:29 -0600715 reset@0 {
716 compatible = "sandbox,warm-reset";
717 };
718
719 reset@1 {
720 compatible = "sandbox,reset";
721 };
722
Stephen Warren4581b712016-06-17 09:43:59 -0600723 resetc: reset-ctl {
724 compatible = "sandbox,reset-ctl";
725 #reset-cells = <1>;
726 };
727
728 reset-ctl-test {
729 compatible = "sandbox,reset-ctl-test";
730 resets = <&resetc 100>, <&resetc 2>;
731 reset-names = "other", "test";
732 };
733
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530734 rng {
735 compatible = "sandbox,sandbox-rng";
736 };
737
Nishanth Menon52159402015-09-17 15:42:41 -0500738 rproc_1: rproc@1 {
739 compatible = "sandbox,test-processor";
740 remoteproc-name = "remoteproc-test-dev1";
741 };
742
743 rproc_2: rproc@2 {
744 compatible = "sandbox,test-processor";
745 internal-memory-mapped;
746 remoteproc-name = "remoteproc-test-dev2";
747 };
748
Simon Glass5d9a88f2018-10-01 12:22:40 -0600749 panel {
750 compatible = "simple-panel";
751 backlight = <&backlight 0 100>;
752 };
753
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300754 smem@0 {
755 compatible = "sandbox,smem";
756 };
757
Simon Glassd4901892018-12-10 10:37:36 -0700758 sound {
759 compatible = "sandbox,sound";
760 cpu {
761 sound-dai = <&i2s 0>;
762 };
763
764 codec {
765 sound-dai = <&audio 0>;
766 };
767 };
768
Simon Glass0ae0cb72014-10-13 23:42:11 -0600769 spi@0 {
770 #address-cells = <1>;
771 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600772 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600773 compatible = "sandbox,spi";
774 cs-gpios = <0>, <&gpio_a 0>;
775 spi.bin@0 {
776 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000777 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600778 spi-max-frequency = <40000000>;
779 sandbox,filename = "spi.bin";
780 };
781 };
782
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100783 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600784 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200785 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600786 };
787
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100788 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600789 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600790 reg = <0x20 5
791 0x28 6
792 0x30 7
793 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600794 };
795
Patrick Delaunaya442e612019-03-07 09:57:13 +0100796 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900797 compatible = "simple-mfd", "syscon";
798 reg = <0x40 5
799 0x48 6
800 0x50 7
801 0x58 8>;
802 };
803
Thomas Choue7cc8d12015-12-11 16:27:34 +0800804 timer {
805 compatible = "sandbox,timer";
806 clock-frequency = <1000000>;
807 };
808
Miquel Raynalb91ad162018-05-15 11:57:27 +0200809 tpm2 {
810 compatible = "sandbox,tpm2";
811 };
812
Simon Glass171e9912015-05-22 15:42:15 -0600813 uart0: serial {
814 compatible = "sandbox,serial";
815 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500816 };
817
Simon Glasse00cb222015-03-25 12:23:05 -0600818 usb_0: usb@0 {
819 compatible = "sandbox,usb";
820 status = "disabled";
821 hub {
822 compatible = "sandbox,usb-hub";
823 #address-cells = <1>;
824 #size-cells = <0>;
825 flash-stick {
826 reg = <0>;
827 compatible = "sandbox,usb-flash";
828 };
829 };
830 };
831
832 usb_1: usb@1 {
833 compatible = "sandbox,usb";
834 hub {
835 compatible = "usb-hub";
836 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +0200837 #address-cells = <1>;
838 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -0600839 hub-emul {
840 compatible = "sandbox,usb-hub";
841 #address-cells = <1>;
842 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700843 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600844 reg = <0>;
845 compatible = "sandbox,usb-flash";
846 sandbox,filepath = "testflash.bin";
847 };
848
Simon Glass431cbd62015-11-08 23:48:01 -0700849 flash-stick@1 {
850 reg = <1>;
851 compatible = "sandbox,usb-flash";
852 sandbox,filepath = "testflash1.bin";
853 };
854
855 flash-stick@2 {
856 reg = <2>;
857 compatible = "sandbox,usb-flash";
858 sandbox,filepath = "testflash2.bin";
859 };
860
Simon Glassbff1a712015-11-08 23:48:08 -0700861 keyb@3 {
862 reg = <3>;
863 compatible = "sandbox,usb-keyb";
864 };
865
Simon Glasse00cb222015-03-25 12:23:05 -0600866 };
Michael Wallec03b7612020-06-02 01:47:07 +0200867
868 usbstor@1 {
869 reg = <1>;
870 };
871 usbstor@3 {
872 reg = <3>;
873 };
Simon Glasse00cb222015-03-25 12:23:05 -0600874 };
875 };
876
877 usb_2: usb@2 {
878 compatible = "sandbox,usb";
879 status = "disabled";
880 };
881
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200882 spmi: spmi@0 {
883 compatible = "sandbox,spmi";
884 #address-cells = <0x1>;
885 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600886 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200887 pm8916@0 {
888 compatible = "qcom,spmi-pmic";
889 reg = <0x0 0x1>;
890 #address-cells = <0x1>;
891 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600892 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200893
894 spmi_gpios: gpios@c000 {
895 compatible = "qcom,pm8916-gpio";
896 reg = <0xc000 0x400>;
897 gpio-controller;
898 gpio-count = <4>;
899 #gpio-cells = <2>;
900 gpio-bank-name="spmi";
901 };
902 };
903 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700904
905 wdt0: wdt@0 {
906 compatible = "sandbox,wdt";
907 };
Rob Clarkf2006802018-01-10 11:33:30 +0100908
Mario Six957983e2018-08-09 14:51:19 +0200909 axi: axi@0 {
910 compatible = "sandbox,axi";
911 #address-cells = <0x1>;
912 #size-cells = <0x1>;
913 store@0 {
914 compatible = "sandbox,sandbox_store";
915 reg = <0x0 0x400>;
916 };
917 };
918
Rob Clarkf2006802018-01-10 11:33:30 +0100919 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700920 #address-cells = <1>;
921 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -0700922 setting = "sunrise ohoka";
923 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -0700924 int-values = <0x1937 72993>;
Rob Clarkf2006802018-01-10 11:33:30 +0100925 chosen-test {
926 compatible = "denx,u-boot-fdt-test";
927 reg = <9 1>;
928 };
929 };
Mario Sixe8d52912018-03-12 14:53:33 +0100930
931 translation-test@8000 {
932 compatible = "simple-bus";
933 reg = <0x8000 0x4000>;
934
935 #address-cells = <0x2>;
936 #size-cells = <0x1>;
937
938 ranges = <0 0x0 0x8000 0x1000
939 1 0x100 0x9000 0x1000
940 2 0x200 0xA000 0x1000
941 3 0x300 0xB000 0x1000
942 >;
943
Fabien Dessenne641067f2019-05-31 15:11:30 +0200944 dma-ranges = <0 0x000 0x10000000 0x1000
945 1 0x100 0x20000000 0x1000
946 >;
947
Mario Sixe8d52912018-03-12 14:53:33 +0100948 dev@0,0 {
949 compatible = "denx,u-boot-fdt-dummy";
950 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100951 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100952 };
953
954 dev@1,100 {
955 compatible = "denx,u-boot-fdt-dummy";
956 reg = <1 0x100 0x1000>;
957
958 };
959
960 dev@2,200 {
961 compatible = "denx,u-boot-fdt-dummy";
962 reg = <2 0x200 0x1000>;
963 };
964
965
966 noxlatebus@3,300 {
967 compatible = "simple-bus";
968 reg = <3 0x300 0x1000>;
969
970 #address-cells = <0x1>;
971 #size-cells = <0x0>;
972
973 dev@42 {
974 compatible = "denx,u-boot-fdt-dummy";
975 reg = <0x42>;
976 };
977 };
978 };
Mario Six4eea5312018-09-27 09:19:31 +0200979
980 osd {
981 compatible = "sandbox,sandbox_osd";
982 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400983
Mario Sixe6fd0182018-07-31 11:44:13 +0200984 board {
985 compatible = "sandbox,board_sandbox";
986 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200987
988 sandbox_tee {
989 compatible = "sandbox,tee";
990 };
Bin Meng4f89d492018-10-15 02:21:26 -0700991
992 sandbox_virtio1 {
993 compatible = "sandbox,virtio1";
994 };
995
996 sandbox_virtio2 {
997 compatible = "sandbox,virtio2";
998 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200999
1000 pinctrl {
1001 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001002
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&gpios>;
1005
1006 gpios: gpios {
1007 gpio0 {
1008 pins = "GPIO0";
1009 bias-pull-up;
1010 input-disable;
1011 };
1012 gpio1 {
1013 pins = "GPIO1";
1014 output-high;
1015 drive-open-drain;
1016 };
1017 gpio2 {
1018 pins = "GPIO2";
1019 bias-pull-down;
1020 input-enable;
1021 };
1022 gpio3 {
1023 pins = "GPIO3";
1024 bias-disable;
1025 };
1026 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001027 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001028
1029 hwspinlock@0 {
1030 compatible = "sandbox,hwspinlock";
1031 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001032
1033 dma: dma {
1034 compatible = "sandbox,dma";
1035 #dma-cells = <1>;
1036
1037 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1038 dma-names = "m2m", "tx0", "rx0";
1039 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001040
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001041 /*
1042 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1043 * end of the test. If parent mdio is removed first, clean-up of the
1044 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1045 * active at the end of the test. That it turn doesn't allow the mdio
1046 * class to be destroyed, triggering an error.
1047 */
1048 mdio-mux-test {
1049 compatible = "sandbox,mdio-mux";
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 mdio-parent-bus = <&mdio>;
1053
1054 mdio-ch-test@0 {
1055 reg = <0>;
1056 };
1057 mdio-ch-test@1 {
1058 reg = <1>;
1059 };
1060 };
1061
1062 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001063 compatible = "sandbox,mdio";
1064 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001065
1066 pm-bus-test {
1067 compatible = "simple-pm-bus";
1068 clocks = <&clk_sandbox 4>;
1069 power-domains = <&pwrdom 1>;
1070 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001071
1072 resetc2: syscon-reset {
1073 compatible = "syscon-reset";
1074 #reset-cells = <1>;
1075 regmap = <&syscon0>;
1076 offset = <1>;
1077 mask = <0x27FFFFFF>;
1078 assert-high = <0>;
1079 };
1080
1081 syscon-reset-test {
1082 compatible = "sandbox,misc_sandbox";
1083 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1084 reset-names = "valid", "no_mask", "out_of_range";
1085 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001086};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001087
1088#include "sandbox_pmic.dtsi"