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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 93f7f82782cb3d2bd55215ce984887efc6cddfed / . / arch / sandbox / dts / test.dts
blob: 4bccfbe6e1b1d3fe2ac67df60fd1d167b341f795 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100[diff] [blame]3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]6/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]10 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]11
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]12 aliases {
13 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]14 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]15 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]16 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]17 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +0100[diff] [blame]19 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]20 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]21 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]23 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]25 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]26 remoteproc1 = &rproc_1;
27 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]28 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]30 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +0200[diff] [blame]31 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]32 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +0200[diff] [blame]38 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]42 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]45 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]46 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]47 };
48
Simon Glassce6d99a2018-12-10 10:37:33 -0700[diff] [blame]49 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]54 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600[diff] [blame]55 reg = <0 0>;
56 compatible = "google,cros-ec-sandbox";
57
58 /*
59 * This describes the flash memory within the EC. Note
60 * that the STM32L flash erases to 0, not 0xff.
61 */
62 flash {
63 image-pos = <0x08000000>;
64 size = <0x20000>;
65 erase-value = <0>;
66
67 /* Information for sandbox */
68 ro {
69 image-pos = <0>;
70 size = <0xf000>;
71 };
72 wp-ro {
73 image-pos = <0xf000>;
74 size = <0x1000>;
75 };
76 rw {
77 image-pos = <0x10000>;
78 size = <0x10000>;
79 };
80 };
81 };
82
Yannick Fertré23f965a2019-10-07 15:29:05 +0200[diff] [blame]83 dsi_host: dsi_host {
84 compatible = "sandbox,dsi-host";
85 };
86
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]87 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]88 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]89 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]90 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]91 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]92 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100[diff] [blame]93 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
94 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]95 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100[diff] [blame]96 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
97 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
98 <&gpio_b 7 GPIO_IN 3 2 1>,
99 <&gpio_b 8 GPIO_OUT 3 2 1>,
100 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100[diff] [blame]101 test3-gpios =
102 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
103 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
104 <&gpio_c 2 GPIO_OUT>,
105 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
106 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
107 <&gpio_c 5 GPIO_IN>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700[diff] [blame]108 int-value = <1234>;
109 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200[diff] [blame]110 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200[diff] [blame]111 int-array = <5678 9123 4567>;
Simon Glass02554352020-02-06 09:55:00 -0700[diff] [blame]112 interrupts-extended = <&irq 3 0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]113 };
114
115 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]116 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]117 compatible = "not,compatible";
118 };
119
120 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]121 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]122 };
123
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]124 backlight: backlight {
125 compatible = "pwm-backlight";
126 enable-gpios = <&gpio_a 1>;
127 power-supply = <&ldo_1>;
128 pwms = <&pwm 0 1000>;
129 default-brightness-level = <5>;
130 brightness-levels = <0 16 32 64 128 170 202 234 255>;
131 };
132
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200[diff] [blame]133 bind-test {
134 bind-test-child1 {
135 compatible = "sandbox,phy";
136 #phy-cells = <1>;
137 };
138
139 bind-test-child2 {
140 compatible = "simple-bus";
141 };
142 };
143
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]144 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]145 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]146 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]147 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]148 ping-add = <3>;
149 };
150
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200[diff] [blame]151 phy_provider0: gen_phy@0 {
152 compatible = "sandbox,phy";
153 #phy-cells = <1>;
154 };
155
156 phy_provider1: gen_phy@1 {
157 compatible = "sandbox,phy";
158 #phy-cells = <0>;
159 broken;
160 };
161
162 gen_phy_user: gen_phy_user {
163 compatible = "simple-bus";
164 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
165 phy-names = "phy1", "phy2", "phy3";
166 };
167
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]168 some-bus {
169 #address-cells = <1>;
170 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]171 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]172 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]173 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]174 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]175 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]176 compatible = "denx,u-boot-fdt-test";
177 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]178 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]179 ping-add = <5>;
180 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]181 c-test@0 {
182 compatible = "denx,u-boot-fdt-test";
183 reg = <0>;
184 ping-expect = <6>;
185 ping-add = <6>;
186 };
187 c-test@1 {
188 compatible = "denx,u-boot-fdt-test";
189 reg = <1>;
190 ping-expect = <7>;
191 ping-add = <7>;
192 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]193 };
194
195 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]196 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]197 ping-expect = <6>;
198 ping-add = <6>;
199 compatible = "google,another-fdt-test";
200 };
201
202 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]203 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]204 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]205 ping-add = <6>;
206 compatible = "google,another-fdt-test";
207 };
208
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]209 f-test {
210 compatible = "denx,u-boot-fdt-test";
211 };
212
213 g-test {
214 compatible = "denx,u-boot-fdt-test";
215 };
216
Bin Meng2786cd72018-10-10 22:07:01 -0700[diff] [blame]217 h-test {
218 compatible = "denx,u-boot-fdt-test1";
219 };
220
Simon Glassdc12ebb2019-12-29 21:19:25 -0700[diff] [blame]221 devres-test {
222 compatible = "denx,u-boot-devres-test";
223 };
224
Simon Glassf50cc952020-04-08 16:57:34 -0600[diff] [blame]225 acpi-test {
226 compatible = "denx,u-boot-acpi-test";
227 };
228
Simon Glass93f7f822020-04-26 09:19:46 -0600[diff] [blame^]229 acpi-test2 {
230 compatible = "denx,u-boot-acpi-test";
231 };
232
Patrice Chotardee87a092017-09-04 14:55:57 +0200[diff] [blame]233 clocks {
234 clk_fixed: clk-fixed {
235 compatible = "fixed-clock";
236 #clock-cells = <0>;
237 clock-frequency = <1234>;
238 };
Anup Patelb630d572019-02-25 08:14:55 +0000[diff] [blame]239
240 clk_fixed_factor: clk-fixed-factor {
241 compatible = "fixed-factor-clock";
242 #clock-cells = <0>;
243 clock-div = <3>;
244 clock-mult = <2>;
245 clocks = <&clk_fixed>;
246 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200[diff] [blame]247
248 osc {
249 compatible = "fixed-clock";
250 #clock-cells = <0>;
251 clock-frequency = <20000000>;
252 };
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]253 };
254
255 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]256 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]257 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200[diff] [blame]258 assigned-clocks = <&clk_sandbox 3>;
259 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600[diff] [blame]260 };
261
262 clk-test {
263 compatible = "sandbox,clk-test";
264 clocks = <&clk_fixed>,
265 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200[diff] [blame]266 <&clk_sandbox 0>,
267 <&clk_sandbox 3>,
268 <&clk_sandbox 2>;
269 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600[diff] [blame]270 };
271
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200[diff] [blame]272 ccf: clk-ccf {
273 compatible = "sandbox,clk-ccf";
274 };
275
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]276 eth@10002000 {
277 compatible = "sandbox,eth";
278 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]279 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]280 };
281
282 eth_5: eth@10003000 {
283 compatible = "sandbox,eth";
284 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]285 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]286 };
287
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]288 eth_3: sbe5 {
289 compatible = "sandbox,eth";
290 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]291 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700[diff] [blame]292 };
293
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]294 eth@10004000 {
295 compatible = "sandbox,eth";
296 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500[diff] [blame]297 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]298 };
299
Rajan Vaja31b82172018-09-19 03:43:46 -0700[diff] [blame]300 firmware {
301 sandbox_firmware: sandbox-firmware {
302 compatible = "sandbox,firmware";
303 };
304 };
305
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100[diff] [blame]306 pinctrl-gpio {
307 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]308
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100[diff] [blame]309 gpio_a: base-gpios {
310 compatible = "sandbox,gpio";
311 gpio-controller;
312 #gpio-cells = <1>;
313 gpio-bank-name = "a";
314 sandbox,gpio-count = <20>;
315 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]316
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100[diff] [blame]317 gpio_b: extra-gpios {
318 compatible = "sandbox,gpio";
319 gpio-controller;
320 #gpio-cells = <5>;
321 gpio-bank-name = "b";
322 sandbox,gpio-count = <10>;
323 };
324
325 gpio_c: pinmux-gpios {
326 compatible = "sandbox,gpio";
327 gpio-controller;
328 #gpio-cells = <2>;
329 gpio-bank-name = "c";
330 sandbox,gpio-count = <10>;
331 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100[diff] [blame]332 };
333
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]334 i2c@0 {
335 #address-cells = <1>;
336 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]337 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]338 compatible = "sandbox,i2c";
339 clock-frequency = <100000>;
340 eeprom@2c {
341 reg = <0x2c>;
342 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]343 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]344 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]345
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]346 rtc_0: rtc@43 {
347 reg = <0x43>;
348 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]349 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]350 };
351
352 rtc_1: rtc@61 {
353 reg = <0x61>;
354 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]355 sandbox,emul = <&emul1>;
356 };
357
358 i2c_emul: emul {
359 reg = <0xff>;
360 compatible = "sandbox,i2c-emul-parent";
361 emul_eeprom: emul-eeprom {
362 compatible = "sandbox,i2c-eeprom";
363 sandbox,filename = "i2c.bin";
364 sandbox,size = <256>;
365 };
366 emul0: emul0 {
367 compatible = "sandbox,i2c-rtc";
368 };
369 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600[diff] [blame]370 compatible = "sandbox,i2c-rtc";
371 };
372 };
373
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]374 sandbox_pmic: sandbox_pmic {
375 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]376 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]377 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]378
379 mc34708: pmic@41 {
380 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700[diff] [blame]381 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200[diff] [blame]382 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]383 };
384
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100[diff] [blame]385 bootcount@0 {
386 compatible = "u-boot,bootcount-rtc";
387 rtc = <&rtc_1>;
388 offset = <0x13>;
389 };
390
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100[diff] [blame]391 adc@0 {
392 compatible = "sandbox,adc";
393 vdd-supply = <&buck2>;
394 vss-microvolts = <0>;
395 };
396
Simon Glass02554352020-02-06 09:55:00 -0700[diff] [blame]397 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700[diff] [blame]398 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700[diff] [blame]399 interrupt-controller;
400 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700[diff] [blame]401 };
402
Simon Glass3c97c4f2016-01-18 19:52:26 -0700[diff] [blame]403 lcd {
404 u-boot,dm-pre-reloc;
405 compatible = "sandbox,lcd-sdl";
406 xres = <1366>;
407 yres = <768>;
408 };
409
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]410 leds {
411 compatible = "gpio-leds";
412
413 iracibble {
414 gpios = <&gpio_a 1 0>;
415 label = "sandbox:red";
416 };
417
418 martinet {
419 gpios = <&gpio_a 2 0>;
420 label = "sandbox:green";
421 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200[diff] [blame]422
423 default_on {
424 gpios = <&gpio_a 5 0>;
425 label = "sandbox:default_on";
426 default-state = "on";
427 };
428
429 default_off {
430 gpios = <&gpio_a 6 0>;
431 label = "sandbox:default_off";
432 default-state = "off";
433 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600[diff] [blame]434 };
435
Stephen Warren8961b522016-05-16 17:41:37 -0600[diff] [blame]436 mbox: mbox {
437 compatible = "sandbox,mbox";
438 #mbox-cells = <1>;
439 };
440
441 mbox-test {
442 compatible = "sandbox,mbox-test";
443 mboxes = <&mbox 100>, <&mbox 1>;
444 mbox-names = "other", "test";
445 };
446
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]447 cpus {
448 cpu-test1 {
449 compatible = "sandbox,cpu_sandbox";
450 u-boot,dm-pre-reloc;
451 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]452
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]453 cpu-test2 {
454 compatible = "sandbox,cpu_sandbox";
455 u-boot,dm-pre-reloc;
456 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]457
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900[diff] [blame]458 cpu-test3 {
459 compatible = "sandbox,cpu_sandbox";
460 u-boot,dm-pre-reloc;
461 };
Mario Sixfa44b532018-08-06 10:23:44 +0200[diff] [blame]462 };
463
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]464 i2s: i2s {
465 compatible = "sandbox,i2s";
466 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700[diff] [blame]467 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700[diff] [blame]468 };
469
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200[diff] [blame]470 nop-test_0 {
471 compatible = "sandbox,nop_sandbox1";
472 nop-test_1 {
473 compatible = "sandbox,nop_sandbox2";
474 bind = "True";
475 };
476 nop-test_2 {
477 compatible = "sandbox,nop_sandbox2";
478 bind = "False";
479 };
480 };
481
Mario Six004e67c2018-07-31 14:24:14 +0200[diff] [blame]482 misc-test {
483 compatible = "sandbox,misc_sandbox";
484 };
485
Simon Glasse48eeb92017-04-23 20:02:07 -0600[diff] [blame]486 mmc2 {
487 compatible = "sandbox,mmc";
488 };
489
490 mmc1 {
491 compatible = "sandbox,mmc";
492 };
493
494 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600[diff] [blame]495 compatible = "sandbox,mmc";
496 };
497
Simon Glassb45c8332019-02-16 20:24:50 -0700[diff] [blame]498 pch {
499 compatible = "sandbox,pch";
500 };
501
Tom Rini42c64d12020-02-11 12:41:23 -0500[diff] [blame]502 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]503 compatible = "sandbox,pci";
504 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500[diff] [blame]505 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]506 #address-cells = <3>;
507 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600[diff] [blame]508 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]509 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]510 pci@0,0 {
511 compatible = "pci-generic";
512 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]513 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700[diff] [blame]514 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300[diff] [blame]515 pci@1,0 {
516 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600[diff] [blame]517 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
518 reg = <0x02000814 0 0 0 0
519 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]520 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300[diff] [blame]521 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700[diff] [blame]522 p2sb-pci@2,0 {
523 compatible = "sandbox,p2sb";
524 reg = <0x02001010 0 0 0 0>;
525 sandbox,emul = <&p2sb_emul>;
526
527 adder {
528 intel,p2sb-port-id = <3>;
529 compatible = "sandbox,adder";
530 };
531 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700[diff] [blame]532 pci@1e,0 {
533 compatible = "sandbox,pmc";
534 reg = <0xf000 0 0 0 0>;
535 sandbox,emul = <&pmc_emul1e>;
536 acpi-base = <0x400>;
537 gpe0-dwx-mask = <0xf>;
538 gpe0-dwx-shift-base = <4>;
539 gpe0-dw = <6 7 9>;
540 gpe0-sts = <0x20>;
541 gpe0-en = <0x30>;
542 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]543 pci@1f,0 {
544 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600[diff] [blame]545 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
546 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]547 sandbox,emul = <&swap_case_emul0_1f>;
548 };
549 };
550
551 pci-emul0 {
552 compatible = "sandbox,pci-emul-parent";
553 swap_case_emul0_0: emul0@0,0 {
554 compatible = "sandbox,swap-case";
555 };
556 swap_case_emul0_1: emul0@1,0 {
557 compatible = "sandbox,swap-case";
558 use-ea;
559 };
560 swap_case_emul0_1f: emul0@1f,0 {
561 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]562 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700[diff] [blame]563 p2sb_emul: emul@2,0 {
564 compatible = "sandbox,p2sb-emul";
565 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700[diff] [blame]566 pmc_emul1e: emul@1e,0 {
567 compatible = "sandbox,pmc-emul";
568 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame]569 };
570
Tom Rini42c64d12020-02-11 12:41:23 -0500[diff] [blame]571 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]572 compatible = "sandbox,pci";
573 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500[diff] [blame]574 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]575 #address-cells = <3>;
576 #size-cells = <2>;
577 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
578 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700[diff] [blame]579 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200[diff] [blame]580 0x0c 0x00 0x1234 0x5678
581 0x10 0x00 0x1234 0x5678>;
582 pci@10,0 {
583 reg = <0x8000 0 0 0 0>;
584 };
Bin Mengdee4d752018-08-03 01:14:41 -0700[diff] [blame]585 };
586
Tom Rini42c64d12020-02-11 12:41:23 -0500[diff] [blame]587 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]588 compatible = "sandbox,pci";
589 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500[diff] [blame]590 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]591 #address-cells = <3>;
592 #size-cells = <2>;
593 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
594 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
595 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
596 pci@1f,0 {
597 compatible = "pci-generic";
598 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600[diff] [blame]599 sandbox,emul = <&swap_case_emul2_1f>;
600 };
601 };
602
603 pci-emul2 {
604 compatible = "sandbox,pci-emul-parent";
605 swap_case_emul2_1f: emul2@1f,0 {
606 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700[diff] [blame]607 };
608 };
609
Ramon Friedbb413332019-04-27 11:15:23 +0300[diff] [blame]610 pci_ep: pci_ep {
611 compatible = "sandbox,pci_ep";
612 };
613
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]614 probing {
615 compatible = "simple-bus";
616 test1 {
617 compatible = "denx,u-boot-probe-test";
618 };
619
620 test2 {
621 compatible = "denx,u-boot-probe-test";
622 };
623
624 test3 {
625 compatible = "denx,u-boot-probe-test";
626 };
627
628 test4 {
629 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]630 first-syscon = <&syscon0>;
631 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100[diff] [blame]632 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600[diff] [blame]633 };
634 };
635
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600[diff] [blame]636 pwrdom: power-domain {
637 compatible = "sandbox,power-domain";
638 #power-domain-cells = <1>;
639 };
640
641 power-domain-test {
642 compatible = "sandbox,power-domain-test";
643 power-domains = <&pwrdom 2>;
644 };
645
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]646 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]647 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]648 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]649 };
650
651 pwm2 {
652 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]653 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600[diff] [blame]654 };
655
Simon Glass64ce0ca2015-07-06 12:54:31 -0600[diff] [blame]656 ram {
657 compatible = "sandbox,ram";
658 };
659
Simon Glass5010d982015-07-06 12:54:29 -0600[diff] [blame]660 reset@0 {
661 compatible = "sandbox,warm-reset";
662 };
663
664 reset@1 {
665 compatible = "sandbox,reset";
666 };
667
Stephen Warren4581b712016-06-17 09:43:59 -0600[diff] [blame]668 resetc: reset-ctl {
669 compatible = "sandbox,reset-ctl";
670 #reset-cells = <1>;
671 };
672
673 reset-ctl-test {
674 compatible = "sandbox,reset-ctl-test";
675 resets = <&resetc 100>, <&resetc 2>;
676 reset-names = "other", "test";
677 };
678
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530[diff] [blame]679 rng {
680 compatible = "sandbox,sandbox-rng";
681 };
682
Nishanth Menon52159402015-09-17 15:42:41 -0500[diff] [blame]683 rproc_1: rproc@1 {
684 compatible = "sandbox,test-processor";
685 remoteproc-name = "remoteproc-test-dev1";
686 };
687
688 rproc_2: rproc@2 {
689 compatible = "sandbox,test-processor";
690 internal-memory-mapped;
691 remoteproc-name = "remoteproc-test-dev2";
692 };
693
Simon Glass5d9a88f2018-10-01 12:22:40 -0600[diff] [blame]694 panel {
695 compatible = "simple-panel";
696 backlight = <&backlight 0 100>;
697 };
698
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300[diff] [blame]699 smem@0 {
700 compatible = "sandbox,smem";
701 };
702
Simon Glassd4901892018-12-10 10:37:36 -0700[diff] [blame]703 sound {
704 compatible = "sandbox,sound";
705 cpu {
706 sound-dai = <&i2s 0>;
707 };
708
709 codec {
710 sound-dai = <&audio 0>;
711 };
712 };
713
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]714 spi@0 {
715 #address-cells = <1>;
716 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]717 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]718 compatible = "sandbox,spi";
719 cs-gpios = <0>, <&gpio_a 0>;
720 spi.bin@0 {
721 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000[diff] [blame]722 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]723 spi-max-frequency = <40000000>;
724 sandbox,filename = "spi.bin";
725 };
726 };
727
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]728 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]729 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200[diff] [blame]730 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]731 };
732
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100[diff] [blame]733 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]734 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600[diff] [blame]735 reg = <0x20 5
736 0x28 6
737 0x30 7
738 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600[diff] [blame]739 };
740
Patrick Delaunaya442e612019-03-07 09:57:13 +0100[diff] [blame]741 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900[diff] [blame]742 compatible = "simple-mfd", "syscon";
743 reg = <0x40 5
744 0x48 6
745 0x50 7
746 0x58 8>;
747 };
748
Thomas Choue7cc8d12015-12-11 16:27:34 +0800[diff] [blame]749 timer {
750 compatible = "sandbox,timer";
751 clock-frequency = <1000000>;
752 };
753
Miquel Raynalb91ad162018-05-15 11:57:27 +0200[diff] [blame]754 tpm2 {
755 compatible = "sandbox,tpm2";
756 };
757
Simon Glass171e9912015-05-22 15:42:15 -0600[diff] [blame]758 uart0: serial {
759 compatible = "sandbox,serial";
760 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500[diff] [blame]761 };
762
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]763 usb_0: usb@0 {
764 compatible = "sandbox,usb";
765 status = "disabled";
766 hub {
767 compatible = "sandbox,usb-hub";
768 #address-cells = <1>;
769 #size-cells = <0>;
770 flash-stick {
771 reg = <0>;
772 compatible = "sandbox,usb-flash";
773 };
774 };
775 };
776
777 usb_1: usb@1 {
778 compatible = "sandbox,usb";
779 hub {
780 compatible = "usb-hub";
781 usb,device-class = <9>;
782 hub-emul {
783 compatible = "sandbox,usb-hub";
784 #address-cells = <1>;
785 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]786 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]787 reg = <0>;
788 compatible = "sandbox,usb-flash";
789 sandbox,filepath = "testflash.bin";
790 };
791
Simon Glass431cbd62015-11-08 23:48:01 -0700[diff] [blame]792 flash-stick@1 {
793 reg = <1>;
794 compatible = "sandbox,usb-flash";
795 sandbox,filepath = "testflash1.bin";
796 };
797
798 flash-stick@2 {
799 reg = <2>;
800 compatible = "sandbox,usb-flash";
801 sandbox,filepath = "testflash2.bin";
802 };
803
Simon Glassbff1a712015-11-08 23:48:08 -0700[diff] [blame]804 keyb@3 {
805 reg = <3>;
806 compatible = "sandbox,usb-keyb";
807 };
808
Simon Glasse00cb222015-03-25 12:23:05 -0600[diff] [blame]809 };
810 };
811 };
812
813 usb_2: usb@2 {
814 compatible = "sandbox,usb";
815 status = "disabled";
816 };
817
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]818 spmi: spmi@0 {
819 compatible = "sandbox,spmi";
820 #address-cells = <0x1>;
821 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600[diff] [blame]822 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]823 pm8916@0 {
824 compatible = "qcom,spmi-pmic";
825 reg = <0x0 0x1>;
826 #address-cells = <0x1>;
827 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600[diff] [blame]828 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200[diff] [blame]829
830 spmi_gpios: gpios@c000 {
831 compatible = "qcom,pm8916-gpio";
832 reg = <0xc000 0x400>;
833 gpio-controller;
834 gpio-count = <4>;
835 #gpio-cells = <2>;
836 gpio-bank-name="spmi";
837 };
838 };
839 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700[diff] [blame]840
841 wdt0: wdt@0 {
842 compatible = "sandbox,wdt";
843 };
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]844
Mario Six957983e2018-08-09 14:51:19 +0200[diff] [blame]845 axi: axi@0 {
846 compatible = "sandbox,axi";
847 #address-cells = <0x1>;
848 #size-cells = <0x1>;
849 store@0 {
850 compatible = "sandbox,sandbox_store";
851 reg = <0x0 0x400>;
852 };
853 };
854
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]855 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700[diff] [blame]856 #address-cells = <1>;
857 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -0700[diff] [blame]858 setting = "sunrise ohoka";
859 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -0700[diff] [blame]860 int-values = <0x1937 72993>;
Rob Clarkf2006802018-01-10 11:33:30 +0100[diff] [blame]861 chosen-test {
862 compatible = "denx,u-boot-fdt-test";
863 reg = <9 1>;
864 };
865 };
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]866
867 translation-test@8000 {
868 compatible = "simple-bus";
869 reg = <0x8000 0x4000>;
870
871 #address-cells = <0x2>;
872 #size-cells = <0x1>;
873
874 ranges = <0 0x0 0x8000 0x1000
875 1 0x100 0x9000 0x1000
876 2 0x200 0xA000 0x1000
877 3 0x300 0xB000 0x1000
878 >;
879
Fabien Dessenne641067f2019-05-31 15:11:30 +0200[diff] [blame]880 dma-ranges = <0 0x000 0x10000000 0x1000
881 1 0x100 0x20000000 0x1000
882 >;
883
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]884 dev@0,0 {
885 compatible = "denx,u-boot-fdt-dummy";
886 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100[diff] [blame]887 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100[diff] [blame]888 };
889
890 dev@1,100 {
891 compatible = "denx,u-boot-fdt-dummy";
892 reg = <1 0x100 0x1000>;
893
894 };
895
896 dev@2,200 {
897 compatible = "denx,u-boot-fdt-dummy";
898 reg = <2 0x200 0x1000>;
899 };
900
901
902 noxlatebus@3,300 {
903 compatible = "simple-bus";
904 reg = <3 0x300 0x1000>;
905
906 #address-cells = <0x1>;
907 #size-cells = <0x0>;
908
909 dev@42 {
910 compatible = "denx,u-boot-fdt-dummy";
911 reg = <0x42>;
912 };
913 };
914 };
Mario Six4eea5312018-09-27 09:19:31 +0200[diff] [blame]915
916 osd {
917 compatible = "sandbox,sandbox_osd";
918 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400[diff] [blame]919
Mario Sixe6fd0182018-07-31 11:44:13 +0200[diff] [blame]920 board {
921 compatible = "sandbox,board_sandbox";
922 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200[diff] [blame]923
924 sandbox_tee {
925 compatible = "sandbox,tee";
926 };
Bin Meng4f89d492018-10-15 02:21:26 -0700[diff] [blame]927
928 sandbox_virtio1 {
929 compatible = "sandbox,virtio1";
930 };
931
932 sandbox_virtio2 {
933 compatible = "sandbox,virtio2";
934 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200[diff] [blame]935
936 pinctrl {
937 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +0100[diff] [blame]938
939 pinctrl-names = "default";
940 pinctrl-0 = <&gpios>;
941
942 gpios: gpios {
943 gpio0 {
944 pins = "GPIO0";
945 bias-pull-up;
946 input-disable;
947 };
948 gpio1 {
949 pins = "GPIO1";
950 output-high;
951 drive-open-drain;
952 };
953 gpio2 {
954 pins = "GPIO2";
955 bias-pull-down;
956 input-enable;
957 };
958 gpio3 {
959 pins = "GPIO3";
960 bias-disable;
961 };
962 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200[diff] [blame]963 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +0100[diff] [blame]964
965 hwspinlock@0 {
966 compatible = "sandbox,hwspinlock";
967 };
Grygorii Strashkob3309912018-11-28 19:17:51 +0100[diff] [blame]968
969 dma: dma {
970 compatible = "sandbox,dma";
971 #dma-cells = <1>;
972
973 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
974 dma-names = "m2m", "tx0", "rx0";
975 };
Alex Margineanec9594a2019-06-03 19:12:28 +0300[diff] [blame]976
Alex Margineanc3d9f3f2019-07-12 10:13:53 +0300[diff] [blame]977 /*
978 * keep mdio-mux ahead of mdio so that the mux is removed first at the
979 * end of the test. If parent mdio is removed first, clean-up of the
980 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
981 * active at the end of the test. That it turn doesn't allow the mdio
982 * class to be destroyed, triggering an error.
983 */
984 mdio-mux-test {
985 compatible = "sandbox,mdio-mux";
986 #address-cells = <1>;
987 #size-cells = <0>;
988 mdio-parent-bus = <&mdio>;
989
990 mdio-ch-test@0 {
991 reg = <0>;
992 };
993 mdio-ch-test@1 {
994 reg = <1>;
995 };
996 };
997
998 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +0300[diff] [blame]999 compatible = "sandbox,mdio";
1000 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1001};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200[diff] [blame]1002
1003#include "sandbox_pmic.dtsi"