blob: 6b1f10d9a0ebfcc25630ec1cfe02245908ed421a [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "MIPS architecture"
2 depends on MIPS
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "mips"
6
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +01007config SYS_CPU
Paul Burton20286cd2016-05-16 10:52:11 +01008 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
Daniel Schwierzeckb9863b62014-10-26 14:14:07 +010010
Masahiro Yamadadd840582014-07-30 14:08:14 +090011choice
12 prompt "Target select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050013 optional
Masahiro Yamadadd840582014-07-30 14:08:14 +090014
Masahiro Yamadadd840582014-07-30 14:08:14 +090015config TARGET_MALTA
16 bool "Support malta"
Daniel Schwierzeck526ceb42021-07-15 20:54:01 +020017 select BOARD_EARLY_INIT_R
Paul Burton6242aa12016-05-17 07:43:28 +010018 select DM
19 select DM_SERIAL
Daniel Schwierzeck526ceb42021-07-15 20:54:01 +020020 select DM_PCI
21 select DM_ETH
Paul Burton05e34252016-01-29 13:54:52 +000022 select DYNAMIC_IO_PORT_BASE
Paul Burton566ce04d2016-09-21 11:18:56 +010023 select MIPS_CM
Daniel Schwierzeckd1c3d8b2018-09-07 19:18:44 +020024 select MIPS_INSERT_BOOT_CONFIG
Michal Simek5ed063d2018-07-23 15:55:13 +020025 select MIPS_L1_CACHE_SHIFT_6
Paul Burton566ce04d2016-09-21 11:18:56 +010026 select MIPS_L2_CACHE
Paul Burton6242aa12016-05-17 07:43:28 +010027 select OF_CONTROL
28 select OF_ISA_BUS
Daniel Schwierzeck526ceb42021-07-15 20:54:01 +020029 select PCI_MAP_SYSTEM_MEMORY
Michal Simek5ed063d2018-07-23 15:55:13 +020030 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010031 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010032 select SUPPORTS_CPU_MIPS32_R1
33 select SUPPORTS_CPU_MIPS32_R2
Paul Burton40ba13c2016-05-16 10:52:14 +010034 select SUPPORTS_CPU_MIPS32_R6
Paul Burton0f832b92016-05-26 14:49:36 +010035 select SUPPORTS_CPU_MIPS64_R1
36 select SUPPORTS_CPU_MIPS64_R2
37 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +020038 select SUPPORTS_LITTLE_ENDIAN
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +010039 select SWAP_IO_SPACE
Michal Simek08a00cb2018-07-23 15:55:14 +020040 imply CMD_DM
Masahiro Yamadadd840582014-07-30 14:08:14 +090041
42config TARGET_VCT
43 bool "Support vct"
Michal Simek5ed063d2018-07-23 15:55:13 +020044 select ROM_EXCEPTION_VECTORS
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +010045 select SUPPORTS_BIG_ENDIAN
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +010046 select SUPPORTS_CPU_MIPS32_R1
47 select SUPPORTS_CPU_MIPS32_R2
Paul Burtondd7c7202015-01-29 01:28:02 +000048 select SYS_MIPS_CACHE_INIT_RAM_LOAD
Masahiro Yamadadd840582014-07-30 14:08:14 +090049
Wills Wang1d3d0f12016-03-16 16:59:52 +080050config ARCH_ATH79
51 bool "Support QCA/Atheros ath79"
Wills Wang1d3d0f12016-03-16 16:59:52 +080052 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +020053 select OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +020054 imply CMD_DM
Wills Wang1d3d0f12016-03-16 16:59:52 +080055
Gregory CLEMENTdd1033e2018-12-14 16:16:47 +010056config ARCH_MSCC
57 bool "Support MSCC VCore-III"
58 select OF_CONTROL
59 select DM
60
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020061config ARCH_BMIPS
62 bool "Support BMIPS SoCs"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020063 select CLK
64 select CPU
Michal Simek5ed063d2018-07-23 15:55:13 +020065 select DM
66 select OF_CONTROL
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020067 select RAM
68 select SYSRESET
Michal Simek08a00cb2018-07-23 15:55:14 +020069 imply CMD_DM
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +020070
Weijie Gao16b94902019-04-30 11:13:58 +080071config ARCH_MTMIPS
72 bool "Support MediaTek MIPS platforms"
Weijie Gao3f851c92019-09-25 17:45:43 +080073 select CLK
Stefan Roese4c835a62018-09-05 15:12:35 +020074 imply CMD_DM
75 select DISPLAY_CPUINFO
76 select DM
Stefan Roeseb4a6a1b2018-10-09 08:59:09 +020077 imply DM_ETH
78 imply DM_GPIO
Weijie Gao3f851c92019-09-25 17:45:43 +080079 select DM_RESET
Stefan Roese4c835a62018-09-05 15:12:35 +020080 select DM_SERIAL
Weijie Gao3f851c92019-09-25 17:45:43 +080081 select PINCTRL
82 select PINMUX
83 select PINCONF
84 select RESET_MTMIPS
Stefan Roese4c835a62018-09-05 15:12:35 +020085 imply DM_SPI
86 imply DM_SPI_FLASH
Stefan Roese9814fb22019-05-28 08:11:37 +020087 select LAST_STAGE_INIT
Stefan Roese4c835a62018-09-05 15:12:35 +020088 select MIPS_TUNE_24KC
89 select OF_CONTROL
90 select ROM_EXCEPTION_VECTORS
91 select SUPPORTS_CPU_MIPS32_R1
92 select SUPPORTS_CPU_MIPS32_R2
93 select SUPPORTS_LITTLE_ENDIAN
Weijie Gao7a4b6962020-04-21 09:28:47 +020094 select SUPPORT_SPL
Stefan Roese4c835a62018-09-05 15:12:35 +020095
Paul Burtoncd71b1d2018-12-16 19:25:22 -030096config ARCH_JZ47XX
97 bool "Support Ingenic JZ47xx"
98 select SUPPORT_SPL
99 select OF_CONTROL
100 select DM
101
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200102config ARCH_OCTEON
103 bool "Support Marvell Octeon CN7xxx platforms"
104 select CPU_CAVIUM_OCTEON
105 select DISPLAY_CPUINFO
106 select DMA_ADDR_T_64BIT
107 select DM
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200108 select DM_ETH
Stefan Roese10155402020-07-30 13:56:21 +0200109 select DM_GPIO
110 select DM_I2C
111 select DM_SERIAL
112 select DM_SPI
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200113 select MIPS_L2_CACHE
Stefan Roesee9609dc2020-06-30 12:33:17 +0200114 select MIPS_MACH_EARLY_INIT
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200115 select MIPS_TUNE_OCTEON3
116 select ROM_EXCEPTION_VECTORS
117 select SUPPORTS_BIG_ENDIAN
118 select SUPPORTS_CPU_MIPS64_OCTEON
119 select PHYS_64BIT
120 select OF_CONTROL
121 select OF_LIVE
122 imply CMD_DM
123
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530124config MACH_PIC32
125 bool "Support Microchip PIC32"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530126 select DM
Michal Simek5ed063d2018-07-23 15:55:13 +0200127 select OF_CONTROL
Michal Simek08a00cb2018-07-23 15:55:14 +0200128 imply CMD_DM
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530129
Paul Burtonad8783c2016-09-08 07:47:39 +0100130config TARGET_BOSTON
131 bool "Support Boston"
132 select DM
133 select DM_SERIAL
Paul Burtonad8783c2016-09-08 07:47:39 +0100134 select MIPS_CM
135 select MIPS_L1_CACHE_SHIFT_6
136 select MIPS_L2_CACHE
Paul Burtond2b12a52017-04-30 21:22:42 +0200137 select OF_BOARD_SETUP
Michal Simek5ed063d2018-07-23 15:55:13 +0200138 select OF_CONTROL
139 select ROM_EXCEPTION_VECTORS
Paul Burtonad8783c2016-09-08 07:47:39 +0100140 select SUPPORTS_BIG_ENDIAN
Paul Burtonad8783c2016-09-08 07:47:39 +0100141 select SUPPORTS_CPU_MIPS32_R1
142 select SUPPORTS_CPU_MIPS32_R2
143 select SUPPORTS_CPU_MIPS32_R6
144 select SUPPORTS_CPU_MIPS64_R1
145 select SUPPORTS_CPU_MIPS64_R2
146 select SUPPORTS_CPU_MIPS64_R6
Michal Simek5ed063d2018-07-23 15:55:13 +0200147 select SUPPORTS_LITTLE_ENDIAN
Michal Simek08a00cb2018-07-23 15:55:14 +0200148 imply CMD_DM
Paul Burtonad8783c2016-09-08 07:47:39 +0100149
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100150config TARGET_XILFPGA
151 bool "Support Imagination Xilfpga"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100152 select DM
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100153 select DM_ETH
Michal Simek5ed063d2018-07-23 15:55:13 +0200154 select DM_GPIO
155 select DM_SERIAL
156 select MIPS_L1_CACHE_SHIFT_4
157 select OF_CONTROL
158 select ROM_EXCEPTION_VECTORS
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100159 select SUPPORTS_CPU_MIPS32_R1
160 select SUPPORTS_CPU_MIPS32_R2
Michal Simek5ed063d2018-07-23 15:55:13 +0200161 select SUPPORTS_LITTLE_ENDIAN
Michal Simek08a00cb2018-07-23 15:55:14 +0200162 imply CMD_DM
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100163 help
164 This supports IMGTEC MIPSfpga platform
165
Masahiro Yamadadd840582014-07-30 14:08:14 +0900166endchoice
167
Paul Burtonad8783c2016-09-08 07:47:39 +0100168source "board/imgtec/boston/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900169source "board/imgtec/malta/Kconfig"
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +0100170source "board/imgtec/xilfpga/Kconfig"
Wills Wang1d3d0f12016-03-16 16:59:52 +0800171source "arch/mips/mach-ath79/Kconfig"
Gregory CLEMENTdd1033e2018-12-14 16:16:47 +0100172source "arch/mips/mach-mscc/Kconfig"
Álvaro Fernández Rojasee422142017-04-25 00:39:20 +0200173source "arch/mips/mach-bmips/Kconfig"
Paul Burtoncd71b1d2018-12-16 19:25:22 -0300174source "arch/mips/mach-jz47xx/Kconfig"
Purna Chandra Mandal32c1a6e2016-01-28 15:30:10 +0530175source "arch/mips/mach-pic32/Kconfig"
Weijie Gao16b94902019-04-30 11:13:58 +0800176source "arch/mips/mach-mtmips/Kconfig"
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200177source "arch/mips/mach-octeon/Kconfig"
Masahiro Yamadadd840582014-07-30 14:08:14 +0900178
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100179if MIPS
180
181choice
182 prompt "Endianness selection"
183 help
184 Some MIPS boards can be configured for either little or big endian
185 byte order. These modes require different U-Boot images. In general there
186 is one preferred byteorder for a particular system but some systems are
187 just as commonly used in the one or the other endianness.
188
189config SYS_BIG_ENDIAN
190 bool "Big endian"
191 depends on SUPPORTS_BIG_ENDIAN
192
193config SYS_LITTLE_ENDIAN
194 bool "Little endian"
195 depends on SUPPORTS_LITTLE_ENDIAN
196
197endchoice
198
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100199choice
200 prompt "CPU selection"
201 default CPU_MIPS32_R2
202
203config CPU_MIPS32_R1
204 bool "MIPS32 Release 1"
205 depends on SUPPORTS_CPU_MIPS32_R1
206 select 32BIT
207 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100208 Choose this option to build an U-Boot for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100209 MIPS32 architecture.
210
211config CPU_MIPS32_R2
212 bool "MIPS32 Release 2"
213 depends on SUPPORTS_CPU_MIPS32_R2
214 select 32BIT
215 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100216 Choose this option to build an U-Boot for release 2 through 5 of the
217 MIPS32 architecture.
218
219config CPU_MIPS32_R6
220 bool "MIPS32 Release 6"
221 depends on SUPPORTS_CPU_MIPS32_R6
222 select 32BIT
223 help
224 Choose this option to build an U-Boot for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100225 MIPS32 architecture.
226
227config CPU_MIPS64_R1
228 bool "MIPS64 Release 1"
229 depends on SUPPORTS_CPU_MIPS64_R1
230 select 64BIT
231 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100232 Choose this option to build a kernel for release 1 through 5 of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100233 MIPS64 architecture.
234
235config CPU_MIPS64_R2
236 bool "MIPS64 Release 2"
237 depends on SUPPORTS_CPU_MIPS64_R2
238 select 64BIT
239 help
Paul Burtonc52ebea2016-05-16 10:52:12 +0100240 Choose this option to build a kernel for release 2 through 5 of the
241 MIPS64 architecture.
242
243config CPU_MIPS64_R6
244 bool "MIPS64 Release 6"
245 depends on SUPPORTS_CPU_MIPS64_R6
246 select 64BIT
247 help
248 Choose this option to build a kernel for release 6 or later of the
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100249 MIPS64 architecture.
250
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200251config CPU_MIPS64_OCTEON
252 bool "Marvell Octeon series of CPUs"
253 depends on SUPPORTS_CPU_MIPS64_OCTEON
254 select 64BIT
255 help
256 Choose this option for Marvell Octeon CPUs. These CPUs are between
257 MIPS64 R5 and R6 with other extensions.
258
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100259endchoice
260
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100261menu "General setup"
262
263config ROM_EXCEPTION_VECTORS
264 bool "Build U-Boot image with exception vectors"
265 help
266 Enable this to include exception vectors in the U-Boot image. This is
267 required if the U-Boot entry point is equal to the address of the
268 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
269 U-Boot booted from parallel NOR flash).
270 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
271 In that case the image size will be reduced by 0x500 bytes.
272
Paul Burton939a2552017-05-12 13:26:11 +0200273config MIPS_CM_BASE
274 hex "MIPS CM GCR Base Address"
275 depends on MIPS_CM
Paul Burtoned048e72017-04-30 21:22:41 +0200276 default 0x16100000 if TARGET_BOSTON
Paul Burton939a2552017-05-12 13:26:11 +0200277 default 0x1fbf8000
278 help
279 The physical base address at which to map the MIPS Coherence Manager
280 Global Configuration Registers (GCRs). This should be set such that
281 the GCRs occupy a region of the physical address space which is
282 otherwise unused, or at minimum that software doesn't need to access.
283
Daniel Schwierzeck5ef337a2018-09-07 19:02:05 +0200284config MIPS_CACHE_INDEX_BASE
285 hex "Index base address for cache initialisation"
286 default 0x80000000 if CPU_MIPS32
287 default 0xffffffff80000000 if CPU_MIPS64
288 help
289 This is the base address for a memory block, which is used for
290 initialising the cache lines. This is also the base address of a memory
291 block which is used for loading and filling cache lines when
292 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
293 Normally this is CKSEG0. If the MIPS system needs to move this block
294 to some SRAM or ScratchPad RAM, adapt this option accordingly.
295
Stefan Roesede34a612020-06-30 12:33:16 +0200296config MIPS_MACH_EARLY_INIT
297 bool "Enable mach specific very early init code"
298 help
299 Use this to enable the call to mips_mach_early_init() very early
300 from start.S. This function can be used e.g. to do some very early
301 CPU / SoC intitialization or image copying. Its called very early
302 and at this stage the PC might not match the linking address
303 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
304
Daniel Schwierzeck57bfb1a2020-07-12 00:45:57 +0200305config MIPS_CACHE_SETUP
306 bool "Allow generic start code to initialize and setup caches"
307 default n if SKIP_LOWLEVEL_INIT
308 default y
309 help
310 This allows the generic start code to invoke the generic initialization
311 of the CPU caches. Disabling this can be useful for RAM boot scenarios
312 (EJTAG, SPL payload) or for machines which don't need cache initialization
313 or which want to provide their own cache implementation.
314
315 If unsure, say yes.
316
317config MIPS_CACHE_DISABLE
318 bool "Allow generic start code to initially disable caches"
319 default n if SKIP_LOWLEVEL_INIT
320 default y
321 help
322 This allows the generic start code to initially disable the CPU caches
323 and run uncached until the caches are initialized and enabled. Disabling
324 this can be useful on machines which don't need cache initialization or
325 which want to provide their own cache implementation.
326
327 If unsure, say yes.
328
Daniel Schwierzeck96301462018-11-01 02:02:21 +0100329config MIPS_RELOCATION_TABLE_SIZE
330 hex "Relocation table size"
331 range 0x100 0x10000
332 default "0x8000"
333 ---help---
334 A table of relocation data will be appended to the U-Boot binary
335 and parsed in relocate_code() to fix up all offsets in the relocated
336 U-Boot.
337
338 This option allows the amount of space reserved for the table to be
339 adjusted in a range from 256 up to 64k. The default is 32k and should
340 be ok in most cases. Reduce this value to shrink the size of U-Boot
341 binary.
342
343 The build will fail and a valid size suggested if this is too small.
344
345 If unsure, leave at the default value.
346
Weijie Gao71059732020-04-21 09:28:25 +0200347config RESTORE_EXCEPTION_VECTOR_BASE
348 bool "Restore exception vector base before booting linux kernel"
349 default n
350 help
351 In U-Boot the exception vector base will be moved to top of memory,
352 to be used to display register dump when exception occurs.
353 But some old linux kernel does not honor the base set in CP0_EBASE.
354 A modified exception vector base will cause kernel crash.
355
356 This option will restore the exception vector base to its previous
357 value.
358
359 If unsure, say N.
360
361config OVERRIDE_EXCEPTION_VECTOR_BASE
362 bool "Override the exception vector base to be restored"
363 depends on RESTORE_EXCEPTION_VECTOR_BASE
364 default n
365 help
366 Enable this option if you want to use a different exception vector
367 base rather than the previously saved one.
368
369config NEW_EXCEPTION_VECTOR_BASE
370 hex "New exception vector base"
371 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
372 range 0x80000000 0xbffff000
373 default 0x80000000
374 help
375 The exception vector base to be restored before booting linux kernel
376
Weijie Gaoc95c3ec2020-04-21 09:28:33 +0200377config INIT_STACK_WITHOUT_MALLOC_F
378 bool "Do not reserve malloc space on initial stack"
379 default n
380 help
381 Enable this option if you don't want to reserve malloc space on
382 initial stack. This is useful if the initial stack can't hold large
383 malloc space. Platform should set the malloc_base later when DRAM is
384 ready to use.
385
386config SPL_INIT_STACK_WITHOUT_MALLOC_F
387 bool "Do not reserve malloc space on initial stack in SPL"
388 default n
389 help
390 Enable this option if you don't want to reserve malloc space on
391 initial stack. This is useful if the initial stack can't hold large
392 malloc space. Platform should set the malloc_base later when DRAM is
393 ready to use.
394
Weijie Gao814a8912020-04-21 09:28:37 +0200395config SPL_LOADER_SUPPORT
396 bool
397 default n
398 help
399 Enable this option if you want to use SPL loaders without DM enabled.
400
Daniel Schwierzeckaf3971f2016-02-14 18:52:57 +0100401endmenu
402
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100403menu "OS boot interface"
404
405config MIPS_BOOT_CMDLINE_LEGACY
406 bool "Hand over legacy command line to Linux kernel"
407 default y
408 help
409 Enable this option if you want U-Boot to hand over the Yamon-style
410 command line to the kernel. All bootargs will be prepared as argc/argv
411 compatible list. The argument count (argc) is stored in register $a0.
412 The address of the argument list (argv) is stored in register $a1.
413
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100414config MIPS_BOOT_ENV_LEGACY
415 bool "Hand over legacy environment to Linux kernel"
416 default y
417 help
418 Enable this option if you want U-Boot to hand over the Yamon-style
419 environment to the kernel. Information like memory size, initrd
420 address and size will be prepared as zero-terminated key/value list.
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -0400421 The address of the environment is stored in register $a2.
Daniel Schwierzeckca65e582015-01-14 21:44:13 +0100422
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100423config MIPS_BOOT_FDT
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100424 bool "Hand over a flattened device tree to Linux kernel"
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100425 default n
426 help
427 Enable this option if you want U-Boot to hand over a flattened
Daniel Schwierzeck90b1c9f2015-02-22 16:58:30 +0100428 device tree to the kernel. According to UHI register $a0 will be set
429 to -2 and the FDT address is stored in $a1.
Daniel Schwierzeck5002d8c2015-01-14 21:44:13 +0100430
Daniel Schwierzeck25fc6642015-01-14 21:44:13 +0100431endmenu
432
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100433config SUPPORTS_BIG_ENDIAN
434 bool
435
436config SUPPORTS_LITTLE_ENDIAN
437 bool
438
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100439config SUPPORTS_CPU_MIPS32_R1
440 bool
441
442config SUPPORTS_CPU_MIPS32_R2
443 bool
444
Paul Burtonc52ebea2016-05-16 10:52:12 +0100445config SUPPORTS_CPU_MIPS32_R6
446 bool
447
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100448config SUPPORTS_CPU_MIPS64_R1
449 bool
450
451config SUPPORTS_CPU_MIPS64_R2
452 bool
453
Paul Burtonc52ebea2016-05-16 10:52:12 +0100454config SUPPORTS_CPU_MIPS64_R6
455 bool
456
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200457config SUPPORTS_CPU_MIPS64_OCTEON
458 bool
459
460config CPU_CAVIUM_OCTEON
461 bool
462
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100463config CPU_MIPS32
464 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100465 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100466
467config CPU_MIPS64
468 bool
Paul Burtonc52ebea2016-05-16 10:52:12 +0100469 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200470 default y if CPU_MIPS64_OCTEON
Daniel Schwierzeckc57dafb2015-01-18 21:59:35 +0100471
Daniel Schwierzeck0315a282015-12-26 19:55:37 +0100472config MIPS_TUNE_4KC
473 bool
474
475config MIPS_TUNE_14KC
476 bool
477
478config MIPS_TUNE_24KC
479 bool
480
Daniel Schwierzeck5f9cc362016-05-27 15:39:39 +0200481config MIPS_TUNE_34KC
482 bool
483
Marek Vasut0a0a9582016-05-06 20:10:33 +0200484config MIPS_TUNE_74KC
485 bool
486
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200487config MIPS_TUNE_OCTEON3
488 bool
489
Daniel Schwierzeck02611cb2014-10-26 14:14:07 +0100490config 32BIT
491 bool
492
493config 64BIT
494 bool
495
Daniel Schwierzeck9d638ee2015-01-18 22:00:18 +0100496config SWAP_IO_SPACE
497 bool
498
Paul Burtondd7c7202015-01-29 01:28:02 +0000499config SYS_MIPS_CACHE_INIT_RAM_LOAD
500 bool
501
Daniel Schwierzeck924ad862016-06-04 16:13:21 +0200502config MIPS_INIT_STACK_IN_SRAM
503 bool
504 default n
505 help
506 Select this if the initial stack frame could be setup in SRAM.
507 Normally the initial stack frame is set up in DRAM which is often
508 only available after lowlevel_init. With this option the initial
509 stack frame and the early C environment is set up before
510 lowlevel_init. Thus lowlevel_init does not need to be implemented
511 in assembler.
512
Weijie Gao2434f582020-04-21 09:28:27 +0200513config MIPS_SRAM_INIT
514 bool
515 default n
516 depends on MIPS_INIT_STACK_IN_SRAM
517 help
518 Select this if the SRAM for initial stack needs to be initialized
519 before it can be used. If enabled, a function mips_sram_init() will
520 be called just before setup_stack_gd.
521
Aaron Williams0dc4ab92020-06-30 12:08:56 +0200522config DMA_ADDR_T_64BIT
523 bool
524 help
525 Select this to enable 64-bit DMA addressing
526
Paul Burtonace3be42016-05-27 14:28:04 +0100527config SYS_DCACHE_SIZE
528 int
529 default 0
530 help
531 The total size of the L1 Dcache, if known at compile time.
532
Paul Burton37228622016-05-27 14:28:05 +0100533config SYS_DCACHE_LINE_SIZE
Paul Burton4b7b0a02016-06-09 13:09:52 +0100534 int
Paul Burton37228622016-05-27 14:28:05 +0100535 default 0
536 help
537 The size of L1 Dcache lines, if known at compile time.
538
Paul Burtonace3be42016-05-27 14:28:04 +0100539config SYS_ICACHE_SIZE
540 int
541 default 0
542 help
543 The total size of the L1 ICache, if known at compile time.
544
Paul Burton37228622016-05-27 14:28:05 +0100545config SYS_ICACHE_LINE_SIZE
Paul Burtonace3be42016-05-27 14:28:04 +0100546 int
547 default 0
548 help
Paul Burton37228622016-05-27 14:28:05 +0100549 The size of L1 Icache lines, if known at compile time.
Paul Burtonace3be42016-05-27 14:28:04 +0100550
Ramon Fried22247c62019-06-10 21:05:26 +0300551config SYS_SCACHE_LINE_SIZE
552 int
553 default 0
554 help
555 The size of L2 cache lines, if known at compile time.
556
557
Paul Burtonace3be42016-05-27 14:28:04 +0100558config SYS_CACHE_SIZE_AUTO
559 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
Ramon Fried22247c62019-06-10 21:05:26 +0300560 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
561 SYS_SCACHE_LINE_SIZE = 0
Paul Burtonace3be42016-05-27 14:28:04 +0100562 help
563 Select this (or let it be auto-selected by not defining any cache
564 sizes) in order to allow U-Boot to automatically detect the sizes
565 of caches at runtime. This has a small cost in code size & runtime
566 so if you know the cache configuration for your system at compile
567 time it would be beneficial to configure it.
568
Daniel Schwierzeckf53830e2016-01-09 17:32:50 +0100569config MIPS_L1_CACHE_SHIFT_4
570 bool
571
572config MIPS_L1_CACHE_SHIFT_5
573 bool
574
575config MIPS_L1_CACHE_SHIFT_6
576 bool
577
578config MIPS_L1_CACHE_SHIFT_7
579 bool
580
581config MIPS_L1_CACHE_SHIFT
582 int
583 default "7" if MIPS_L1_CACHE_SHIFT_7
584 default "6" if MIPS_L1_CACHE_SHIFT_6
585 default "5" if MIPS_L1_CACHE_SHIFT_5
586 default "4" if MIPS_L1_CACHE_SHIFT_4
587 default "5"
588
Paul Burton4baa0ab2016-09-21 11:18:54 +0100589config MIPS_L2_CACHE
590 bool
591 help
592 Select this if your system includes an L2 cache and you want U-Boot
593 to initialise & maintain it.
594
Paul Burton05e34252016-01-29 13:54:52 +0000595config DYNAMIC_IO_PORT_BASE
596 bool
597
Paul Burtonb2b135d2016-09-21 11:18:53 +0100598config MIPS_CM
599 bool
600 help
601 Select this if your system contains a MIPS Coherence Manager and you
602 wish U-Boot to configure it or make use of it to retrieve system
603 information such as cache configuration.
604
Daniel Schwierzeckd1c3d8b2018-09-07 19:18:44 +0200605config MIPS_INSERT_BOOT_CONFIG
606 bool
607 default n
608 help
609 Enable this to insert some board-specific boot configuration in
610 the U-Boot binary at offset 0x10.
611
612config MIPS_BOOT_CONFIG_WORD0
613 hex
614 depends on MIPS_INSERT_BOOT_CONFIG
615 default 0x420 if TARGET_MALTA
616 default 0x0
617 help
618 Value which is inserted as boot config word 0.
619
620config MIPS_BOOT_CONFIG_WORD1
621 hex
622 depends on MIPS_INSERT_BOOT_CONFIG
623 default 0x0
624 help
625 Value which is inserted as boot config word 1.
626
Daniel Schwierzeck0e1dc342014-10-26 14:14:07 +0100627endif
628
Masahiro Yamadadd840582014-07-30 14:08:14 +0900629endmenu