blob: 5ce5e28476423a50b615ac5c5f391fbab447ab15 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glass2e7d35d2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070011
Simon Glass00606d72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070025 pci2 = &pci2;
Nishanth Menon52159402015-09-17 15:42:41 -050026 remoteproc1 = &rproc_1;
27 remoteproc2 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060047 };
48
Simon Glassce6d99a2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Simon Glasse96fa6c2018-12-10 10:37:34 -070054 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060055 reg = <0 0>;
56 compatible = "google,cros-ec-sandbox";
57
58 /*
59 * This describes the flash memory within the EC. Note
60 * that the STM32L flash erases to 0, not 0xff.
61 */
62 flash {
63 image-pos = <0x08000000>;
64 size = <0x20000>;
65 erase-value = <0>;
66
67 /* Information for sandbox */
68 ro {
69 image-pos = <0>;
70 size = <0xf000>;
71 };
72 wp-ro {
73 image-pos = <0xf000>;
74 size = <0x1000>;
75 };
76 rw {
77 image-pos = <0x10000>;
78 size = <0x10000>;
79 };
80 };
81 };
82
Yannick Fertré23f965a2019-10-07 15:29:05 +020083 dsi_host: dsi_host {
84 compatible = "sandbox,dsi-host";
85 };
86
Simon Glass2e7d35d2014-02-26 15:59:21 -070087 a-test {
Simon Glass0503e822015-07-06 12:54:36 -060088 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070089 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -060090 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070091 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -060092 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010093 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
94 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -070095 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010096 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
97 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
98 <&gpio_b 7 GPIO_IN 3 2 1>,
99 <&gpio_b 8 GPIO_OUT 3 2 1>,
100 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100101 test3-gpios =
102 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
103 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
104 <&gpio_c 2 GPIO_OUT>,
105 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
106 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200107 <&gpio_c 5 GPIO_IN>,
108 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
109 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700110 int-value = <1234>;
111 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200112 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200113 int-array = <5678 9123 4567>;
Simon Glass02554352020-02-06 09:55:00 -0700114 interrupts-extended = <&irq 3 0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700115 };
116
117 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600118 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700119 compatible = "not,compatible";
120 };
121
122 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600123 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700124 };
125
Simon Glass5d9a88f2018-10-01 12:22:40 -0600126 backlight: backlight {
127 compatible = "pwm-backlight";
128 enable-gpios = <&gpio_a 1>;
129 power-supply = <&ldo_1>;
130 pwms = <&pwm 0 1000>;
131 default-brightness-level = <5>;
132 brightness-levels = <0 16 32 64 128 170 202 234 255>;
133 };
134
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200135 bind-test {
136 bind-test-child1 {
137 compatible = "sandbox,phy";
138 #phy-cells = <1>;
139 };
140
141 bind-test-child2 {
142 compatible = "simple-bus";
143 };
144 };
145
Simon Glass2e7d35d2014-02-26 15:59:21 -0700146 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600147 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700148 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600149 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700150 ping-add = <3>;
151 };
152
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200153 phy_provider0: gen_phy@0 {
154 compatible = "sandbox,phy";
155 #phy-cells = <1>;
156 };
157
158 phy_provider1: gen_phy@1 {
159 compatible = "sandbox,phy";
160 #phy-cells = <0>;
161 broken;
162 };
163
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200164 phy_provider2: gen_phy@2 {
165 compatible = "sandbox,phy";
166 #phy-cells = <0>;
167 };
168
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200169 gen_phy_user: gen_phy_user {
170 compatible = "simple-bus";
171 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
172 phy-names = "phy1", "phy2", "phy3";
173 };
174
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200175 gen_phy_user1: gen_phy_user1 {
176 compatible = "simple-bus";
177 phys = <&phy_provider0 0>, <&phy_provider2>;
178 phy-names = "phy1", "phy2";
179 };
180
Simon Glass2e7d35d2014-02-26 15:59:21 -0700181 some-bus {
182 #address-cells = <1>;
183 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600184 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600185 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600186 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700187 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600188 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700189 compatible = "denx,u-boot-fdt-test";
190 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600191 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700192 ping-add = <5>;
193 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600194 c-test@0 {
195 compatible = "denx,u-boot-fdt-test";
196 reg = <0>;
197 ping-expect = <6>;
198 ping-add = <6>;
199 };
200 c-test@1 {
201 compatible = "denx,u-boot-fdt-test";
202 reg = <1>;
203 ping-expect = <7>;
204 ping-add = <7>;
205 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700206 };
207
208 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600209 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600210 ping-expect = <6>;
211 ping-add = <6>;
212 compatible = "google,another-fdt-test";
213 };
214
215 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600216 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600217 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700218 ping-add = <6>;
219 compatible = "google,another-fdt-test";
220 };
221
Simon Glass9cc36a22015-01-25 08:27:05 -0700222 f-test {
223 compatible = "denx,u-boot-fdt-test";
224 };
225
226 g-test {
227 compatible = "denx,u-boot-fdt-test";
228 };
229
Bin Meng2786cd72018-10-10 22:07:01 -0700230 h-test {
231 compatible = "denx,u-boot-fdt-test1";
232 };
233
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200234 i-test {
235 compatible = "mediatek,u-boot-fdt-test";
236 #address-cells = <1>;
237 #size-cells = <0>;
238
239 subnode@0 {
240 reg = <0>;
241 };
242
243 subnode@1 {
244 reg = <1>;
245 };
246
247 subnode@2 {
248 reg = <2>;
249 };
250 };
251
Simon Glassdc12ebb2019-12-29 21:19:25 -0700252 devres-test {
253 compatible = "denx,u-boot-devres-test";
254 };
255
Simon Glassf50cc952020-04-08 16:57:34 -0600256 acpi-test {
257 compatible = "denx,u-boot-acpi-test";
258 };
259
Simon Glass93f7f822020-04-26 09:19:46 -0600260 acpi-test2 {
261 compatible = "denx,u-boot-acpi-test";
262 };
263
Patrice Chotardee87a092017-09-04 14:55:57 +0200264 clocks {
265 clk_fixed: clk-fixed {
266 compatible = "fixed-clock";
267 #clock-cells = <0>;
268 clock-frequency = <1234>;
269 };
Anup Patelb630d572019-02-25 08:14:55 +0000270
271 clk_fixed_factor: clk-fixed-factor {
272 compatible = "fixed-factor-clock";
273 #clock-cells = <0>;
274 clock-div = <3>;
275 clock-mult = <2>;
276 clocks = <&clk_fixed>;
277 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200278
279 osc {
280 compatible = "fixed-clock";
281 #clock-cells = <0>;
282 clock-frequency = <20000000>;
283 };
Stephen Warren135aa952016-06-17 09:44:00 -0600284 };
285
286 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600287 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600288 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200289 assigned-clocks = <&clk_sandbox 3>;
290 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600291 };
292
293 clk-test {
294 compatible = "sandbox,clk-test";
295 clocks = <&clk_fixed>,
296 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200297 <&clk_sandbox 0>,
298 <&clk_sandbox 3>,
299 <&clk_sandbox 2>;
300 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600301 };
302
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200303 ccf: clk-ccf {
304 compatible = "sandbox,clk-ccf";
305 };
306
Simon Glass171e9912015-05-22 15:42:15 -0600307 eth@10002000 {
308 compatible = "sandbox,eth";
309 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500310 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600311 };
312
313 eth_5: eth@10003000 {
314 compatible = "sandbox,eth";
315 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500316 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600317 };
318
Bin Meng71d79712015-08-27 22:25:53 -0700319 eth_3: sbe5 {
320 compatible = "sandbox,eth";
321 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500322 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700323 };
324
Simon Glass171e9912015-05-22 15:42:15 -0600325 eth@10004000 {
326 compatible = "sandbox,eth";
327 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500328 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600329 };
330
Rajan Vaja31b82172018-09-19 03:43:46 -0700331 firmware {
332 sandbox_firmware: sandbox-firmware {
333 compatible = "sandbox,firmware";
334 };
335 };
336
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100337 pinctrl-gpio {
338 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700339
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100340 gpio_a: base-gpios {
341 compatible = "sandbox,gpio";
342 gpio-controller;
343 #gpio-cells = <1>;
344 gpio-bank-name = "a";
345 sandbox,gpio-count = <20>;
346 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600347
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100348 gpio_b: extra-gpios {
349 compatible = "sandbox,gpio";
350 gpio-controller;
351 #gpio-cells = <5>;
352 gpio-bank-name = "b";
353 sandbox,gpio-count = <10>;
354 };
355
356 gpio_c: pinmux-gpios {
357 compatible = "sandbox,gpio";
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-bank-name = "c";
361 sandbox,gpio-count = <10>;
362 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100363 };
364
Simon Glassecc2ed52014-12-10 08:55:55 -0700365 i2c@0 {
366 #address-cells = <1>;
367 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600368 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700369 compatible = "sandbox,i2c";
370 clock-frequency = <100000>;
371 eeprom@2c {
372 reg = <0x2c>;
373 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700374 sandbox,emul = <&emul_eeprom>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700375 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200376
Simon Glass52d3bc52015-05-22 15:42:17 -0600377 rtc_0: rtc@43 {
378 reg = <0x43>;
379 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700380 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600381 };
382
383 rtc_1: rtc@61 {
384 reg = <0x61>;
385 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700386 sandbox,emul = <&emul1>;
387 };
388
389 i2c_emul: emul {
390 reg = <0xff>;
391 compatible = "sandbox,i2c-emul-parent";
392 emul_eeprom: emul-eeprom {
393 compatible = "sandbox,i2c-eeprom";
394 sandbox,filename = "i2c.bin";
395 sandbox,size = <256>;
396 };
397 emul0: emul0 {
398 compatible = "sandbox,i2c-rtc";
399 };
400 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600401 compatible = "sandbox,i2c-rtc";
402 };
403 };
404
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200405 sandbox_pmic: sandbox_pmic {
406 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700407 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200408 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200409
410 mc34708: pmic@41 {
411 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700412 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200413 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700414 };
415
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100416 bootcount@0 {
417 compatible = "u-boot,bootcount-rtc";
418 rtc = <&rtc_1>;
419 offset = <0x13>;
420 };
421
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100422 adc@0 {
423 compatible = "sandbox,adc";
424 vdd-supply = <&buck2>;
425 vss-microvolts = <0>;
426 };
427
Simon Glass02554352020-02-06 09:55:00 -0700428 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700429 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700430 interrupt-controller;
431 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700432 };
433
Simon Glass3c97c4f2016-01-18 19:52:26 -0700434 lcd {
435 u-boot,dm-pre-reloc;
436 compatible = "sandbox,lcd-sdl";
437 xres = <1366>;
438 yres = <768>;
439 };
440
Simon Glass3c43fba2015-07-06 12:54:34 -0600441 leds {
442 compatible = "gpio-leds";
443
444 iracibble {
445 gpios = <&gpio_a 1 0>;
446 label = "sandbox:red";
447 };
448
449 martinet {
450 gpios = <&gpio_a 2 0>;
451 label = "sandbox:green";
452 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200453
454 default_on {
455 gpios = <&gpio_a 5 0>;
456 label = "sandbox:default_on";
457 default-state = "on";
458 };
459
460 default_off {
461 gpios = <&gpio_a 6 0>;
462 label = "sandbox:default_off";
463 default-state = "off";
464 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600465 };
466
Stephen Warren8961b522016-05-16 17:41:37 -0600467 mbox: mbox {
468 compatible = "sandbox,mbox";
469 #mbox-cells = <1>;
470 };
471
472 mbox-test {
473 compatible = "sandbox,mbox-test";
474 mboxes = <&mbox 100>, <&mbox 1>;
475 mbox-names = "other", "test";
476 };
477
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900478 cpus {
479 cpu-test1 {
480 compatible = "sandbox,cpu_sandbox";
481 u-boot,dm-pre-reloc;
482 };
Mario Sixfa44b532018-08-06 10:23:44 +0200483
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900484 cpu-test2 {
485 compatible = "sandbox,cpu_sandbox";
486 u-boot,dm-pre-reloc;
487 };
Mario Sixfa44b532018-08-06 10:23:44 +0200488
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900489 cpu-test3 {
490 compatible = "sandbox,cpu_sandbox";
491 u-boot,dm-pre-reloc;
492 };
Mario Sixfa44b532018-08-06 10:23:44 +0200493 };
494
Simon Glasse96fa6c2018-12-10 10:37:34 -0700495 i2s: i2s {
496 compatible = "sandbox,i2s";
497 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700498 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700499 };
500
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200501 nop-test_0 {
502 compatible = "sandbox,nop_sandbox1";
503 nop-test_1 {
504 compatible = "sandbox,nop_sandbox2";
505 bind = "True";
506 };
507 nop-test_2 {
508 compatible = "sandbox,nop_sandbox2";
509 bind = "False";
510 };
511 };
512
Mario Six004e67c2018-07-31 14:24:14 +0200513 misc-test {
514 compatible = "sandbox,misc_sandbox";
515 };
516
Simon Glasse48eeb92017-04-23 20:02:07 -0600517 mmc2 {
518 compatible = "sandbox,mmc";
519 };
520
521 mmc1 {
522 compatible = "sandbox,mmc";
523 };
524
525 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600526 compatible = "sandbox,mmc";
527 };
528
Simon Glassb45c8332019-02-16 20:24:50 -0700529 pch {
530 compatible = "sandbox,pch";
531 };
532
Tom Rini42c64d12020-02-11 12:41:23 -0500533 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700534 compatible = "sandbox,pci";
535 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500536 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700537 #address-cells = <3>;
538 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600539 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700540 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700541 pci@0,0 {
542 compatible = "pci-generic";
543 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600544 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700545 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300546 pci@1,0 {
547 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600548 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
549 reg = <0x02000814 0 0 0 0
550 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600551 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300552 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700553 p2sb-pci@2,0 {
554 compatible = "sandbox,p2sb";
555 reg = <0x02001010 0 0 0 0>;
556 sandbox,emul = <&p2sb_emul>;
557
558 adder {
559 intel,p2sb-port-id = <3>;
560 compatible = "sandbox,adder";
561 };
562 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700563 pci@1e,0 {
564 compatible = "sandbox,pmc";
565 reg = <0xf000 0 0 0 0>;
566 sandbox,emul = <&pmc_emul1e>;
567 acpi-base = <0x400>;
568 gpe0-dwx-mask = <0xf>;
569 gpe0-dwx-shift-base = <4>;
570 gpe0-dw = <6 7 9>;
571 gpe0-sts = <0x20>;
572 gpe0-en = <0x30>;
573 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700574 pci@1f,0 {
575 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600576 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
577 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600578 sandbox,emul = <&swap_case_emul0_1f>;
579 };
580 };
581
582 pci-emul0 {
583 compatible = "sandbox,pci-emul-parent";
584 swap_case_emul0_0: emul0@0,0 {
585 compatible = "sandbox,swap-case";
586 };
587 swap_case_emul0_1: emul0@1,0 {
588 compatible = "sandbox,swap-case";
589 use-ea;
590 };
591 swap_case_emul0_1f: emul0@1f,0 {
592 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700593 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700594 p2sb_emul: emul@2,0 {
595 compatible = "sandbox,p2sb-emul";
596 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700597 pmc_emul1e: emul@1e,0 {
598 compatible = "sandbox,pmc-emul";
599 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700600 };
601
Tom Rini42c64d12020-02-11 12:41:23 -0500602 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700603 compatible = "sandbox,pci";
604 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500605 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700606 #address-cells = <3>;
607 #size-cells = <2>;
608 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
609 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700610 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200611 0x0c 0x00 0x1234 0x5678
612 0x10 0x00 0x1234 0x5678>;
613 pci@10,0 {
614 reg = <0x8000 0 0 0 0>;
615 };
Bin Mengdee4d752018-08-03 01:14:41 -0700616 };
617
Tom Rini42c64d12020-02-11 12:41:23 -0500618 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700619 compatible = "sandbox,pci";
620 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500621 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700622 #address-cells = <3>;
623 #size-cells = <2>;
624 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
625 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
626 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
627 pci@1f,0 {
628 compatible = "pci-generic";
629 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600630 sandbox,emul = <&swap_case_emul2_1f>;
631 };
632 };
633
634 pci-emul2 {
635 compatible = "sandbox,pci-emul-parent";
636 swap_case_emul2_1f: emul2@1f,0 {
637 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700638 };
639 };
640
Ramon Friedbb413332019-04-27 11:15:23 +0300641 pci_ep: pci_ep {
642 compatible = "sandbox,pci_ep";
643 };
644
Simon Glass98561572017-04-23 20:10:44 -0600645 probing {
646 compatible = "simple-bus";
647 test1 {
648 compatible = "denx,u-boot-probe-test";
649 };
650
651 test2 {
652 compatible = "denx,u-boot-probe-test";
653 };
654
655 test3 {
656 compatible = "denx,u-boot-probe-test";
657 };
658
659 test4 {
660 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100661 first-syscon = <&syscon0>;
662 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100663 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600664 };
665 };
666
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600667 pwrdom: power-domain {
668 compatible = "sandbox,power-domain";
669 #power-domain-cells = <1>;
670 };
671
672 power-domain-test {
673 compatible = "sandbox,power-domain-test";
674 power-domains = <&pwrdom 2>;
675 };
676
Simon Glass5d9a88f2018-10-01 12:22:40 -0600677 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600678 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600679 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600680 };
681
682 pwm2 {
683 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600684 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600685 };
686
Simon Glass64ce0ca2015-07-06 12:54:31 -0600687 ram {
688 compatible = "sandbox,ram";
689 };
690
Simon Glass5010d982015-07-06 12:54:29 -0600691 reset@0 {
692 compatible = "sandbox,warm-reset";
693 };
694
695 reset@1 {
696 compatible = "sandbox,reset";
697 };
698
Stephen Warren4581b712016-06-17 09:43:59 -0600699 resetc: reset-ctl {
700 compatible = "sandbox,reset-ctl";
701 #reset-cells = <1>;
702 };
703
704 reset-ctl-test {
705 compatible = "sandbox,reset-ctl-test";
706 resets = <&resetc 100>, <&resetc 2>;
707 reset-names = "other", "test";
708 };
709
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530710 rng {
711 compatible = "sandbox,sandbox-rng";
712 };
713
Nishanth Menon52159402015-09-17 15:42:41 -0500714 rproc_1: rproc@1 {
715 compatible = "sandbox,test-processor";
716 remoteproc-name = "remoteproc-test-dev1";
717 };
718
719 rproc_2: rproc@2 {
720 compatible = "sandbox,test-processor";
721 internal-memory-mapped;
722 remoteproc-name = "remoteproc-test-dev2";
723 };
724
Simon Glass5d9a88f2018-10-01 12:22:40 -0600725 panel {
726 compatible = "simple-panel";
727 backlight = <&backlight 0 100>;
728 };
729
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300730 smem@0 {
731 compatible = "sandbox,smem";
732 };
733
Simon Glassd4901892018-12-10 10:37:36 -0700734 sound {
735 compatible = "sandbox,sound";
736 cpu {
737 sound-dai = <&i2s 0>;
738 };
739
740 codec {
741 sound-dai = <&audio 0>;
742 };
743 };
744
Simon Glass0ae0cb72014-10-13 23:42:11 -0600745 spi@0 {
746 #address-cells = <1>;
747 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600748 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600749 compatible = "sandbox,spi";
750 cs-gpios = <0>, <&gpio_a 0>;
751 spi.bin@0 {
752 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000753 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600754 spi-max-frequency = <40000000>;
755 sandbox,filename = "spi.bin";
756 };
757 };
758
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100759 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600760 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200761 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600762 };
763
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100764 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600765 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600766 reg = <0x20 5
767 0x28 6
768 0x30 7
769 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600770 };
771
Patrick Delaunaya442e612019-03-07 09:57:13 +0100772 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900773 compatible = "simple-mfd", "syscon";
774 reg = <0x40 5
775 0x48 6
776 0x50 7
777 0x58 8>;
778 };
779
Thomas Choue7cc8d12015-12-11 16:27:34 +0800780 timer {
781 compatible = "sandbox,timer";
782 clock-frequency = <1000000>;
783 };
784
Miquel Raynalb91ad162018-05-15 11:57:27 +0200785 tpm2 {
786 compatible = "sandbox,tpm2";
787 };
788
Simon Glass171e9912015-05-22 15:42:15 -0600789 uart0: serial {
790 compatible = "sandbox,serial";
791 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500792 };
793
Simon Glasse00cb222015-03-25 12:23:05 -0600794 usb_0: usb@0 {
795 compatible = "sandbox,usb";
796 status = "disabled";
797 hub {
798 compatible = "sandbox,usb-hub";
799 #address-cells = <1>;
800 #size-cells = <0>;
801 flash-stick {
802 reg = <0>;
803 compatible = "sandbox,usb-flash";
804 };
805 };
806 };
807
808 usb_1: usb@1 {
809 compatible = "sandbox,usb";
810 hub {
811 compatible = "usb-hub";
812 usb,device-class = <9>;
813 hub-emul {
814 compatible = "sandbox,usb-hub";
815 #address-cells = <1>;
816 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700817 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600818 reg = <0>;
819 compatible = "sandbox,usb-flash";
820 sandbox,filepath = "testflash.bin";
821 };
822
Simon Glass431cbd62015-11-08 23:48:01 -0700823 flash-stick@1 {
824 reg = <1>;
825 compatible = "sandbox,usb-flash";
826 sandbox,filepath = "testflash1.bin";
827 };
828
829 flash-stick@2 {
830 reg = <2>;
831 compatible = "sandbox,usb-flash";
832 sandbox,filepath = "testflash2.bin";
833 };
834
Simon Glassbff1a712015-11-08 23:48:08 -0700835 keyb@3 {
836 reg = <3>;
837 compatible = "sandbox,usb-keyb";
838 };
839
Simon Glasse00cb222015-03-25 12:23:05 -0600840 };
841 };
842 };
843
844 usb_2: usb@2 {
845 compatible = "sandbox,usb";
846 status = "disabled";
847 };
848
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200849 spmi: spmi@0 {
850 compatible = "sandbox,spmi";
851 #address-cells = <0x1>;
852 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600853 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200854 pm8916@0 {
855 compatible = "qcom,spmi-pmic";
856 reg = <0x0 0x1>;
857 #address-cells = <0x1>;
858 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600859 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200860
861 spmi_gpios: gpios@c000 {
862 compatible = "qcom,pm8916-gpio";
863 reg = <0xc000 0x400>;
864 gpio-controller;
865 gpio-count = <4>;
866 #gpio-cells = <2>;
867 gpio-bank-name="spmi";
868 };
869 };
870 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700871
872 wdt0: wdt@0 {
873 compatible = "sandbox,wdt";
874 };
Rob Clarkf2006802018-01-10 11:33:30 +0100875
Mario Six957983e2018-08-09 14:51:19 +0200876 axi: axi@0 {
877 compatible = "sandbox,axi";
878 #address-cells = <0x1>;
879 #size-cells = <0x1>;
880 store@0 {
881 compatible = "sandbox,sandbox_store";
882 reg = <0x0 0x400>;
883 };
884 };
885
Rob Clarkf2006802018-01-10 11:33:30 +0100886 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700887 #address-cells = <1>;
888 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -0700889 setting = "sunrise ohoka";
890 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -0700891 int-values = <0x1937 72993>;
Rob Clarkf2006802018-01-10 11:33:30 +0100892 chosen-test {
893 compatible = "denx,u-boot-fdt-test";
894 reg = <9 1>;
895 };
896 };
Mario Sixe8d52912018-03-12 14:53:33 +0100897
898 translation-test@8000 {
899 compatible = "simple-bus";
900 reg = <0x8000 0x4000>;
901
902 #address-cells = <0x2>;
903 #size-cells = <0x1>;
904
905 ranges = <0 0x0 0x8000 0x1000
906 1 0x100 0x9000 0x1000
907 2 0x200 0xA000 0x1000
908 3 0x300 0xB000 0x1000
909 >;
910
Fabien Dessenne641067f2019-05-31 15:11:30 +0200911 dma-ranges = <0 0x000 0x10000000 0x1000
912 1 0x100 0x20000000 0x1000
913 >;
914
Mario Sixe8d52912018-03-12 14:53:33 +0100915 dev@0,0 {
916 compatible = "denx,u-boot-fdt-dummy";
917 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100918 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100919 };
920
921 dev@1,100 {
922 compatible = "denx,u-boot-fdt-dummy";
923 reg = <1 0x100 0x1000>;
924
925 };
926
927 dev@2,200 {
928 compatible = "denx,u-boot-fdt-dummy";
929 reg = <2 0x200 0x1000>;
930 };
931
932
933 noxlatebus@3,300 {
934 compatible = "simple-bus";
935 reg = <3 0x300 0x1000>;
936
937 #address-cells = <0x1>;
938 #size-cells = <0x0>;
939
940 dev@42 {
941 compatible = "denx,u-boot-fdt-dummy";
942 reg = <0x42>;
943 };
944 };
945 };
Mario Six4eea5312018-09-27 09:19:31 +0200946
947 osd {
948 compatible = "sandbox,sandbox_osd";
949 };
Tom Rinid24c1d02018-09-30 18:16:51 -0400950
Mario Sixe6fd0182018-07-31 11:44:13 +0200951 board {
952 compatible = "sandbox,board_sandbox";
953 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +0200954
955 sandbox_tee {
956 compatible = "sandbox,tee";
957 };
Bin Meng4f89d492018-10-15 02:21:26 -0700958
959 sandbox_virtio1 {
960 compatible = "sandbox,virtio1";
961 };
962
963 sandbox_virtio2 {
964 compatible = "sandbox,virtio2";
965 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200966
967 pinctrl {
968 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +0100969
970 pinctrl-names = "default";
971 pinctrl-0 = <&gpios>;
972
973 gpios: gpios {
974 gpio0 {
975 pins = "GPIO0";
976 bias-pull-up;
977 input-disable;
978 };
979 gpio1 {
980 pins = "GPIO1";
981 output-high;
982 drive-open-drain;
983 };
984 gpio2 {
985 pins = "GPIO2";
986 bias-pull-down;
987 input-enable;
988 };
989 gpio3 {
990 pins = "GPIO3";
991 bias-disable;
992 };
993 };
Patrice Chotardf41a8242018-10-24 14:10:23 +0200994 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +0100995
996 hwspinlock@0 {
997 compatible = "sandbox,hwspinlock";
998 };
Grygorii Strashkob3309912018-11-28 19:17:51 +0100999
1000 dma: dma {
1001 compatible = "sandbox,dma";
1002 #dma-cells = <1>;
1003
1004 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1005 dma-names = "m2m", "tx0", "rx0";
1006 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001007
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001008 /*
1009 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1010 * end of the test. If parent mdio is removed first, clean-up of the
1011 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1012 * active at the end of the test. That it turn doesn't allow the mdio
1013 * class to be destroyed, triggering an error.
1014 */
1015 mdio-mux-test {
1016 compatible = "sandbox,mdio-mux";
1017 #address-cells = <1>;
1018 #size-cells = <0>;
1019 mdio-parent-bus = <&mdio>;
1020
1021 mdio-ch-test@0 {
1022 reg = <0>;
1023 };
1024 mdio-ch-test@1 {
1025 reg = <1>;
1026 };
1027 };
1028
1029 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001030 compatible = "sandbox,mdio";
1031 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001032};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001033
1034#include "sandbox_pmic.dtsi"