blob: e1d4ab148f0838d746889775cfbab5bed57838bf [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Siva Durga Prasad Paladugua4d88922016-07-29 15:31:47 +05303config IDENT_STRING
4 default " Allwinner Technology"
5
Simon Glass8f925582016-10-17 20:12:36 -06006config PRE_CONSOLE_BUFFER
7 default y
8
Simon Glass53b5bf32016-09-12 23:18:39 -06009config SPL_GPIO_SUPPORT
10 default y
11
Simon Glass77d2f7f2016-09-12 23:18:41 -060012config SPL_LIBCOMMON_SUPPORT
13 default y
14
Simon Glass1646eba2016-09-12 23:18:42 -060015config SPL_LIBDISK_SUPPORT
16 default y
17
Simon Glasscc4288e2016-09-12 23:18:43 -060018config SPL_LIBGENERIC_SUPPORT
19 default y
20
Simon Glass1fdf7c62016-09-12 23:18:44 -060021config SPL_MMC_SUPPORT
22 default y
23
Simon Glass22537972016-09-12 23:18:54 -060024config SPL_POWER_SUPPORT
25 default y
26
Simon Glasse00f76c2016-09-12 23:18:56 -060027config SPL_SERIAL_SUPPORT
28 default y
29
Hans de Goede44d8ae52015-04-06 20:33:34 +020030# Note only one of these may be selected at a time! But hidden choices are
31# not supported by Kconfig
32config SUNXI_GEN_SUN4I
33 bool
34 ---help---
35 Select this for sunxi SoCs which have resets and clocks set up
36 as the original A10 (mach-sun4i).
37
38config SUNXI_GEN_SUN6I
39 bool
40 ---help---
41 Select this for sunxi SoCs which have sun6i like periphery, like
42 separate ahb reset control registers, custom pmic bus, new style
43 watchdog, etc.
44
45
Ian Campbell2c7e3b92014-10-24 21:20:44 +010046choice
47 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020048 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010049
Ian Campbellc3be2792014-10-24 21:20:45 +010050config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010051 bool "sun4i (Allwinner A10)"
52 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020053 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010054 select SUPPORT_SPL
55
Ian Campbellc3be2792014-10-24 21:20:45 +010056config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010057 bool "sun5i (Allwinner A13)"
58 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020059 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010060 select SUPPORT_SPL
61
Ian Campbellc3be2792014-10-24 21:20:45 +010062config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010063 bool "sun6i (Allwinner A31)"
64 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080065 select CPU_V7_HAS_NONSEC
66 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090067 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020068 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020069 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080070 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010071
Ian Campbellc3be2792014-10-24 21:20:45 +010072config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010073 bool "sun7i (Allwinner A20)"
74 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010075 select CPU_V7_HAS_NONSEC
76 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090077 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020078 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010079 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020080 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010081
Hans de Goede5e6bacd2015-04-06 20:55:39 +020082config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010083 bool "sun8i (Allwinner A23)"
84 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080085 select CPU_V7_HAS_NONSEC
86 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090087 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020088 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010089 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080090 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010091
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053092config MACH_SUN8I_A33
93 bool "sun8i (Allwinner A33)"
94 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080095 select CPU_V7_HAS_NONSEC
96 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090097 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053098 select SUNXI_GEN_SUN6I
99 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800100 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530101
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800102config MACH_SUN8I_A83T
103 bool "sun8i (Allwinner A83T)"
104 select CPU_V7
105 select SUNXI_GEN_SUN6I
106 select SUPPORT_SPL
107
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100108config MACH_SUN8I_H3
109 bool "sun8i (Allwinner H3)"
110 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800111 select CPU_V7_HAS_NONSEC
112 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900113 select ARCH_SUPPORT_PSCI
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100114 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +0100115 select SUPPORT_SPL
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800116 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100117
Hans de Goede1871a8c2015-01-13 19:25:06 +0100118config MACH_SUN9I
119 bool "sun9i (Allwinner A80)"
120 select CPU_V7
121 select SUNXI_GEN_SUN6I
Philipp Tomsicha98c2962016-10-28 18:21:32 +0800122 select SUPPORT_SPL
Hans de Goede1871a8c2015-01-13 19:25:06 +0100123
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800124config MACH_SUN50I
125 bool "sun50i (Allwinner A64)"
126 select ARM64
127 select SUNXI_GEN_SUN6I
128
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100129endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800130
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200131# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
132config MACH_SUN8I
133 bool
vishnupatekar762e24a2015-11-29 01:07:19 +0800134 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200135
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800136config DRAM_TYPE
137 int "sunxi dram type"
138 depends on MACH_SUN8I_A83T
139 default 3
140 ---help---
141 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200142
Hans de Goede37781a12014-11-15 19:46:39 +0100143config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100144 int "sunxi dram clock speed"
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800145 default 792 if MACH_SUN9I
Hans de Goede8ffc4872015-01-17 14:24:55 +0100146 default 312 if MACH_SUN6I || MACH_SUN8I
147 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100148 ---help---
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800149 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
150 must be a multiple of 24. For the sun9i (A80), the tested values
151 (for DDR3-1600) are 312 to 792.
Hans de Goede37781a12014-11-15 19:46:39 +0100152
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200153if MACH_SUN5I || MACH_SUN7I
154config DRAM_MBUS_CLK
155 int "sunxi mbus clock speed"
156 default 300
157 ---help---
158 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
159
160endif
161
Hans de Goede37781a12014-11-15 19:46:39 +0100162config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100163 int "sunxi dram zq value"
164 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
165 default 127 if MACH_SUN7I
Chen-Yu Tsai58b628e2016-10-28 18:21:36 +0800166 default 4145117 if MACH_SUN9I
Hans de Goede37781a12014-11-15 19:46:39 +0100167 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100168 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100169
Hans de Goede8975cdf2015-05-13 15:00:46 +0200170config DRAM_ODT_EN
171 bool "sunxi dram odt enable"
172 default n if !MACH_SUN8I_A23
173 default y if MACH_SUN8I_A23
174 ---help---
175 Select this to enable dram odt (on die termination).
176
Hans de Goede8ffc4872015-01-17 14:24:55 +0100177if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
178config DRAM_EMR1
179 int "sunxi dram emr1 value"
180 default 0 if MACH_SUN4I
181 default 4 if MACH_SUN5I || MACH_SUN7I
182 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100183 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200184
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200185config DRAM_TPR3
186 hex "sunxi dram tpr3 value"
187 default 0
188 ---help---
189 Set the dram controller tpr3 parameter. This parameter configures
190 the delay on the command lane and also phase shifts, which are
191 applied for sampling incoming read data. The default value 0
192 means that no phase/delay adjustments are necessary. Properly
193 configuring this parameter increases reliability at high DRAM
194 clock speeds.
195
196config DRAM_DQS_GATING_DELAY
197 hex "sunxi dram dqs_gating_delay value"
198 default 0
199 ---help---
200 Set the dram controller dqs_gating_delay parmeter. Each byte
201 encodes the DQS gating delay for each byte lane. The delay
202 granularity is 1/4 cycle. For example, the value 0x05060606
203 means that the delay is 5 quarter-cycles for one lane (1.25
204 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
205 The default value 0 means autodetection. The results of hardware
206 autodetection are not very reliable and depend on the chip
207 temperature (sometimes producing different results on cold start
208 and warm reboot). But the accuracy of hardware autodetection
209 is usually good enough, unless running at really high DRAM
210 clocks speeds (up to 600MHz). If unsure, keep as 0.
211
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200212choice
213 prompt "sunxi dram timings"
214 default DRAM_TIMINGS_VENDOR_MAGIC
215 ---help---
216 Select the timings of the DDR3 chips.
217
218config DRAM_TIMINGS_VENDOR_MAGIC
219 bool "Magic vendor timings from Android"
220 ---help---
221 The same DRAM timings as in the Allwinner boot0 bootloader.
222
223config DRAM_TIMINGS_DDR3_1066F_1333H
224 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
225 ---help---
226 Use the timings of the standard JEDEC DDR3-1066F speed bin for
227 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
228 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
229 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
230 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
231 that down binning to DDR3-1066F is supported (because DDR3-1066F
232 uses a bit faster timings than DDR3-1333H).
233
234config DRAM_TIMINGS_DDR3_800E_1066G_1333J
235 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
236 ---help---
237 Use the timings of the slowest possible JEDEC speed bin for the
238 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
239 DDR3-800E, DDR3-1066G or DDR3-1333J.
240
241endchoice
242
Hans de Goede37781a12014-11-15 19:46:39 +0100243endif
244
Hans de Goede8975cdf2015-05-13 15:00:46 +0200245if MACH_SUN8I_A23
246config DRAM_ODT_CORRECTION
247 int "sunxi dram odt correction value"
248 default 0
249 ---help---
250 Set the dram odt correction value (range -255 - 255). In allwinner
251 fex files, this option is found in bits 8-15 of the u32 odt_en variable
252 in the [dram] section. When bit 31 of the odt_en variable is set
253 then the correction is negative. Usually the value for this is 0.
254endif
255
Iain Patone71b4222015-03-28 10:26:38 +0000256config SYS_CLK_FREQ
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200257 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000258 default 912000000 if MACH_SUN7I
Chen-Yu Tsaic53344a2016-10-28 18:21:34 +0800259 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
Iain Patone71b4222015-03-28 10:26:38 +0000260
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800261config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100262 default "sun4i" if MACH_SUN4I
263 default "sun5i" if MACH_SUN5I
264 default "sun6i" if MACH_SUN6I
265 default "sun7i" if MACH_SUN7I
266 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100267 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200268 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200269
Masahiro Yamadadd840582014-07-30 14:08:14 +0900270config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900271 default "sunxi"
272
273config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900274 default "sunxi"
275
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200276config UART0_PORT_F
277 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200278 default n
279 ---help---
280 Repurpose the SD card slot for getting access to the UART0 serial
281 console. Primarily useful only for low level u-boot debugging on
282 tablets, where normal UART0 is difficult to access and requires
283 device disassembly and/or soldering. As the SD card can't be used
284 at the same time, the system can be only booted in the FEL mode.
285 Only enable this if you really know what you are doing.
286
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200287config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900288 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200289 default n
290 ---help---
291 Set this to enable various workarounds for old kernels, this results in
292 sub-optimal settings for newer kernels, only enable if needed.
293
Maxime Ripard44c79872015-10-15 22:04:07 +0200294config MMC
295 depends on !UART0_PORT_F
296 default y if ARCH_SUNXI
297
Hans de Goedecd821132014-10-02 20:29:26 +0200298config MMC0_CD_PIN
299 string "Card detect pin for mmc0"
Chen-Yu Tsaiacdab172016-05-02 10:28:08 +0800300 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200301 default ""
302 ---help---
303 Set the card detect pin for mmc0, leave empty to not use cd. This
304 takes a string in the format understood by sunxi_name_to_gpio, e.g.
305 PH1 for pin 1 of port H.
306
307config MMC1_CD_PIN
308 string "Card detect pin for mmc1"
309 default ""
310 ---help---
311 See MMC0_CD_PIN help text.
312
313config MMC2_CD_PIN
314 string "Card detect pin for mmc2"
315 default ""
316 ---help---
317 See MMC0_CD_PIN help text.
318
319config MMC3_CD_PIN
320 string "Card detect pin for mmc3"
321 default ""
322 ---help---
323 See MMC0_CD_PIN help text.
324
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100325config MMC1_PINS
326 string "Pins for mmc1"
327 default ""
328 ---help---
329 Set the pins used for mmc1, when applicable. This takes a string in the
330 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
331
332config MMC2_PINS
333 string "Pins for mmc2"
334 default ""
335 ---help---
336 See MMC1_PINS help text.
337
338config MMC3_PINS
339 string "Pins for mmc3"
340 default ""
341 ---help---
342 See MMC1_PINS help text.
343
Hans de Goede2ccfac02014-10-02 20:43:50 +0200344config MMC_SUNXI_SLOT_EXTRA
345 int "mmc extra slot number"
346 default -1
347 ---help---
348 sunxi builds always enable mmc0, some boards also have a second sdcard
349 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
350 support for this.
351
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200352config INITIAL_USB_SCAN_DELAY
353 int "delay initial usb scan by x ms to allow builtin devices to init"
354 default 0
355 ---help---
356 Some boards have on board usb devices which need longer than the
357 USB spec's 1 second to connect from board powerup. Set this config
358 option to a non 0 value to add an extra delay before the first usb
359 bus scan.
360
Hans de Goede4458b7a2015-01-07 15:26:06 +0100361config USB0_VBUS_PIN
362 string "Vbus enable pin for usb0 (otg)"
363 default ""
364 ---help---
365 Set the Vbus enable pin for usb0 (otg). This takes a string in the
366 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
367
Hans de Goede52defe82015-02-16 22:13:43 +0100368config USB0_VBUS_DET
369 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100370 default ""
371 ---help---
372 Set the Vbus detect pin for usb0 (otg). This takes a string in the
373 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
374
Hans de Goede48c06c92015-06-14 17:29:53 +0200375config USB0_ID_DET
376 string "ID detect pin for usb0 (otg)"
377 default ""
378 ---help---
379 Set the ID detect pin for usb0 (otg). This takes a string in the
380 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
381
Hans de Goede115200c2014-11-07 16:09:00 +0100382config USB1_VBUS_PIN
383 string "Vbus enable pin for usb1 (ehci0)"
384 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100385 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100386 ---help---
387 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
388 a string in the format understood by sunxi_name_to_gpio, e.g.
389 PH1 for pin 1 of port H.
390
391config USB2_VBUS_PIN
392 string "Vbus enable pin for usb2 (ehci1)"
393 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100394 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100395 ---help---
396 See USB1_VBUS_PIN help text.
397
Hans de Goede60fa6302016-03-18 08:42:01 +0100398config USB3_VBUS_PIN
399 string "Vbus enable pin for usb3 (ehci2)"
400 default ""
401 ---help---
402 See USB1_VBUS_PIN help text.
403
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200404config I2C0_ENABLE
405 bool "Enable I2C/TWI controller 0"
406 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
407 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200408 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200409 ---help---
410 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
411 its clock and setting up the bus. This is especially useful on devices
412 with slaves connected to the bus or with pins exposed through e.g. an
413 expansion port/header.
414
415config I2C1_ENABLE
416 bool "Enable I2C/TWI controller 1"
417 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200418 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200419 ---help---
420 See I2C0_ENABLE help text.
421
422config I2C2_ENABLE
423 bool "Enable I2C/TWI controller 2"
424 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200425 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200426 ---help---
427 See I2C0_ENABLE help text.
428
429if MACH_SUN6I || MACH_SUN7I
430config I2C3_ENABLE
431 bool "Enable I2C/TWI controller 3"
432 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200433 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200434 ---help---
435 See I2C0_ENABLE help text.
436endif
437
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100438if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100439config R_I2C_ENABLE
440 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100441 # This is used for the pmic on H3
442 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200443 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100444 ---help---
445 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100446endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100447
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200448if MACH_SUN7I
449config I2C4_ENABLE
450 bool "Enable I2C/TWI controller 4"
451 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200452 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200453 ---help---
454 See I2C0_ENABLE help text.
455endif
456
Hans de Goede2fcf0332015-04-25 17:25:14 +0200457config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900458 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200459 default n
460 ---help---
461 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
462
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200463config VIDEO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900464 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywarafa855d32016-09-05 01:32:40 +0100465 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200466 default y
467 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100468 Say Y here to add support for using a cfb console on the HDMI, LCD
469 or VGA output found on most sunxi devices. See doc/README.video for
470 info on how to select the video output and mode.
471
Hans de Goede2fbf0912014-12-23 23:04:35 +0100472config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900473 bool "HDMI output support"
Hans de Goede2fbf0912014-12-23 23:04:35 +0100474 depends on VIDEO && !MACH_SUN8I
475 default y
476 ---help---
477 Say Y here to add support for outputting video over HDMI.
478
Hans de Goeded9786d22014-12-25 13:58:06 +0100479config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900480 bool "VGA output support"
Hans de Goeded9786d22014-12-25 13:58:06 +0100481 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
482 default n
483 ---help---
484 Say Y here to add support for outputting video over VGA.
485
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100486config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900487 bool "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800488 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100489 default n
490 ---help---
491 Say Y here to add support for external DACs connected to the parallel
492 LCD interface driving a VGA connector, such as found on the
493 Olimex A13 boards.
494
Hans de Goedefb75d972015-01-25 15:33:07 +0100495config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900496 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100497 depends on VIDEO_VGA_VIA_LCD
498 default n
499 ---help---
500 Say Y here if you've a board which uses opendrain drivers for the vga
501 hsync and vsync signals. Opendrain drivers cannot generate steep enough
502 positive edges for a stable video output, so on boards with opendrain
503 drivers the sync signals must always be active high.
504
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800505config VIDEO_VGA_EXTERNAL_DAC_EN
506 string "LCD panel power enable pin"
507 depends on VIDEO_VGA_VIA_LCD
508 default ""
509 ---help---
510 Set the enable pin for the external VGA DAC. This takes a string in the
511 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
512
Hans de Goede39920c82015-08-03 19:20:26 +0200513config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900514 bool "Composite video output support"
Hans de Goede39920c82015-08-03 19:20:26 +0200515 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
516 default n
517 ---help---
518 Say Y here to add support for outputting composite video.
519
Hans de Goede2dae8002014-12-21 16:28:32 +0100520config VIDEO_LCD_MODE
521 string "LCD panel timing details"
522 depends on VIDEO
523 default ""
524 ---help---
525 LCD panel timing details string, leave empty if there is no LCD panel.
526 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
527 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200528 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100529
Hans de Goede65150322015-01-13 13:21:46 +0100530config VIDEO_LCD_DCLK_PHASE
531 int "LCD panel display clock phase"
532 depends on VIDEO
533 default 1
534 ---help---
535 Select LCD panel display clock phase shift, range 0-3.
536
Hans de Goede2dae8002014-12-21 16:28:32 +0100537config VIDEO_LCD_POWER
538 string "LCD panel power enable pin"
539 depends on VIDEO
540 default ""
541 ---help---
542 Set the power enable pin for the LCD panel. This takes a string in the
543 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
544
Hans de Goede242e3d82015-02-16 17:26:41 +0100545config VIDEO_LCD_RESET
546 string "LCD panel reset pin"
547 depends on VIDEO
548 default ""
549 ---help---
550 Set the reset pin for the LCD panel. This takes a string in the format
551 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
552
Hans de Goede2dae8002014-12-21 16:28:32 +0100553config VIDEO_LCD_BL_EN
554 string "LCD panel backlight enable pin"
555 depends on VIDEO
556 default ""
557 ---help---
558 Set the backlight enable pin for the LCD panel. This takes a string in the
559 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
560 port H.
561
562config VIDEO_LCD_BL_PWM
563 string "LCD panel backlight pwm pin"
564 depends on VIDEO
565 default ""
566 ---help---
567 Set the backlight pwm pin for the LCD panel. This takes a string in the
568 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200569
Hans de Goedea7403ae2015-01-22 21:02:42 +0100570config VIDEO_LCD_BL_PWM_ACTIVE_LOW
571 bool "LCD panel backlight pwm is inverted"
572 depends on VIDEO
573 default y
574 ---help---
575 Set this if the backlight pwm output is active low.
576
Hans de Goede55410082015-02-16 17:23:25 +0100577config VIDEO_LCD_PANEL_I2C
578 bool "LCD panel needs to be configured via i2c"
579 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100580 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200581 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100582 ---help---
583 Say y here if the LCD panel needs to be configured via i2c. This
584 will add a bitbang i2c controller using gpios to talk to the LCD.
585
586config VIDEO_LCD_PANEL_I2C_SDA
587 string "LCD panel i2c interface SDA pin"
588 depends on VIDEO_LCD_PANEL_I2C
589 default "PG12"
590 ---help---
591 Set the SDA pin for the LCD i2c interface. This takes a string in the
592 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
593
594config VIDEO_LCD_PANEL_I2C_SCL
595 string "LCD panel i2c interface SCL pin"
596 depends on VIDEO_LCD_PANEL_I2C
597 default "PG10"
598 ---help---
599 Set the SCL pin for the LCD i2c interface. This takes a string in the
600 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
601
Hans de Goede213480e2015-01-01 22:04:34 +0100602
603# Note only one of these may be selected at a time! But hidden choices are
604# not supported by Kconfig
605config VIDEO_LCD_IF_PARALLEL
606 bool
607
608config VIDEO_LCD_IF_LVDS
609 bool
610
611
612choice
613 prompt "LCD panel support"
614 depends on VIDEO
615 ---help---
616 Select which type of LCD panel to support.
617
618config VIDEO_LCD_PANEL_PARALLEL
619 bool "Generic parallel interface LCD panel"
620 select VIDEO_LCD_IF_PARALLEL
621
622config VIDEO_LCD_PANEL_LVDS
623 bool "Generic lvds interface LCD panel"
624 select VIDEO_LCD_IF_LVDS
625
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200626config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
627 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
628 select VIDEO_LCD_SSD2828
629 select VIDEO_LCD_IF_PARALLEL
630 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200631 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
632
633config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
634 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
635 select VIDEO_LCD_ANX9804
636 select VIDEO_LCD_IF_PARALLEL
637 select VIDEO_LCD_PANEL_I2C
638 ---help---
639 Select this for eDP LCD panels with 4 lanes running at 1.62G,
640 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200641
Hans de Goede27515b22015-01-20 09:23:36 +0100642config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
643 bool "Hitachi tx18d42vm LCD panel"
644 select VIDEO_LCD_HITACHI_TX18D42VM
645 select VIDEO_LCD_IF_LVDS
646 ---help---
647 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
648
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100649config VIDEO_LCD_TL059WV5C0
650 bool "tl059wv5c0 LCD panel"
651 select VIDEO_LCD_PANEL_I2C
652 select VIDEO_LCD_IF_PARALLEL
653 ---help---
654 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
655 Aigo M60/M608/M606 tablets.
656
Hans de Goede213480e2015-01-01 22:04:34 +0100657endchoice
658
659
Hans de Goedec13f60d2015-01-25 12:10:48 +0100660config GMAC_TX_DELAY
661 int "GMAC Transmit Clock Delay Chain"
662 default 0
663 ---help---
664 Set the GMAC Transmit Clock Delay Chain value.
665
Hans de Goedeff42d102015-09-13 13:02:48 +0200666config SPL_STACK_R_ADDR
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200667 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200668 default 0x2fe00000 if MACH_SUN9I
669
Masahiro Yamadadd840582014-07-30 14:08:14 +0900670endif