blob: 76ed46a79046e021d0221c900ad264f85c0b44f7 [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Simon Glass53b5bf32016-09-12 23:18:39 -06003config SPL_GPIO_SUPPORT
4 default y
5
Simon Glass77d2f7f2016-09-12 23:18:41 -06006config SPL_LIBCOMMON_SUPPORT
7 default y
8
Simon Glass1646eba2016-09-12 23:18:42 -06009config SPL_LIBDISK_SUPPORT
10 default y
11
Simon Glasscc4288e2016-09-12 23:18:43 -060012config SPL_LIBGENERIC_SUPPORT
13 default y
14
Simon Glass1fdf7c62016-09-12 23:18:44 -060015config SPL_MMC_SUPPORT
16 default y
17
Simon Glass22537972016-09-12 23:18:54 -060018config SPL_POWER_SUPPORT
19 default y
20
Hans de Goede44d8ae52015-04-06 20:33:34 +020021# Note only one of these may be selected at a time! But hidden choices are
22# not supported by Kconfig
23config SUNXI_GEN_SUN4I
24 bool
25 ---help---
26 Select this for sunxi SoCs which have resets and clocks set up
27 as the original A10 (mach-sun4i).
28
29config SUNXI_GEN_SUN6I
30 bool
31 ---help---
32 Select this for sunxi SoCs which have sun6i like periphery, like
33 separate ahb reset control registers, custom pmic bus, new style
34 watchdog, etc.
35
36
Ian Campbell2c7e3b92014-10-24 21:20:44 +010037choice
38 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020039 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010040
Ian Campbellc3be2792014-10-24 21:20:45 +010041config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010042 bool "sun4i (Allwinner A10)"
43 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020044 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010045 select SUPPORT_SPL
46
Ian Campbellc3be2792014-10-24 21:20:45 +010047config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010048 bool "sun5i (Allwinner A13)"
49 select CPU_V7
Hans de Goede44d8ae52015-04-06 20:33:34 +020050 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010051 select SUPPORT_SPL
52
Ian Campbellc3be2792014-10-24 21:20:45 +010053config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010054 bool "sun6i (Allwinner A31)"
55 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080056 select CPU_V7_HAS_NONSEC
57 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090058 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020059 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020060 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080061 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010062
Ian Campbellc3be2792014-10-24 21:20:45 +010063config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010064 bool "sun7i (Allwinner A20)"
65 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010066 select CPU_V7_HAS_NONSEC
67 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090068 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020069 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010070 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +020071 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010072
Hans de Goede5e6bacd2015-04-06 20:55:39 +020073config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +010074 bool "sun8i (Allwinner A23)"
75 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080076 select CPU_V7_HAS_NONSEC
77 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090078 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020079 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +010080 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080081 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010082
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053083config MACH_SUN8I_A33
84 bool "sun8i (Allwinner A33)"
85 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080086 select CPU_V7_HAS_NONSEC
87 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090088 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053089 select SUNXI_GEN_SUN6I
90 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +080091 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +053092
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +080093config MACH_SUN8I_A83T
94 bool "sun8i (Allwinner A83T)"
95 select CPU_V7
96 select SUNXI_GEN_SUN6I
97 select SUPPORT_SPL
98
Jens Kuske1c27b7d2015-11-17 15:12:58 +010099config MACH_SUN8I_H3
100 bool "sun8i (Allwinner H3)"
101 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800102 select CPU_V7_HAS_NONSEC
103 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900104 select ARCH_SUPPORT_PSCI
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100105 select SUNXI_GEN_SUN6I
Jens Kuske0404d532015-11-17 15:12:59 +0100106 select SUPPORT_SPL
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800107 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100108
Hans de Goede1871a8c2015-01-13 19:25:06 +0100109config MACH_SUN9I
110 bool "sun9i (Allwinner A80)"
111 select CPU_V7
112 select SUNXI_GEN_SUN6I
113
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800114config MACH_SUN50I
115 bool "sun50i (Allwinner A64)"
116 select ARM64
117 select SUNXI_GEN_SUN6I
118
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100119endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800120
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200121# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
122config MACH_SUN8I
123 bool
vishnupatekar762e24a2015-11-29 01:07:19 +0800124 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200125
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800126config DRAM_TYPE
127 int "sunxi dram type"
128 depends on MACH_SUN8I_A83T
129 default 3
130 ---help---
131 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200132
Hans de Goede37781a12014-11-15 19:46:39 +0100133config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100134 int "sunxi dram clock speed"
135 default 312 if MACH_SUN6I || MACH_SUN8I
136 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100137 ---help---
138 Set the dram clock speed, valid range 240 - 480, must be a multiple
Hans de Goedee1a08882015-01-25 11:29:27 +0100139 of 24.
Hans de Goede37781a12014-11-15 19:46:39 +0100140
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200141if MACH_SUN5I || MACH_SUN7I
142config DRAM_MBUS_CLK
143 int "sunxi mbus clock speed"
144 default 300
145 ---help---
146 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
147
148endif
149
Hans de Goede37781a12014-11-15 19:46:39 +0100150config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100151 int "sunxi dram zq value"
152 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
153 default 127 if MACH_SUN7I
Hans de Goede37781a12014-11-15 19:46:39 +0100154 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100155 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100156
Hans de Goede8975cdf2015-05-13 15:00:46 +0200157config DRAM_ODT_EN
158 bool "sunxi dram odt enable"
159 default n if !MACH_SUN8I_A23
160 default y if MACH_SUN8I_A23
161 ---help---
162 Select this to enable dram odt (on die termination).
163
Hans de Goede8ffc4872015-01-17 14:24:55 +0100164if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
165config DRAM_EMR1
166 int "sunxi dram emr1 value"
167 default 0 if MACH_SUN4I
168 default 4 if MACH_SUN5I || MACH_SUN7I
169 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100170 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200171
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200172config DRAM_TPR3
173 hex "sunxi dram tpr3 value"
174 default 0
175 ---help---
176 Set the dram controller tpr3 parameter. This parameter configures
177 the delay on the command lane and also phase shifts, which are
178 applied for sampling incoming read data. The default value 0
179 means that no phase/delay adjustments are necessary. Properly
180 configuring this parameter increases reliability at high DRAM
181 clock speeds.
182
183config DRAM_DQS_GATING_DELAY
184 hex "sunxi dram dqs_gating_delay value"
185 default 0
186 ---help---
187 Set the dram controller dqs_gating_delay parmeter. Each byte
188 encodes the DQS gating delay for each byte lane. The delay
189 granularity is 1/4 cycle. For example, the value 0x05060606
190 means that the delay is 5 quarter-cycles for one lane (1.25
191 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
192 The default value 0 means autodetection. The results of hardware
193 autodetection are not very reliable and depend on the chip
194 temperature (sometimes producing different results on cold start
195 and warm reboot). But the accuracy of hardware autodetection
196 is usually good enough, unless running at really high DRAM
197 clocks speeds (up to 600MHz). If unsure, keep as 0.
198
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200199choice
200 prompt "sunxi dram timings"
201 default DRAM_TIMINGS_VENDOR_MAGIC
202 ---help---
203 Select the timings of the DDR3 chips.
204
205config DRAM_TIMINGS_VENDOR_MAGIC
206 bool "Magic vendor timings from Android"
207 ---help---
208 The same DRAM timings as in the Allwinner boot0 bootloader.
209
210config DRAM_TIMINGS_DDR3_1066F_1333H
211 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
212 ---help---
213 Use the timings of the standard JEDEC DDR3-1066F speed bin for
214 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
215 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
216 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
217 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
218 that down binning to DDR3-1066F is supported (because DDR3-1066F
219 uses a bit faster timings than DDR3-1333H).
220
221config DRAM_TIMINGS_DDR3_800E_1066G_1333J
222 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
223 ---help---
224 Use the timings of the slowest possible JEDEC speed bin for the
225 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
226 DDR3-800E, DDR3-1066G or DDR3-1333J.
227
228endchoice
229
Hans de Goede37781a12014-11-15 19:46:39 +0100230endif
231
Hans de Goede8975cdf2015-05-13 15:00:46 +0200232if MACH_SUN8I_A23
233config DRAM_ODT_CORRECTION
234 int "sunxi dram odt correction value"
235 default 0
236 ---help---
237 Set the dram odt correction value (range -255 - 255). In allwinner
238 fex files, this option is found in bits 8-15 of the u32 odt_en variable
239 in the [dram] section. When bit 31 of the odt_en variable is set
240 then the correction is negative. Usually the value for this is 0.
241endif
242
Iain Patone71b4222015-03-28 10:26:38 +0000243config SYS_CLK_FREQ
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200244 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000245 default 912000000 if MACH_SUN7I
246 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
247
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800248config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100249 default "sun4i" if MACH_SUN4I
250 default "sun5i" if MACH_SUN5I
251 default "sun6i" if MACH_SUN6I
252 default "sun7i" if MACH_SUN7I
253 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100254 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200255 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200256
Masahiro Yamadadd840582014-07-30 14:08:14 +0900257config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900258 default "sunxi"
259
260config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900261 default "sunxi"
262
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200263config UART0_PORT_F
264 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200265 default n
266 ---help---
267 Repurpose the SD card slot for getting access to the UART0 serial
268 console. Primarily useful only for low level u-boot debugging on
269 tablets, where normal UART0 is difficult to access and requires
270 device disassembly and/or soldering. As the SD card can't be used
271 at the same time, the system can be only booted in the FEL mode.
272 Only enable this if you really know what you are doing.
273
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200274config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900275 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200276 default n
277 ---help---
278 Set this to enable various workarounds for old kernels, this results in
279 sub-optimal settings for newer kernels, only enable if needed.
280
Maxime Ripard44c79872015-10-15 22:04:07 +0200281config MMC
282 depends on !UART0_PORT_F
283 default y if ARCH_SUNXI
284
Hans de Goedecd821132014-10-02 20:29:26 +0200285config MMC0_CD_PIN
286 string "Card detect pin for mmc0"
Chen-Yu Tsaiacdab172016-05-02 10:28:08 +0800287 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200288 default ""
289 ---help---
290 Set the card detect pin for mmc0, leave empty to not use cd. This
291 takes a string in the format understood by sunxi_name_to_gpio, e.g.
292 PH1 for pin 1 of port H.
293
294config MMC1_CD_PIN
295 string "Card detect pin for mmc1"
296 default ""
297 ---help---
298 See MMC0_CD_PIN help text.
299
300config MMC2_CD_PIN
301 string "Card detect pin for mmc2"
302 default ""
303 ---help---
304 See MMC0_CD_PIN help text.
305
306config MMC3_CD_PIN
307 string "Card detect pin for mmc3"
308 default ""
309 ---help---
310 See MMC0_CD_PIN help text.
311
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100312config MMC1_PINS
313 string "Pins for mmc1"
314 default ""
315 ---help---
316 Set the pins used for mmc1, when applicable. This takes a string in the
317 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
318
319config MMC2_PINS
320 string "Pins for mmc2"
321 default ""
322 ---help---
323 See MMC1_PINS help text.
324
325config MMC3_PINS
326 string "Pins for mmc3"
327 default ""
328 ---help---
329 See MMC1_PINS help text.
330
Hans de Goede2ccfac02014-10-02 20:43:50 +0200331config MMC_SUNXI_SLOT_EXTRA
332 int "mmc extra slot number"
333 default -1
334 ---help---
335 sunxi builds always enable mmc0, some boards also have a second sdcard
336 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
337 support for this.
338
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200339config INITIAL_USB_SCAN_DELAY
340 int "delay initial usb scan by x ms to allow builtin devices to init"
341 default 0
342 ---help---
343 Some boards have on board usb devices which need longer than the
344 USB spec's 1 second to connect from board powerup. Set this config
345 option to a non 0 value to add an extra delay before the first usb
346 bus scan.
347
Hans de Goede4458b7a2015-01-07 15:26:06 +0100348config USB0_VBUS_PIN
349 string "Vbus enable pin for usb0 (otg)"
350 default ""
351 ---help---
352 Set the Vbus enable pin for usb0 (otg). This takes a string in the
353 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
354
Hans de Goede52defe82015-02-16 22:13:43 +0100355config USB0_VBUS_DET
356 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100357 default ""
358 ---help---
359 Set the Vbus detect pin for usb0 (otg). This takes a string in the
360 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
361
Hans de Goede48c06c92015-06-14 17:29:53 +0200362config USB0_ID_DET
363 string "ID detect pin for usb0 (otg)"
364 default ""
365 ---help---
366 Set the ID detect pin for usb0 (otg). This takes a string in the
367 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
368
Hans de Goede115200c2014-11-07 16:09:00 +0100369config USB1_VBUS_PIN
370 string "Vbus enable pin for usb1 (ehci0)"
371 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100372 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100373 ---help---
374 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
375 a string in the format understood by sunxi_name_to_gpio, e.g.
376 PH1 for pin 1 of port H.
377
378config USB2_VBUS_PIN
379 string "Vbus enable pin for usb2 (ehci1)"
380 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100381 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100382 ---help---
383 See USB1_VBUS_PIN help text.
384
Hans de Goede60fa6302016-03-18 08:42:01 +0100385config USB3_VBUS_PIN
386 string "Vbus enable pin for usb3 (ehci2)"
387 default ""
388 ---help---
389 See USB1_VBUS_PIN help text.
390
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200391config I2C0_ENABLE
392 bool "Enable I2C/TWI controller 0"
393 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
394 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200395 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200396 ---help---
397 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
398 its clock and setting up the bus. This is especially useful on devices
399 with slaves connected to the bus or with pins exposed through e.g. an
400 expansion port/header.
401
402config I2C1_ENABLE
403 bool "Enable I2C/TWI controller 1"
404 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200405 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200406 ---help---
407 See I2C0_ENABLE help text.
408
409config I2C2_ENABLE
410 bool "Enable I2C/TWI controller 2"
411 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200412 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200413 ---help---
414 See I2C0_ENABLE help text.
415
416if MACH_SUN6I || MACH_SUN7I
417config I2C3_ENABLE
418 bool "Enable I2C/TWI controller 3"
419 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200420 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200421 ---help---
422 See I2C0_ENABLE help text.
423endif
424
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100425if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100426config R_I2C_ENABLE
427 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100428 # This is used for the pmic on H3
429 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200430 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100431 ---help---
432 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100433endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100434
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200435if MACH_SUN7I
436config I2C4_ENABLE
437 bool "Enable I2C/TWI controller 4"
438 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200439 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200440 ---help---
441 See I2C0_ENABLE help text.
442endif
443
Hans de Goede2fcf0332015-04-25 17:25:14 +0200444config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900445 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200446 default n
447 ---help---
448 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
449
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200450config VIDEO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900451 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Andre Przywarafa855d32016-09-05 01:32:40 +0100452 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200453 default y
454 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100455 Say Y here to add support for using a cfb console on the HDMI, LCD
456 or VGA output found on most sunxi devices. See doc/README.video for
457 info on how to select the video output and mode.
458
Hans de Goede2fbf0912014-12-23 23:04:35 +0100459config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900460 bool "HDMI output support"
Hans de Goede2fbf0912014-12-23 23:04:35 +0100461 depends on VIDEO && !MACH_SUN8I
462 default y
463 ---help---
464 Say Y here to add support for outputting video over HDMI.
465
Hans de Goeded9786d22014-12-25 13:58:06 +0100466config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900467 bool "VGA output support"
Hans de Goeded9786d22014-12-25 13:58:06 +0100468 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
469 default n
470 ---help---
471 Say Y here to add support for outputting video over VGA.
472
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100473config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900474 bool "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800475 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100476 default n
477 ---help---
478 Say Y here to add support for external DACs connected to the parallel
479 LCD interface driving a VGA connector, such as found on the
480 Olimex A13 boards.
481
Hans de Goedefb75d972015-01-25 15:33:07 +0100482config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900483 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100484 depends on VIDEO_VGA_VIA_LCD
485 default n
486 ---help---
487 Say Y here if you've a board which uses opendrain drivers for the vga
488 hsync and vsync signals. Opendrain drivers cannot generate steep enough
489 positive edges for a stable video output, so on boards with opendrain
490 drivers the sync signals must always be active high.
491
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800492config VIDEO_VGA_EXTERNAL_DAC_EN
493 string "LCD panel power enable pin"
494 depends on VIDEO_VGA_VIA_LCD
495 default ""
496 ---help---
497 Set the enable pin for the external VGA DAC. This takes a string in the
498 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
499
Hans de Goede39920c82015-08-03 19:20:26 +0200500config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900501 bool "Composite video output support"
Hans de Goede39920c82015-08-03 19:20:26 +0200502 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
503 default n
504 ---help---
505 Say Y here to add support for outputting composite video.
506
Hans de Goede2dae8002014-12-21 16:28:32 +0100507config VIDEO_LCD_MODE
508 string "LCD panel timing details"
509 depends on VIDEO
510 default ""
511 ---help---
512 LCD panel timing details string, leave empty if there is no LCD panel.
513 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
514 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200515 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100516
Hans de Goede65150322015-01-13 13:21:46 +0100517config VIDEO_LCD_DCLK_PHASE
518 int "LCD panel display clock phase"
519 depends on VIDEO
520 default 1
521 ---help---
522 Select LCD panel display clock phase shift, range 0-3.
523
Hans de Goede2dae8002014-12-21 16:28:32 +0100524config VIDEO_LCD_POWER
525 string "LCD panel power enable pin"
526 depends on VIDEO
527 default ""
528 ---help---
529 Set the power enable pin for the LCD panel. This takes a string in the
530 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
531
Hans de Goede242e3d82015-02-16 17:26:41 +0100532config VIDEO_LCD_RESET
533 string "LCD panel reset pin"
534 depends on VIDEO
535 default ""
536 ---help---
537 Set the reset pin for the LCD panel. This takes a string in the format
538 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
539
Hans de Goede2dae8002014-12-21 16:28:32 +0100540config VIDEO_LCD_BL_EN
541 string "LCD panel backlight enable pin"
542 depends on VIDEO
543 default ""
544 ---help---
545 Set the backlight enable pin for the LCD panel. This takes a string in the
546 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
547 port H.
548
549config VIDEO_LCD_BL_PWM
550 string "LCD panel backlight pwm pin"
551 depends on VIDEO
552 default ""
553 ---help---
554 Set the backlight pwm pin for the LCD panel. This takes a string in the
555 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200556
Hans de Goedea7403ae2015-01-22 21:02:42 +0100557config VIDEO_LCD_BL_PWM_ACTIVE_LOW
558 bool "LCD panel backlight pwm is inverted"
559 depends on VIDEO
560 default y
561 ---help---
562 Set this if the backlight pwm output is active low.
563
Hans de Goede55410082015-02-16 17:23:25 +0100564config VIDEO_LCD_PANEL_I2C
565 bool "LCD panel needs to be configured via i2c"
566 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100567 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200568 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100569 ---help---
570 Say y here if the LCD panel needs to be configured via i2c. This
571 will add a bitbang i2c controller using gpios to talk to the LCD.
572
573config VIDEO_LCD_PANEL_I2C_SDA
574 string "LCD panel i2c interface SDA pin"
575 depends on VIDEO_LCD_PANEL_I2C
576 default "PG12"
577 ---help---
578 Set the SDA pin for the LCD i2c interface. This takes a string in the
579 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
580
581config VIDEO_LCD_PANEL_I2C_SCL
582 string "LCD panel i2c interface SCL pin"
583 depends on VIDEO_LCD_PANEL_I2C
584 default "PG10"
585 ---help---
586 Set the SCL pin for the LCD i2c interface. This takes a string in the
587 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
588
Hans de Goede213480e2015-01-01 22:04:34 +0100589
590# Note only one of these may be selected at a time! But hidden choices are
591# not supported by Kconfig
592config VIDEO_LCD_IF_PARALLEL
593 bool
594
595config VIDEO_LCD_IF_LVDS
596 bool
597
598
599choice
600 prompt "LCD panel support"
601 depends on VIDEO
602 ---help---
603 Select which type of LCD panel to support.
604
605config VIDEO_LCD_PANEL_PARALLEL
606 bool "Generic parallel interface LCD panel"
607 select VIDEO_LCD_IF_PARALLEL
608
609config VIDEO_LCD_PANEL_LVDS
610 bool "Generic lvds interface LCD panel"
611 select VIDEO_LCD_IF_LVDS
612
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200613config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
614 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
615 select VIDEO_LCD_SSD2828
616 select VIDEO_LCD_IF_PARALLEL
617 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200618 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
619
620config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
621 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
622 select VIDEO_LCD_ANX9804
623 select VIDEO_LCD_IF_PARALLEL
624 select VIDEO_LCD_PANEL_I2C
625 ---help---
626 Select this for eDP LCD panels with 4 lanes running at 1.62G,
627 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200628
Hans de Goede27515b22015-01-20 09:23:36 +0100629config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
630 bool "Hitachi tx18d42vm LCD panel"
631 select VIDEO_LCD_HITACHI_TX18D42VM
632 select VIDEO_LCD_IF_LVDS
633 ---help---
634 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
635
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100636config VIDEO_LCD_TL059WV5C0
637 bool "tl059wv5c0 LCD panel"
638 select VIDEO_LCD_PANEL_I2C
639 select VIDEO_LCD_IF_PARALLEL
640 ---help---
641 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
642 Aigo M60/M608/M606 tablets.
643
Hans de Goede213480e2015-01-01 22:04:34 +0100644endchoice
645
646
Hans de Goedec13f60d2015-01-25 12:10:48 +0100647config GMAC_TX_DELAY
648 int "GMAC Transmit Clock Delay Chain"
649 default 0
650 ---help---
651 Set the GMAC Transmit Clock Delay Chain value.
652
Hans de Goedeff42d102015-09-13 13:02:48 +0200653config SPL_STACK_R_ADDR
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200654 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200655 default 0x2fe00000 if MACH_SUN9I
656
Masahiro Yamadadd840582014-07-30 14:08:14 +0900657endif