blob: 692c3775ddedc2390cfc34fdd7de07cee8813e52 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glass2e7d35d2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070011
Simon Glass00606d72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070025 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020026 remoteproc0 = &rproc_1;
27 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060047 };
48
Simon Glassce6d99a2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020054 buttons {
55 compatible = "gpio-keys";
56
57 summer {
58 gpios = <&gpio_a 3 0>;
59 label = "summer";
60 };
61
62 christmas {
63 gpios = <&gpio_a 4 0>;
64 label = "christmas";
65 };
66 };
67
Simon Glasse96fa6c2018-12-10 10:37:34 -070068 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060069 reg = <0 0>;
70 compatible = "google,cros-ec-sandbox";
71
72 /*
73 * This describes the flash memory within the EC. Note
74 * that the STM32L flash erases to 0, not 0xff.
75 */
76 flash {
77 image-pos = <0x08000000>;
78 size = <0x20000>;
79 erase-value = <0>;
80
81 /* Information for sandbox */
82 ro {
83 image-pos = <0>;
84 size = <0xf000>;
85 };
86 wp-ro {
87 image-pos = <0xf000>;
88 size = <0x1000>;
89 };
90 rw {
91 image-pos = <0x10000>;
92 size = <0x10000>;
93 };
94 };
95 };
96
Yannick Fertré23f965a2019-10-07 15:29:05 +020097 dsi_host: dsi_host {
98 compatible = "sandbox,dsi-host";
99 };
100
Simon Glass2e7d35d2014-02-26 15:59:21 -0700101 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600102 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700103 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600104 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700105 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600106 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100107 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
108 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700109 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100110 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
111 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
112 <&gpio_b 7 GPIO_IN 3 2 1>,
113 <&gpio_b 8 GPIO_OUT 3 2 1>,
114 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100115 test3-gpios =
116 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
117 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
118 <&gpio_c 2 GPIO_OUT>,
119 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
120 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200121 <&gpio_c 5 GPIO_IN>,
122 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
123 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700124 int-value = <1234>;
125 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200126 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200127 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600128 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700129 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600130 acpi,name = "GHIJ";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700131 };
132
133 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600134 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700135 compatible = "not,compatible";
136 };
137
138 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600139 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700140 };
141
Simon Glass5d9a88f2018-10-01 12:22:40 -0600142 backlight: backlight {
143 compatible = "pwm-backlight";
144 enable-gpios = <&gpio_a 1>;
145 power-supply = <&ldo_1>;
146 pwms = <&pwm 0 1000>;
147 default-brightness-level = <5>;
148 brightness-levels = <0 16 32 64 128 170 202 234 255>;
149 };
150
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200151 bind-test {
152 bind-test-child1 {
153 compatible = "sandbox,phy";
154 #phy-cells = <1>;
155 };
156
157 bind-test-child2 {
158 compatible = "simple-bus";
159 };
160 };
161
Simon Glass2e7d35d2014-02-26 15:59:21 -0700162 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600163 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700164 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600165 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700166 ping-add = <3>;
167 };
168
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200169 phy_provider0: gen_phy@0 {
170 compatible = "sandbox,phy";
171 #phy-cells = <1>;
172 };
173
174 phy_provider1: gen_phy@1 {
175 compatible = "sandbox,phy";
176 #phy-cells = <0>;
177 broken;
178 };
179
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200180 phy_provider2: gen_phy@2 {
181 compatible = "sandbox,phy";
182 #phy-cells = <0>;
183 };
184
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200185 gen_phy_user: gen_phy_user {
186 compatible = "simple-bus";
187 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
188 phy-names = "phy1", "phy2", "phy3";
189 };
190
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200191 gen_phy_user1: gen_phy_user1 {
192 compatible = "simple-bus";
193 phys = <&phy_provider0 0>, <&phy_provider2>;
194 phy-names = "phy1", "phy2";
195 };
196
Simon Glass2e7d35d2014-02-26 15:59:21 -0700197 some-bus {
198 #address-cells = <1>;
199 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600200 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600201 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600202 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700203 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600204 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700205 compatible = "denx,u-boot-fdt-test";
206 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600207 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700208 ping-add = <5>;
209 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600210 c-test@0 {
211 compatible = "denx,u-boot-fdt-test";
212 reg = <0>;
213 ping-expect = <6>;
214 ping-add = <6>;
215 };
216 c-test@1 {
217 compatible = "denx,u-boot-fdt-test";
218 reg = <1>;
219 ping-expect = <7>;
220 ping-add = <7>;
221 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700222 };
223
224 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600225 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600226 ping-expect = <6>;
227 ping-add = <6>;
228 compatible = "google,another-fdt-test";
229 };
230
231 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600232 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600233 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700234 ping-add = <6>;
235 compatible = "google,another-fdt-test";
236 };
237
Simon Glass9cc36a22015-01-25 08:27:05 -0700238 f-test {
239 compatible = "denx,u-boot-fdt-test";
240 };
241
242 g-test {
243 compatible = "denx,u-boot-fdt-test";
244 };
245
Bin Meng2786cd72018-10-10 22:07:01 -0700246 h-test {
247 compatible = "denx,u-boot-fdt-test1";
248 };
249
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200250 i-test {
251 compatible = "mediatek,u-boot-fdt-test";
252 #address-cells = <1>;
253 #size-cells = <0>;
254
255 subnode@0 {
256 reg = <0>;
257 };
258
259 subnode@1 {
260 reg = <1>;
261 };
262
263 subnode@2 {
264 reg = <2>;
265 };
266 };
267
Simon Glassdc12ebb2019-12-29 21:19:25 -0700268 devres-test {
269 compatible = "denx,u-boot-devres-test";
270 };
271
Simon Glass0f7b1112020-07-07 13:12:06 -0600272 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600273 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600274 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600275 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600276 child {
277 compatible = "denx,u-boot-acpi-test";
278 };
Simon Glassf50cc952020-04-08 16:57:34 -0600279 };
280
Simon Glass0f7b1112020-07-07 13:12:06 -0600281 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600282 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600283 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600284 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600285 };
286
Patrice Chotardee87a092017-09-04 14:55:57 +0200287 clocks {
288 clk_fixed: clk-fixed {
289 compatible = "fixed-clock";
290 #clock-cells = <0>;
291 clock-frequency = <1234>;
292 };
Anup Patelb630d572019-02-25 08:14:55 +0000293
294 clk_fixed_factor: clk-fixed-factor {
295 compatible = "fixed-factor-clock";
296 #clock-cells = <0>;
297 clock-div = <3>;
298 clock-mult = <2>;
299 clocks = <&clk_fixed>;
300 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200301
302 osc {
303 compatible = "fixed-clock";
304 #clock-cells = <0>;
305 clock-frequency = <20000000>;
306 };
Stephen Warren135aa952016-06-17 09:44:00 -0600307 };
308
309 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600310 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600311 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200312 assigned-clocks = <&clk_sandbox 3>;
313 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600314 };
315
316 clk-test {
317 compatible = "sandbox,clk-test";
318 clocks = <&clk_fixed>,
319 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200320 <&clk_sandbox 0>,
321 <&clk_sandbox 3>,
322 <&clk_sandbox 2>;
323 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600324 };
325
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200326 ccf: clk-ccf {
327 compatible = "sandbox,clk-ccf";
328 };
329
Simon Glass171e9912015-05-22 15:42:15 -0600330 eth@10002000 {
331 compatible = "sandbox,eth";
332 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500333 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600334 };
335
336 eth_5: eth@10003000 {
337 compatible = "sandbox,eth";
338 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500339 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600340 };
341
Bin Meng71d79712015-08-27 22:25:53 -0700342 eth_3: sbe5 {
343 compatible = "sandbox,eth";
344 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500345 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700346 };
347
Simon Glass171e9912015-05-22 15:42:15 -0600348 eth@10004000 {
349 compatible = "sandbox,eth";
350 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500351 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600352 };
353
Rajan Vaja31b82172018-09-19 03:43:46 -0700354 firmware {
355 sandbox_firmware: sandbox-firmware {
356 compatible = "sandbox,firmware";
357 };
358 };
359
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100360 pinctrl-gpio {
361 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700362
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100363 gpio_a: base-gpios {
364 compatible = "sandbox,gpio";
365 gpio-controller;
366 #gpio-cells = <1>;
367 gpio-bank-name = "a";
368 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200369 hog_input_active_low {
370 gpio-hog;
371 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200372 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200373 };
374 hog_input_active_high {
375 gpio-hog;
376 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200377 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200378 };
379 hog_output_low {
380 gpio-hog;
381 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200382 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200383 };
384 hog_output_high {
385 gpio-hog;
386 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200387 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200388 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100389 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600390
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100391 gpio_b: extra-gpios {
392 compatible = "sandbox,gpio";
393 gpio-controller;
394 #gpio-cells = <5>;
395 gpio-bank-name = "b";
396 sandbox,gpio-count = <10>;
397 };
398
399 gpio_c: pinmux-gpios {
400 compatible = "sandbox,gpio";
401 gpio-controller;
402 #gpio-cells = <2>;
403 gpio-bank-name = "c";
404 sandbox,gpio-count = <10>;
405 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100406 };
407
Simon Glassecc2ed52014-12-10 08:55:55 -0700408 i2c@0 {
409 #address-cells = <1>;
410 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600411 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700412 compatible = "sandbox,i2c";
413 clock-frequency = <100000>;
414 eeprom@2c {
415 reg = <0x2c>;
416 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700417 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200418 partitions {
419 compatible = "fixed-partitions";
420 #address-cells = <1>;
421 #size-cells = <1>;
422 bootcount_i2c: bootcount@10 {
423 reg = <10 2>;
424 };
425 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700426 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200427
Simon Glass52d3bc52015-05-22 15:42:17 -0600428 rtc_0: rtc@43 {
429 reg = <0x43>;
430 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700431 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600432 };
433
434 rtc_1: rtc@61 {
435 reg = <0x61>;
436 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700437 sandbox,emul = <&emul1>;
438 };
439
440 i2c_emul: emul {
441 reg = <0xff>;
442 compatible = "sandbox,i2c-emul-parent";
443 emul_eeprom: emul-eeprom {
444 compatible = "sandbox,i2c-eeprom";
445 sandbox,filename = "i2c.bin";
446 sandbox,size = <256>;
447 };
448 emul0: emul0 {
449 compatible = "sandbox,i2c-rtc";
450 };
451 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600452 compatible = "sandbox,i2c-rtc";
453 };
454 };
455
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200456 sandbox_pmic: sandbox_pmic {
457 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700458 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200459 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200460
461 mc34708: pmic@41 {
462 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700463 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200464 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700465 };
466
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100467 bootcount@0 {
468 compatible = "u-boot,bootcount-rtc";
469 rtc = <&rtc_1>;
470 offset = <0x13>;
471 };
472
Michal Simekf692b472020-05-28 11:48:55 +0200473 bootcount {
474 compatible = "u-boot,bootcount-i2c-eeprom";
475 i2c-eeprom = <&bootcount_i2c>;
476 };
477
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100478 adc@0 {
479 compatible = "sandbox,adc";
480 vdd-supply = <&buck2>;
481 vss-microvolts = <0>;
482 };
483
Simon Glass02554352020-02-06 09:55:00 -0700484 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700485 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700486 interrupt-controller;
487 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700488 };
489
Simon Glass3c97c4f2016-01-18 19:52:26 -0700490 lcd {
491 u-boot,dm-pre-reloc;
492 compatible = "sandbox,lcd-sdl";
493 xres = <1366>;
494 yres = <768>;
495 };
496
Simon Glass3c43fba2015-07-06 12:54:34 -0600497 leds {
498 compatible = "gpio-leds";
499
500 iracibble {
501 gpios = <&gpio_a 1 0>;
502 label = "sandbox:red";
503 };
504
505 martinet {
506 gpios = <&gpio_a 2 0>;
507 label = "sandbox:green";
508 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200509
510 default_on {
511 gpios = <&gpio_a 5 0>;
512 label = "sandbox:default_on";
513 default-state = "on";
514 };
515
516 default_off {
517 gpios = <&gpio_a 6 0>;
518 label = "sandbox:default_off";
519 default-state = "off";
520 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600521 };
522
Stephen Warren8961b522016-05-16 17:41:37 -0600523 mbox: mbox {
524 compatible = "sandbox,mbox";
525 #mbox-cells = <1>;
526 };
527
528 mbox-test {
529 compatible = "sandbox,mbox-test";
530 mboxes = <&mbox 100>, <&mbox 1>;
531 mbox-names = "other", "test";
532 };
533
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900534 cpus {
535 cpu-test1 {
536 compatible = "sandbox,cpu_sandbox";
537 u-boot,dm-pre-reloc;
538 };
Mario Sixfa44b532018-08-06 10:23:44 +0200539
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900540 cpu-test2 {
541 compatible = "sandbox,cpu_sandbox";
542 u-boot,dm-pre-reloc;
543 };
Mario Sixfa44b532018-08-06 10:23:44 +0200544
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900545 cpu-test3 {
546 compatible = "sandbox,cpu_sandbox";
547 u-boot,dm-pre-reloc;
548 };
Mario Sixfa44b532018-08-06 10:23:44 +0200549 };
550
Dave Gerlach21e3c212020-07-15 23:39:58 -0500551 chipid: chipid {
552 compatible = "sandbox,soc";
553 };
554
Simon Glasse96fa6c2018-12-10 10:37:34 -0700555 i2s: i2s {
556 compatible = "sandbox,i2s";
557 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700558 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700559 };
560
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200561 nop-test_0 {
562 compatible = "sandbox,nop_sandbox1";
563 nop-test_1 {
564 compatible = "sandbox,nop_sandbox2";
565 bind = "True";
566 };
567 nop-test_2 {
568 compatible = "sandbox,nop_sandbox2";
569 bind = "False";
570 };
571 };
572
Mario Six004e67c2018-07-31 14:24:14 +0200573 misc-test {
574 compatible = "sandbox,misc_sandbox";
575 };
576
Simon Glasse48eeb92017-04-23 20:02:07 -0600577 mmc2 {
578 compatible = "sandbox,mmc";
579 };
580
581 mmc1 {
582 compatible = "sandbox,mmc";
583 };
584
585 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600586 compatible = "sandbox,mmc";
587 };
588
Simon Glassb45c8332019-02-16 20:24:50 -0700589 pch {
590 compatible = "sandbox,pch";
591 };
592
Tom Rini42c64d12020-02-11 12:41:23 -0500593 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700594 compatible = "sandbox,pci";
595 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500596 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700597 #address-cells = <3>;
598 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600599 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700600 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700601 pci@0,0 {
602 compatible = "pci-generic";
603 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600604 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700605 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300606 pci@1,0 {
607 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600608 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
609 reg = <0x02000814 0 0 0 0
610 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600611 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300612 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700613 p2sb-pci@2,0 {
614 compatible = "sandbox,p2sb";
615 reg = <0x02001010 0 0 0 0>;
616 sandbox,emul = <&p2sb_emul>;
617
618 adder {
619 intel,p2sb-port-id = <3>;
620 compatible = "sandbox,adder";
621 };
622 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700623 pci@1e,0 {
624 compatible = "sandbox,pmc";
625 reg = <0xf000 0 0 0 0>;
626 sandbox,emul = <&pmc_emul1e>;
627 acpi-base = <0x400>;
628 gpe0-dwx-mask = <0xf>;
629 gpe0-dwx-shift-base = <4>;
630 gpe0-dw = <6 7 9>;
631 gpe0-sts = <0x20>;
632 gpe0-en = <0x30>;
633 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700634 pci@1f,0 {
635 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600636 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
637 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600638 sandbox,emul = <&swap_case_emul0_1f>;
639 };
640 };
641
642 pci-emul0 {
643 compatible = "sandbox,pci-emul-parent";
644 swap_case_emul0_0: emul0@0,0 {
645 compatible = "sandbox,swap-case";
646 };
647 swap_case_emul0_1: emul0@1,0 {
648 compatible = "sandbox,swap-case";
649 use-ea;
650 };
651 swap_case_emul0_1f: emul0@1f,0 {
652 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700653 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700654 p2sb_emul: emul@2,0 {
655 compatible = "sandbox,p2sb-emul";
656 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700657 pmc_emul1e: emul@1e,0 {
658 compatible = "sandbox,pmc-emul";
659 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700660 };
661
Tom Rini42c64d12020-02-11 12:41:23 -0500662 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700663 compatible = "sandbox,pci";
664 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500665 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700666 #address-cells = <3>;
667 #size-cells = <2>;
668 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
669 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700670 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200671 0x0c 0x00 0x1234 0x5678
672 0x10 0x00 0x1234 0x5678>;
673 pci@10,0 {
674 reg = <0x8000 0 0 0 0>;
675 };
Bin Mengdee4d752018-08-03 01:14:41 -0700676 };
677
Tom Rini42c64d12020-02-11 12:41:23 -0500678 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700679 compatible = "sandbox,pci";
680 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500681 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700682 #address-cells = <3>;
683 #size-cells = <2>;
684 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
685 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
686 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
687 pci@1f,0 {
688 compatible = "pci-generic";
689 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600690 sandbox,emul = <&swap_case_emul2_1f>;
691 };
692 };
693
694 pci-emul2 {
695 compatible = "sandbox,pci-emul-parent";
696 swap_case_emul2_1f: emul2@1f,0 {
697 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700698 };
699 };
700
Ramon Friedbb413332019-04-27 11:15:23 +0300701 pci_ep: pci_ep {
702 compatible = "sandbox,pci_ep";
703 };
704
Simon Glass98561572017-04-23 20:10:44 -0600705 probing {
706 compatible = "simple-bus";
707 test1 {
708 compatible = "denx,u-boot-probe-test";
709 };
710
711 test2 {
712 compatible = "denx,u-boot-probe-test";
713 };
714
715 test3 {
716 compatible = "denx,u-boot-probe-test";
717 };
718
719 test4 {
720 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100721 first-syscon = <&syscon0>;
722 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100723 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600724 };
725 };
726
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600727 pwrdom: power-domain {
728 compatible = "sandbox,power-domain";
729 #power-domain-cells = <1>;
730 };
731
732 power-domain-test {
733 compatible = "sandbox,power-domain-test";
734 power-domains = <&pwrdom 2>;
735 };
736
Simon Glass5d9a88f2018-10-01 12:22:40 -0600737 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600738 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600739 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600740 };
741
742 pwm2 {
743 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600744 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600745 };
746
Simon Glass64ce0ca2015-07-06 12:54:31 -0600747 ram {
748 compatible = "sandbox,ram";
749 };
750
Simon Glass5010d982015-07-06 12:54:29 -0600751 reset@0 {
752 compatible = "sandbox,warm-reset";
753 };
754
755 reset@1 {
756 compatible = "sandbox,reset";
757 };
758
Stephen Warren4581b712016-06-17 09:43:59 -0600759 resetc: reset-ctl {
760 compatible = "sandbox,reset-ctl";
761 #reset-cells = <1>;
762 };
763
764 reset-ctl-test {
765 compatible = "sandbox,reset-ctl-test";
766 resets = <&resetc 100>, <&resetc 2>;
767 reset-names = "other", "test";
768 };
769
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530770 rng {
771 compatible = "sandbox,sandbox-rng";
772 };
773
Nishanth Menon52159402015-09-17 15:42:41 -0500774 rproc_1: rproc@1 {
775 compatible = "sandbox,test-processor";
776 remoteproc-name = "remoteproc-test-dev1";
777 };
778
779 rproc_2: rproc@2 {
780 compatible = "sandbox,test-processor";
781 internal-memory-mapped;
782 remoteproc-name = "remoteproc-test-dev2";
783 };
784
Simon Glass5d9a88f2018-10-01 12:22:40 -0600785 panel {
786 compatible = "simple-panel";
787 backlight = <&backlight 0 100>;
788 };
789
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300790 smem@0 {
791 compatible = "sandbox,smem";
792 };
793
Simon Glassd4901892018-12-10 10:37:36 -0700794 sound {
795 compatible = "sandbox,sound";
796 cpu {
797 sound-dai = <&i2s 0>;
798 };
799
800 codec {
801 sound-dai = <&audio 0>;
802 };
803 };
804
Simon Glass0ae0cb72014-10-13 23:42:11 -0600805 spi@0 {
806 #address-cells = <1>;
807 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600808 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600809 compatible = "sandbox,spi";
810 cs-gpios = <0>, <&gpio_a 0>;
811 spi.bin@0 {
812 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000813 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600814 spi-max-frequency = <40000000>;
815 sandbox,filename = "spi.bin";
816 };
817 };
818
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100819 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600820 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200821 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600822 };
823
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100824 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600825 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600826 reg = <0x20 5
827 0x28 6
828 0x30 7
829 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600830 };
831
Patrick Delaunaya442e612019-03-07 09:57:13 +0100832 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900833 compatible = "simple-mfd", "syscon";
834 reg = <0x40 5
835 0x48 6
836 0x50 7
837 0x58 8>;
838 };
839
Thomas Choue7cc8d12015-12-11 16:27:34 +0800840 timer {
841 compatible = "sandbox,timer";
842 clock-frequency = <1000000>;
843 };
844
Miquel Raynalb91ad162018-05-15 11:57:27 +0200845 tpm2 {
846 compatible = "sandbox,tpm2";
847 };
848
Simon Glass171e9912015-05-22 15:42:15 -0600849 uart0: serial {
850 compatible = "sandbox,serial";
851 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500852 };
853
Simon Glasse00cb222015-03-25 12:23:05 -0600854 usb_0: usb@0 {
855 compatible = "sandbox,usb";
856 status = "disabled";
857 hub {
858 compatible = "sandbox,usb-hub";
859 #address-cells = <1>;
860 #size-cells = <0>;
861 flash-stick {
862 reg = <0>;
863 compatible = "sandbox,usb-flash";
864 };
865 };
866 };
867
868 usb_1: usb@1 {
869 compatible = "sandbox,usb";
870 hub {
871 compatible = "usb-hub";
872 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +0200873 #address-cells = <1>;
874 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -0600875 hub-emul {
876 compatible = "sandbox,usb-hub";
877 #address-cells = <1>;
878 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700879 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600880 reg = <0>;
881 compatible = "sandbox,usb-flash";
882 sandbox,filepath = "testflash.bin";
883 };
884
Simon Glass431cbd62015-11-08 23:48:01 -0700885 flash-stick@1 {
886 reg = <1>;
887 compatible = "sandbox,usb-flash";
888 sandbox,filepath = "testflash1.bin";
889 };
890
891 flash-stick@2 {
892 reg = <2>;
893 compatible = "sandbox,usb-flash";
894 sandbox,filepath = "testflash2.bin";
895 };
896
Simon Glassbff1a712015-11-08 23:48:08 -0700897 keyb@3 {
898 reg = <3>;
899 compatible = "sandbox,usb-keyb";
900 };
901
Simon Glasse00cb222015-03-25 12:23:05 -0600902 };
Michael Wallec03b7612020-06-02 01:47:07 +0200903
904 usbstor@1 {
905 reg = <1>;
906 };
907 usbstor@3 {
908 reg = <3>;
909 };
Simon Glasse00cb222015-03-25 12:23:05 -0600910 };
911 };
912
913 usb_2: usb@2 {
914 compatible = "sandbox,usb";
915 status = "disabled";
916 };
917
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200918 spmi: spmi@0 {
919 compatible = "sandbox,spmi";
920 #address-cells = <0x1>;
921 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600922 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200923 pm8916@0 {
924 compatible = "qcom,spmi-pmic";
925 reg = <0x0 0x1>;
926 #address-cells = <0x1>;
927 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600928 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200929
930 spmi_gpios: gpios@c000 {
931 compatible = "qcom,pm8916-gpio";
932 reg = <0xc000 0x400>;
933 gpio-controller;
934 gpio-count = <4>;
935 #gpio-cells = <2>;
936 gpio-bank-name="spmi";
937 };
938 };
939 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700940
941 wdt0: wdt@0 {
942 compatible = "sandbox,wdt";
943 };
Rob Clarkf2006802018-01-10 11:33:30 +0100944
Mario Six957983e2018-08-09 14:51:19 +0200945 axi: axi@0 {
946 compatible = "sandbox,axi";
947 #address-cells = <0x1>;
948 #size-cells = <0x1>;
949 store@0 {
950 compatible = "sandbox,sandbox_store";
951 reg = <0x0 0x400>;
952 };
953 };
954
Rob Clarkf2006802018-01-10 11:33:30 +0100955 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700956 #address-cells = <1>;
957 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -0700958 setting = "sunrise ohoka";
959 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -0700960 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -0600961 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100962 chosen-test {
963 compatible = "denx,u-boot-fdt-test";
964 reg = <9 1>;
965 };
966 };
Mario Sixe8d52912018-03-12 14:53:33 +0100967
968 translation-test@8000 {
969 compatible = "simple-bus";
970 reg = <0x8000 0x4000>;
971
972 #address-cells = <0x2>;
973 #size-cells = <0x1>;
974
975 ranges = <0 0x0 0x8000 0x1000
976 1 0x100 0x9000 0x1000
977 2 0x200 0xA000 0x1000
978 3 0x300 0xB000 0x1000
979 >;
980
Fabien Dessenne641067f2019-05-31 15:11:30 +0200981 dma-ranges = <0 0x000 0x10000000 0x1000
982 1 0x100 0x20000000 0x1000
983 >;
984
Mario Sixe8d52912018-03-12 14:53:33 +0100985 dev@0,0 {
986 compatible = "denx,u-boot-fdt-dummy";
987 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100988 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100989 };
990
991 dev@1,100 {
992 compatible = "denx,u-boot-fdt-dummy";
993 reg = <1 0x100 0x1000>;
994
995 };
996
997 dev@2,200 {
998 compatible = "denx,u-boot-fdt-dummy";
999 reg = <2 0x200 0x1000>;
1000 };
1001
1002
1003 noxlatebus@3,300 {
1004 compatible = "simple-bus";
1005 reg = <3 0x300 0x1000>;
1006
1007 #address-cells = <0x1>;
1008 #size-cells = <0x0>;
1009
1010 dev@42 {
1011 compatible = "denx,u-boot-fdt-dummy";
1012 reg = <0x42>;
1013 };
1014 };
1015 };
Mario Six4eea5312018-09-27 09:19:31 +02001016
1017 osd {
1018 compatible = "sandbox,sandbox_osd";
1019 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001020
Mario Sixe6fd0182018-07-31 11:44:13 +02001021 board {
1022 compatible = "sandbox,board_sandbox";
1023 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001024
1025 sandbox_tee {
1026 compatible = "sandbox,tee";
1027 };
Bin Meng4f89d492018-10-15 02:21:26 -07001028
1029 sandbox_virtio1 {
1030 compatible = "sandbox,virtio1";
1031 };
1032
1033 sandbox_virtio2 {
1034 compatible = "sandbox,virtio2";
1035 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001036
1037 pinctrl {
1038 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001039
1040 pinctrl-names = "default";
1041 pinctrl-0 = <&gpios>;
1042
1043 gpios: gpios {
1044 gpio0 {
1045 pins = "GPIO0";
1046 bias-pull-up;
1047 input-disable;
1048 };
1049 gpio1 {
1050 pins = "GPIO1";
1051 output-high;
1052 drive-open-drain;
1053 };
1054 gpio2 {
1055 pins = "GPIO2";
1056 bias-pull-down;
1057 input-enable;
1058 };
1059 gpio3 {
1060 pins = "GPIO3";
1061 bias-disable;
1062 };
1063 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001064 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001065
1066 hwspinlock@0 {
1067 compatible = "sandbox,hwspinlock";
1068 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001069
1070 dma: dma {
1071 compatible = "sandbox,dma";
1072 #dma-cells = <1>;
1073
1074 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1075 dma-names = "m2m", "tx0", "rx0";
1076 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001077
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001078 /*
1079 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1080 * end of the test. If parent mdio is removed first, clean-up of the
1081 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1082 * active at the end of the test. That it turn doesn't allow the mdio
1083 * class to be destroyed, triggering an error.
1084 */
1085 mdio-mux-test {
1086 compatible = "sandbox,mdio-mux";
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089 mdio-parent-bus = <&mdio>;
1090
1091 mdio-ch-test@0 {
1092 reg = <0>;
1093 };
1094 mdio-ch-test@1 {
1095 reg = <1>;
1096 };
1097 };
1098
1099 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001100 compatible = "sandbox,mdio";
1101 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001102
1103 pm-bus-test {
1104 compatible = "simple-pm-bus";
1105 clocks = <&clk_sandbox 4>;
1106 power-domains = <&pwrdom 1>;
1107 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001108
1109 resetc2: syscon-reset {
1110 compatible = "syscon-reset";
1111 #reset-cells = <1>;
1112 regmap = <&syscon0>;
1113 offset = <1>;
1114 mask = <0x27FFFFFF>;
1115 assert-high = <0>;
1116 };
1117
1118 syscon-reset-test {
1119 compatible = "sandbox,misc_sandbox";
1120 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1121 reset-names = "valid", "no_mask", "out_of_range";
1122 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001123};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001124
1125#include "sandbox_pmic.dtsi"