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Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
5
Simon Glass2e7d35d2014-02-26 15:59:21 -07006/ {
7 model = "sandbox";
8 compatible = "sandbox";
9 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060010 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070011
Simon Glass00606d72014-07-23 06:55:03 -060012 aliases {
13 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060014 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070015 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060016 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060017 gpio1 = &gpio_a;
18 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010019 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070020 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060021 mmc0 = "/mmc0";
22 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070023 pci0 = &pci0;
24 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070025 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020026 remoteproc0 = &rproc_1;
27 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060028 rtc0 = &rtc_0;
29 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060030 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020031 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070032 testbus3 = "/some-bus";
33 testfdt0 = "/some-bus/c-test@0";
34 testfdt1 = "/some-bus/c-test@1";
35 testfdt3 = "/b-test";
36 testfdt5 = "/some-bus/c-test@5";
37 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +020038 fdt-dummy0 = "/translation-test@8000/dev@0,0";
39 fdt-dummy1 = "/translation-test@8000/dev@1,100";
40 fdt-dummy2 = "/translation-test@8000/dev@2,200";
41 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060042 usb0 = &usb_0;
43 usb1 = &usb_1;
44 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020045 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020046 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060047 };
48
Simon Glassce6d99a2018-12-10 10:37:33 -070049 audio: audio-codec {
50 compatible = "sandbox,audio-codec";
51 #sound-dai-cells = <1>;
52 };
53
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020054 buttons {
55 compatible = "gpio-keys";
56
57 summer {
58 gpios = <&gpio_a 3 0>;
59 label = "summer";
60 };
61
62 christmas {
63 gpios = <&gpio_a 4 0>;
64 label = "christmas";
65 };
66 };
67
Simon Glasse96fa6c2018-12-10 10:37:34 -070068 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060069 reg = <0 0>;
70 compatible = "google,cros-ec-sandbox";
71
72 /*
73 * This describes the flash memory within the EC. Note
74 * that the STM32L flash erases to 0, not 0xff.
75 */
76 flash {
77 image-pos = <0x08000000>;
78 size = <0x20000>;
79 erase-value = <0>;
80
81 /* Information for sandbox */
82 ro {
83 image-pos = <0>;
84 size = <0xf000>;
85 };
86 wp-ro {
87 image-pos = <0xf000>;
88 size = <0x1000>;
89 };
90 rw {
91 image-pos = <0x10000>;
92 size = <0x10000>;
93 };
94 };
95 };
96
Yannick Fertré23f965a2019-10-07 15:29:05 +020097 dsi_host: dsi_host {
98 compatible = "sandbox,dsi-host";
99 };
100
Simon Glass2e7d35d2014-02-26 15:59:21 -0700101 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600102 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700103 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600104 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700105 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600106 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100107 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
108 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700109 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100110 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
111 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
112 <&gpio_b 7 GPIO_IN 3 2 1>,
113 <&gpio_b 8 GPIO_OUT 3 2 1>,
114 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100115 test3-gpios =
116 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
117 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
118 <&gpio_c 2 GPIO_OUT>,
119 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
120 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200121 <&gpio_c 5 GPIO_IN>,
122 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
123 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700124 int-value = <1234>;
125 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200126 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200127 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600128 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700129 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600130 acpi,name = "GHIJ";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700131 };
132
133 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600134 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700135 compatible = "not,compatible";
136 };
137
138 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600139 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700140 };
141
Simon Glass5d9a88f2018-10-01 12:22:40 -0600142 backlight: backlight {
143 compatible = "pwm-backlight";
144 enable-gpios = <&gpio_a 1>;
145 power-supply = <&ldo_1>;
146 pwms = <&pwm 0 1000>;
147 default-brightness-level = <5>;
148 brightness-levels = <0 16 32 64 128 170 202 234 255>;
149 };
150
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200151 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200152 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200153 bind-test-child1 {
154 compatible = "sandbox,phy";
155 #phy-cells = <1>;
156 };
157
158 bind-test-child2 {
159 compatible = "simple-bus";
160 };
161 };
162
Simon Glass2e7d35d2014-02-26 15:59:21 -0700163 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600164 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700165 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600166 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700167 ping-add = <3>;
168 };
169
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200170 phy_provider0: gen_phy@0 {
171 compatible = "sandbox,phy";
172 #phy-cells = <1>;
173 };
174
175 phy_provider1: gen_phy@1 {
176 compatible = "sandbox,phy";
177 #phy-cells = <0>;
178 broken;
179 };
180
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200181 phy_provider2: gen_phy@2 {
182 compatible = "sandbox,phy";
183 #phy-cells = <0>;
184 };
185
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200186 gen_phy_user: gen_phy_user {
187 compatible = "simple-bus";
188 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
189 phy-names = "phy1", "phy2", "phy3";
190 };
191
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200192 gen_phy_user1: gen_phy_user1 {
193 compatible = "simple-bus";
194 phys = <&phy_provider0 0>, <&phy_provider2>;
195 phy-names = "phy1", "phy2";
196 };
197
Simon Glass2e7d35d2014-02-26 15:59:21 -0700198 some-bus {
199 #address-cells = <1>;
200 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600201 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600202 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600203 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700204 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600205 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700206 compatible = "denx,u-boot-fdt-test";
207 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600208 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700209 ping-add = <5>;
210 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600211 c-test@0 {
212 compatible = "denx,u-boot-fdt-test";
213 reg = <0>;
214 ping-expect = <6>;
215 ping-add = <6>;
216 };
217 c-test@1 {
218 compatible = "denx,u-boot-fdt-test";
219 reg = <1>;
220 ping-expect = <7>;
221 ping-add = <7>;
222 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700223 };
224
225 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600226 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600227 ping-expect = <6>;
228 ping-add = <6>;
229 compatible = "google,another-fdt-test";
230 };
231
232 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600233 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600234 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700235 ping-add = <6>;
236 compatible = "google,another-fdt-test";
237 };
238
Simon Glass9cc36a22015-01-25 08:27:05 -0700239 f-test {
240 compatible = "denx,u-boot-fdt-test";
241 };
242
243 g-test {
244 compatible = "denx,u-boot-fdt-test";
245 };
246
Bin Meng2786cd72018-10-10 22:07:01 -0700247 h-test {
248 compatible = "denx,u-boot-fdt-test1";
249 };
250
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200251 i-test {
252 compatible = "mediatek,u-boot-fdt-test";
253 #address-cells = <1>;
254 #size-cells = <0>;
255
256 subnode@0 {
257 reg = <0>;
258 };
259
260 subnode@1 {
261 reg = <1>;
262 };
263
264 subnode@2 {
265 reg = <2>;
266 };
267 };
268
Simon Glassdc12ebb2019-12-29 21:19:25 -0700269 devres-test {
270 compatible = "denx,u-boot-devres-test";
271 };
272
Simon Glass0f7b1112020-07-07 13:12:06 -0600273 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600274 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600275 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600276 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600277 child {
278 compatible = "denx,u-boot-acpi-test";
279 };
Simon Glassf50cc952020-04-08 16:57:34 -0600280 };
281
Simon Glass0f7b1112020-07-07 13:12:06 -0600282 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600283 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600284 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600285 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600286 };
287
Patrice Chotardee87a092017-09-04 14:55:57 +0200288 clocks {
289 clk_fixed: clk-fixed {
290 compatible = "fixed-clock";
291 #clock-cells = <0>;
292 clock-frequency = <1234>;
293 };
Anup Patelb630d572019-02-25 08:14:55 +0000294
295 clk_fixed_factor: clk-fixed-factor {
296 compatible = "fixed-factor-clock";
297 #clock-cells = <0>;
298 clock-div = <3>;
299 clock-mult = <2>;
300 clocks = <&clk_fixed>;
301 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200302
303 osc {
304 compatible = "fixed-clock";
305 #clock-cells = <0>;
306 clock-frequency = <20000000>;
307 };
Stephen Warren135aa952016-06-17 09:44:00 -0600308 };
309
310 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600311 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600312 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200313 assigned-clocks = <&clk_sandbox 3>;
314 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600315 };
316
317 clk-test {
318 compatible = "sandbox,clk-test";
319 clocks = <&clk_fixed>,
320 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200321 <&clk_sandbox 0>,
322 <&clk_sandbox 3>,
323 <&clk_sandbox 2>;
324 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600325 };
326
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200327 ccf: clk-ccf {
328 compatible = "sandbox,clk-ccf";
329 };
330
Simon Glass171e9912015-05-22 15:42:15 -0600331 eth@10002000 {
332 compatible = "sandbox,eth";
333 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500334 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600335 };
336
337 eth_5: eth@10003000 {
338 compatible = "sandbox,eth";
339 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500340 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600341 };
342
Bin Meng71d79712015-08-27 22:25:53 -0700343 eth_3: sbe5 {
344 compatible = "sandbox,eth";
345 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500346 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700347 };
348
Simon Glass171e9912015-05-22 15:42:15 -0600349 eth@10004000 {
350 compatible = "sandbox,eth";
351 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500352 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600353 };
354
Rajan Vaja31b82172018-09-19 03:43:46 -0700355 firmware {
356 sandbox_firmware: sandbox-firmware {
357 compatible = "sandbox,firmware";
358 };
359 };
360
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100361 pinctrl-gpio {
362 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700363
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100364 gpio_a: base-gpios {
365 compatible = "sandbox,gpio";
366 gpio-controller;
367 #gpio-cells = <1>;
368 gpio-bank-name = "a";
369 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200370 hog_input_active_low {
371 gpio-hog;
372 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200373 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200374 };
375 hog_input_active_high {
376 gpio-hog;
377 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200378 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200379 };
380 hog_output_low {
381 gpio-hog;
382 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200383 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200384 };
385 hog_output_high {
386 gpio-hog;
387 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200388 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200389 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100390 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600391
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100392 gpio_b: extra-gpios {
393 compatible = "sandbox,gpio";
394 gpio-controller;
395 #gpio-cells = <5>;
396 gpio-bank-name = "b";
397 sandbox,gpio-count = <10>;
398 };
399
400 gpio_c: pinmux-gpios {
401 compatible = "sandbox,gpio";
402 gpio-controller;
403 #gpio-cells = <2>;
404 gpio-bank-name = "c";
405 sandbox,gpio-count = <10>;
406 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100407 };
408
Simon Glassecc2ed52014-12-10 08:55:55 -0700409 i2c@0 {
410 #address-cells = <1>;
411 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600412 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700413 compatible = "sandbox,i2c";
414 clock-frequency = <100000>;
415 eeprom@2c {
416 reg = <0x2c>;
417 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700418 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200419 partitions {
420 compatible = "fixed-partitions";
421 #address-cells = <1>;
422 #size-cells = <1>;
423 bootcount_i2c: bootcount@10 {
424 reg = <10 2>;
425 };
426 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700427 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200428
Simon Glass52d3bc52015-05-22 15:42:17 -0600429 rtc_0: rtc@43 {
430 reg = <0x43>;
431 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700432 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600433 };
434
435 rtc_1: rtc@61 {
436 reg = <0x61>;
437 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700438 sandbox,emul = <&emul1>;
439 };
440
441 i2c_emul: emul {
442 reg = <0xff>;
443 compatible = "sandbox,i2c-emul-parent";
444 emul_eeprom: emul-eeprom {
445 compatible = "sandbox,i2c-eeprom";
446 sandbox,filename = "i2c.bin";
447 sandbox,size = <256>;
448 };
449 emul0: emul0 {
450 compatible = "sandbox,i2c-rtc";
451 };
452 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600453 compatible = "sandbox,i2c-rtc";
454 };
455 };
456
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200457 sandbox_pmic: sandbox_pmic {
458 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700459 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200460 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200461
462 mc34708: pmic@41 {
463 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700464 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200465 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700466 };
467
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100468 bootcount@0 {
469 compatible = "u-boot,bootcount-rtc";
470 rtc = <&rtc_1>;
471 offset = <0x13>;
472 };
473
Michal Simekf692b472020-05-28 11:48:55 +0200474 bootcount {
475 compatible = "u-boot,bootcount-i2c-eeprom";
476 i2c-eeprom = <&bootcount_i2c>;
477 };
478
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100479 adc@0 {
480 compatible = "sandbox,adc";
481 vdd-supply = <&buck2>;
482 vss-microvolts = <0>;
483 };
484
Simon Glass02554352020-02-06 09:55:00 -0700485 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700486 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700487 interrupt-controller;
488 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700489 };
490
Simon Glass3c97c4f2016-01-18 19:52:26 -0700491 lcd {
492 u-boot,dm-pre-reloc;
493 compatible = "sandbox,lcd-sdl";
494 xres = <1366>;
495 yres = <768>;
496 };
497
Simon Glass3c43fba2015-07-06 12:54:34 -0600498 leds {
499 compatible = "gpio-leds";
500
501 iracibble {
502 gpios = <&gpio_a 1 0>;
503 label = "sandbox:red";
504 };
505
506 martinet {
507 gpios = <&gpio_a 2 0>;
508 label = "sandbox:green";
509 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200510
511 default_on {
512 gpios = <&gpio_a 5 0>;
513 label = "sandbox:default_on";
514 default-state = "on";
515 };
516
517 default_off {
518 gpios = <&gpio_a 6 0>;
519 label = "sandbox:default_off";
520 default-state = "off";
521 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600522 };
523
Stephen Warren8961b522016-05-16 17:41:37 -0600524 mbox: mbox {
525 compatible = "sandbox,mbox";
526 #mbox-cells = <1>;
527 };
528
529 mbox-test {
530 compatible = "sandbox,mbox-test";
531 mboxes = <&mbox 100>, <&mbox 1>;
532 mbox-names = "other", "test";
533 };
534
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900535 cpus {
536 cpu-test1 {
537 compatible = "sandbox,cpu_sandbox";
538 u-boot,dm-pre-reloc;
539 };
Mario Sixfa44b532018-08-06 10:23:44 +0200540
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900541 cpu-test2 {
542 compatible = "sandbox,cpu_sandbox";
543 u-boot,dm-pre-reloc;
544 };
Mario Sixfa44b532018-08-06 10:23:44 +0200545
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900546 cpu-test3 {
547 compatible = "sandbox,cpu_sandbox";
548 u-boot,dm-pre-reloc;
549 };
Mario Sixfa44b532018-08-06 10:23:44 +0200550 };
551
Dave Gerlach21e3c212020-07-15 23:39:58 -0500552 chipid: chipid {
553 compatible = "sandbox,soc";
554 };
555
Simon Glasse96fa6c2018-12-10 10:37:34 -0700556 i2s: i2s {
557 compatible = "sandbox,i2s";
558 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700559 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700560 };
561
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200562 nop-test_0 {
563 compatible = "sandbox,nop_sandbox1";
564 nop-test_1 {
565 compatible = "sandbox,nop_sandbox2";
566 bind = "True";
567 };
568 nop-test_2 {
569 compatible = "sandbox,nop_sandbox2";
570 bind = "False";
571 };
572 };
573
Mario Six004e67c2018-07-31 14:24:14 +0200574 misc-test {
575 compatible = "sandbox,misc_sandbox";
576 };
577
Simon Glasse48eeb92017-04-23 20:02:07 -0600578 mmc2 {
579 compatible = "sandbox,mmc";
580 };
581
582 mmc1 {
583 compatible = "sandbox,mmc";
584 };
585
586 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600587 compatible = "sandbox,mmc";
588 };
589
Simon Glassb45c8332019-02-16 20:24:50 -0700590 pch {
591 compatible = "sandbox,pch";
592 };
593
Tom Rini42c64d12020-02-11 12:41:23 -0500594 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700595 compatible = "sandbox,pci";
596 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500597 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700598 #address-cells = <3>;
599 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600600 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700601 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700602 pci@0,0 {
603 compatible = "pci-generic";
604 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600605 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700606 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300607 pci@1,0 {
608 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600609 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
610 reg = <0x02000814 0 0 0 0
611 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600612 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300613 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700614 p2sb-pci@2,0 {
615 compatible = "sandbox,p2sb";
616 reg = <0x02001010 0 0 0 0>;
617 sandbox,emul = <&p2sb_emul>;
618
619 adder {
620 intel,p2sb-port-id = <3>;
621 compatible = "sandbox,adder";
622 };
623 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700624 pci@1e,0 {
625 compatible = "sandbox,pmc";
626 reg = <0xf000 0 0 0 0>;
627 sandbox,emul = <&pmc_emul1e>;
628 acpi-base = <0x400>;
629 gpe0-dwx-mask = <0xf>;
630 gpe0-dwx-shift-base = <4>;
631 gpe0-dw = <6 7 9>;
632 gpe0-sts = <0x20>;
633 gpe0-en = <0x30>;
634 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700635 pci@1f,0 {
636 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600637 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
638 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600639 sandbox,emul = <&swap_case_emul0_1f>;
640 };
641 };
642
643 pci-emul0 {
644 compatible = "sandbox,pci-emul-parent";
645 swap_case_emul0_0: emul0@0,0 {
646 compatible = "sandbox,swap-case";
647 };
648 swap_case_emul0_1: emul0@1,0 {
649 compatible = "sandbox,swap-case";
650 use-ea;
651 };
652 swap_case_emul0_1f: emul0@1f,0 {
653 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700654 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700655 p2sb_emul: emul@2,0 {
656 compatible = "sandbox,p2sb-emul";
657 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700658 pmc_emul1e: emul@1e,0 {
659 compatible = "sandbox,pmc-emul";
660 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700661 };
662
Tom Rini42c64d12020-02-11 12:41:23 -0500663 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700664 compatible = "sandbox,pci";
665 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500666 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700667 #address-cells = <3>;
668 #size-cells = <2>;
669 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000
670 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700671 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200672 0x0c 0x00 0x1234 0x5678
673 0x10 0x00 0x1234 0x5678>;
674 pci@10,0 {
675 reg = <0x8000 0 0 0 0>;
676 };
Bin Mengdee4d752018-08-03 01:14:41 -0700677 };
678
Tom Rini42c64d12020-02-11 12:41:23 -0500679 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700680 compatible = "sandbox,pci";
681 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500682 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700683 #address-cells = <3>;
684 #size-cells = <2>;
685 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
686 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
687 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
688 pci@1f,0 {
689 compatible = "pci-generic";
690 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600691 sandbox,emul = <&swap_case_emul2_1f>;
692 };
693 };
694
695 pci-emul2 {
696 compatible = "sandbox,pci-emul-parent";
697 swap_case_emul2_1f: emul2@1f,0 {
698 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700699 };
700 };
701
Ramon Friedbb413332019-04-27 11:15:23 +0300702 pci_ep: pci_ep {
703 compatible = "sandbox,pci_ep";
704 };
705
Simon Glass98561572017-04-23 20:10:44 -0600706 probing {
707 compatible = "simple-bus";
708 test1 {
709 compatible = "denx,u-boot-probe-test";
710 };
711
712 test2 {
713 compatible = "denx,u-boot-probe-test";
714 };
715
716 test3 {
717 compatible = "denx,u-boot-probe-test";
718 };
719
720 test4 {
721 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100722 first-syscon = <&syscon0>;
723 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100724 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600725 };
726 };
727
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600728 pwrdom: power-domain {
729 compatible = "sandbox,power-domain";
730 #power-domain-cells = <1>;
731 };
732
733 power-domain-test {
734 compatible = "sandbox,power-domain-test";
735 power-domains = <&pwrdom 2>;
736 };
737
Simon Glass5d9a88f2018-10-01 12:22:40 -0600738 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600739 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600740 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600741 };
742
743 pwm2 {
744 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600745 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600746 };
747
Simon Glass64ce0ca2015-07-06 12:54:31 -0600748 ram {
749 compatible = "sandbox,ram";
750 };
751
Simon Glass5010d982015-07-06 12:54:29 -0600752 reset@0 {
753 compatible = "sandbox,warm-reset";
754 };
755
756 reset@1 {
757 compatible = "sandbox,reset";
758 };
759
Stephen Warren4581b712016-06-17 09:43:59 -0600760 resetc: reset-ctl {
761 compatible = "sandbox,reset-ctl";
762 #reset-cells = <1>;
763 };
764
765 reset-ctl-test {
766 compatible = "sandbox,reset-ctl-test";
767 resets = <&resetc 100>, <&resetc 2>;
768 reset-names = "other", "test";
769 };
770
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530771 rng {
772 compatible = "sandbox,sandbox-rng";
773 };
774
Nishanth Menon52159402015-09-17 15:42:41 -0500775 rproc_1: rproc@1 {
776 compatible = "sandbox,test-processor";
777 remoteproc-name = "remoteproc-test-dev1";
778 };
779
780 rproc_2: rproc@2 {
781 compatible = "sandbox,test-processor";
782 internal-memory-mapped;
783 remoteproc-name = "remoteproc-test-dev2";
784 };
785
Simon Glass5d9a88f2018-10-01 12:22:40 -0600786 panel {
787 compatible = "simple-panel";
788 backlight = <&backlight 0 100>;
789 };
790
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300791 smem@0 {
792 compatible = "sandbox,smem";
793 };
794
Simon Glassd4901892018-12-10 10:37:36 -0700795 sound {
796 compatible = "sandbox,sound";
797 cpu {
798 sound-dai = <&i2s 0>;
799 };
800
801 codec {
802 sound-dai = <&audio 0>;
803 };
804 };
805
Simon Glass0ae0cb72014-10-13 23:42:11 -0600806 spi@0 {
807 #address-cells = <1>;
808 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600809 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600810 compatible = "sandbox,spi";
811 cs-gpios = <0>, <&gpio_a 0>;
812 spi.bin@0 {
813 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000814 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600815 spi-max-frequency = <40000000>;
816 sandbox,filename = "spi.bin";
817 };
818 };
819
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100820 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600821 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200822 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600823 };
824
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100825 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600826 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600827 reg = <0x20 5
828 0x28 6
829 0x30 7
830 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600831 };
832
Patrick Delaunaya442e612019-03-07 09:57:13 +0100833 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900834 compatible = "simple-mfd", "syscon";
835 reg = <0x40 5
836 0x48 6
837 0x50 7
838 0x58 8>;
839 };
840
Thomas Choue7cc8d12015-12-11 16:27:34 +0800841 timer {
842 compatible = "sandbox,timer";
843 clock-frequency = <1000000>;
844 };
845
Miquel Raynalb91ad162018-05-15 11:57:27 +0200846 tpm2 {
847 compatible = "sandbox,tpm2";
848 };
849
Simon Glass171e9912015-05-22 15:42:15 -0600850 uart0: serial {
851 compatible = "sandbox,serial";
852 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500853 };
854
Simon Glasse00cb222015-03-25 12:23:05 -0600855 usb_0: usb@0 {
856 compatible = "sandbox,usb";
857 status = "disabled";
858 hub {
859 compatible = "sandbox,usb-hub";
860 #address-cells = <1>;
861 #size-cells = <0>;
862 flash-stick {
863 reg = <0>;
864 compatible = "sandbox,usb-flash";
865 };
866 };
867 };
868
869 usb_1: usb@1 {
870 compatible = "sandbox,usb";
871 hub {
872 compatible = "usb-hub";
873 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +0200874 #address-cells = <1>;
875 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -0600876 hub-emul {
877 compatible = "sandbox,usb-hub";
878 #address-cells = <1>;
879 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700880 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600881 reg = <0>;
882 compatible = "sandbox,usb-flash";
883 sandbox,filepath = "testflash.bin";
884 };
885
Simon Glass431cbd62015-11-08 23:48:01 -0700886 flash-stick@1 {
887 reg = <1>;
888 compatible = "sandbox,usb-flash";
889 sandbox,filepath = "testflash1.bin";
890 };
891
892 flash-stick@2 {
893 reg = <2>;
894 compatible = "sandbox,usb-flash";
895 sandbox,filepath = "testflash2.bin";
896 };
897
Simon Glassbff1a712015-11-08 23:48:08 -0700898 keyb@3 {
899 reg = <3>;
900 compatible = "sandbox,usb-keyb";
901 };
902
Simon Glasse00cb222015-03-25 12:23:05 -0600903 };
Michael Wallec03b7612020-06-02 01:47:07 +0200904
905 usbstor@1 {
906 reg = <1>;
907 };
908 usbstor@3 {
909 reg = <3>;
910 };
Simon Glasse00cb222015-03-25 12:23:05 -0600911 };
912 };
913
914 usb_2: usb@2 {
915 compatible = "sandbox,usb";
916 status = "disabled";
917 };
918
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200919 spmi: spmi@0 {
920 compatible = "sandbox,spmi";
921 #address-cells = <0x1>;
922 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600923 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200924 pm8916@0 {
925 compatible = "qcom,spmi-pmic";
926 reg = <0x0 0x1>;
927 #address-cells = <0x1>;
928 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600929 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200930
931 spmi_gpios: gpios@c000 {
932 compatible = "qcom,pm8916-gpio";
933 reg = <0xc000 0x400>;
934 gpio-controller;
935 gpio-count = <4>;
936 #gpio-cells = <2>;
937 gpio-bank-name="spmi";
938 };
939 };
940 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700941
942 wdt0: wdt@0 {
943 compatible = "sandbox,wdt";
944 };
Rob Clarkf2006802018-01-10 11:33:30 +0100945
Mario Six957983e2018-08-09 14:51:19 +0200946 axi: axi@0 {
947 compatible = "sandbox,axi";
948 #address-cells = <0x1>;
949 #size-cells = <0x1>;
950 store@0 {
951 compatible = "sandbox,sandbox_store";
952 reg = <0x0 0x400>;
953 };
954 };
955
Rob Clarkf2006802018-01-10 11:33:30 +0100956 chosen {
Simon Glass7e878162018-02-03 10:36:58 -0700957 #address-cells = <1>;
958 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -0700959 setting = "sunrise ohoka";
960 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -0700961 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -0600962 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +0100963 chosen-test {
964 compatible = "denx,u-boot-fdt-test";
965 reg = <9 1>;
966 };
967 };
Mario Sixe8d52912018-03-12 14:53:33 +0100968
969 translation-test@8000 {
970 compatible = "simple-bus";
971 reg = <0x8000 0x4000>;
972
973 #address-cells = <0x2>;
974 #size-cells = <0x1>;
975
976 ranges = <0 0x0 0x8000 0x1000
977 1 0x100 0x9000 0x1000
978 2 0x200 0xA000 0x1000
979 3 0x300 0xB000 0x1000
980 >;
981
Fabien Dessenne641067f2019-05-31 15:11:30 +0200982 dma-ranges = <0 0x000 0x10000000 0x1000
983 1 0x100 0x20000000 0x1000
984 >;
985
Mario Sixe8d52912018-03-12 14:53:33 +0100986 dev@0,0 {
987 compatible = "denx,u-boot-fdt-dummy";
988 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +0100989 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +0100990 };
991
992 dev@1,100 {
993 compatible = "denx,u-boot-fdt-dummy";
994 reg = <1 0x100 0x1000>;
995
996 };
997
998 dev@2,200 {
999 compatible = "denx,u-boot-fdt-dummy";
1000 reg = <2 0x200 0x1000>;
1001 };
1002
1003
1004 noxlatebus@3,300 {
1005 compatible = "simple-bus";
1006 reg = <3 0x300 0x1000>;
1007
1008 #address-cells = <0x1>;
1009 #size-cells = <0x0>;
1010
1011 dev@42 {
1012 compatible = "denx,u-boot-fdt-dummy";
1013 reg = <0x42>;
1014 };
1015 };
1016 };
Mario Six4eea5312018-09-27 09:19:31 +02001017
1018 osd {
1019 compatible = "sandbox,sandbox_osd";
1020 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001021
Mario Sixe6fd0182018-07-31 11:44:13 +02001022 board {
1023 compatible = "sandbox,board_sandbox";
1024 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001025
1026 sandbox_tee {
1027 compatible = "sandbox,tee";
1028 };
Bin Meng4f89d492018-10-15 02:21:26 -07001029
1030 sandbox_virtio1 {
1031 compatible = "sandbox,virtio1";
1032 };
1033
1034 sandbox_virtio2 {
1035 compatible = "sandbox,virtio2";
1036 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001037
1038 pinctrl {
1039 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001040
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&gpios>;
1043
1044 gpios: gpios {
1045 gpio0 {
1046 pins = "GPIO0";
1047 bias-pull-up;
1048 input-disable;
1049 };
1050 gpio1 {
1051 pins = "GPIO1";
1052 output-high;
1053 drive-open-drain;
1054 };
1055 gpio2 {
1056 pins = "GPIO2";
1057 bias-pull-down;
1058 input-enable;
1059 };
1060 gpio3 {
1061 pins = "GPIO3";
1062 bias-disable;
1063 };
1064 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001065 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001066
1067 hwspinlock@0 {
1068 compatible = "sandbox,hwspinlock";
1069 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001070
1071 dma: dma {
1072 compatible = "sandbox,dma";
1073 #dma-cells = <1>;
1074
1075 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1076 dma-names = "m2m", "tx0", "rx0";
1077 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001078
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001079 /*
1080 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1081 * end of the test. If parent mdio is removed first, clean-up of the
1082 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1083 * active at the end of the test. That it turn doesn't allow the mdio
1084 * class to be destroyed, triggering an error.
1085 */
1086 mdio-mux-test {
1087 compatible = "sandbox,mdio-mux";
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 mdio-parent-bus = <&mdio>;
1091
1092 mdio-ch-test@0 {
1093 reg = <0>;
1094 };
1095 mdio-ch-test@1 {
1096 reg = <1>;
1097 };
1098 };
1099
1100 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001101 compatible = "sandbox,mdio";
1102 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001103
1104 pm-bus-test {
1105 compatible = "simple-pm-bus";
1106 clocks = <&clk_sandbox 4>;
1107 power-domains = <&pwrdom 1>;
1108 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001109
1110 resetc2: syscon-reset {
1111 compatible = "syscon-reset";
1112 #reset-cells = <1>;
1113 regmap = <&syscon0>;
1114 offset = <1>;
1115 mask = <0x27FFFFFF>;
1116 assert-high = <0>;
1117 };
1118
1119 syscon-reset-test {
1120 compatible = "sandbox,misc_sandbox";
1121 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1122 reset-names = "valid", "no_mask", "out_of_range";
1123 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001124};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001125
1126#include "sandbox_pmic.dtsi"