blob: c135881ac338f5c653824e951da398acca791c32 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05306#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01007
Simon Glass2e7d35d2014-02-26 15:59:21 -07008/ {
9 model = "sandbox";
10 compatible = "sandbox";
11 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060012 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070013
Simon Glass00606d72014-07-23 06:55:03 -060014 aliases {
15 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060016 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070017 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060018 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060019 gpio1 = &gpio_a;
20 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010021 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070022 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060023 mmc0 = "/mmc0";
24 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070025 pci0 = &pci0;
26 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070027 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020028 remoteproc0 = &rproc_1;
29 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060030 rtc0 = &rtc_0;
31 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060032 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020033 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070034 testbus3 = "/some-bus";
35 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070036 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070037 testfdt3 = "/b-test";
38 testfdt5 = "/some-bus/c-test@5";
39 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070040 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020041 fdt-dummy0 = "/translation-test@8000/dev@0,0";
42 fdt-dummy1 = "/translation-test@8000/dev@1,100";
43 fdt-dummy2 = "/translation-test@8000/dev@2,200";
44 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchid64b9cd2020-12-30 00:16:21 +010045 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glasse00cb222015-03-25 12:23:05 -060046 usb0 = &usb_0;
47 usb1 = &usb_1;
48 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020049 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020050 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060051 };
52
Simon Glassce6d99a2018-12-10 10:37:33 -070053 audio: audio-codec {
54 compatible = "sandbox,audio-codec";
55 #sound-dai-cells = <1>;
56 };
57
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020058 buttons {
59 compatible = "gpio-keys";
60
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020061 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020062 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020063 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020064 };
65
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020066 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020067 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020068 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020069 };
70 };
71
Simon Glasse96fa6c2018-12-10 10:37:34 -070072 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060073 reg = <0 0>;
74 compatible = "google,cros-ec-sandbox";
75
76 /*
77 * This describes the flash memory within the EC. Note
78 * that the STM32L flash erases to 0, not 0xff.
79 */
80 flash {
81 image-pos = <0x08000000>;
82 size = <0x20000>;
83 erase-value = <0>;
84
85 /* Information for sandbox */
86 ro {
87 image-pos = <0>;
88 size = <0xf000>;
89 };
90 wp-ro {
91 image-pos = <0xf000>;
92 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -070093 used = <0x884>;
94 compress = "lz4";
95 uncomp-size = <0xcf8>;
96 hash {
97 algo = "sha256";
98 value = [00 01 02 03 04 05 06 07
99 08 09 0a 0b 0c 0d 0e 0f
100 10 11 12 13 14 15 16 17
101 18 19 1a 1b 1c 1d 1e 1f];
102 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600103 };
104 rw {
105 image-pos = <0x10000>;
106 size = <0x10000>;
107 };
108 };
109 };
110
Yannick Fertré23f965a2019-10-07 15:29:05 +0200111 dsi_host: dsi_host {
112 compatible = "sandbox,dsi-host";
113 };
114
Simon Glass2e7d35d2014-02-26 15:59:21 -0700115 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600116 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700117 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600118 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700119 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600120 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100121 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
122 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700123 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100124 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
125 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
126 <&gpio_b 7 GPIO_IN 3 2 1>,
127 <&gpio_b 8 GPIO_OUT 3 2 1>,
128 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100129 test3-gpios =
130 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
131 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
132 <&gpio_c 2 GPIO_OUT>,
133 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
134 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200135 <&gpio_c 5 GPIO_IN>,
136 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
137 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530138 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
139 test5-gpios = <&gpio_a 19>;
140
Simon Glassa1b17e42018-12-10 10:37:37 -0700141 int-value = <1234>;
142 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200143 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200144 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600145 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700146 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600147 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200148 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530149
150 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
151 <&muxcontroller0 2>, <&muxcontroller0 3>,
152 <&muxcontroller1>;
153 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
154 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100155 display-timings {
156 timing0: 240x320 {
157 clock-frequency = <6500000>;
158 hactive = <240>;
159 vactive = <320>;
160 hfront-porch = <6>;
161 hback-porch = <7>;
162 hsync-len = <1>;
163 vback-porch = <5>;
164 vfront-porch = <8>;
165 vsync-len = <2>;
166 hsync-active = <1>;
167 vsync-active = <0>;
168 de-active = <1>;
169 pixelclk-active = <1>;
170 interlaced;
171 doublescan;
172 doubleclk;
173 };
174 timing1: 480x800 {
175 clock-frequency = <9000000>;
176 hactive = <480>;
177 vactive = <800>;
178 hfront-porch = <10>;
179 hback-porch = <59>;
180 hsync-len = <12>;
181 vback-porch = <15>;
182 vfront-porch = <17>;
183 vsync-len = <16>;
184 hsync-active = <0>;
185 vsync-active = <1>;
186 de-active = <0>;
187 pixelclk-active = <0>;
188 };
189 timing2: 800x480 {
190 clock-frequency = <33500000>;
191 hactive = <800>;
192 vactive = <480>;
193 hback-porch = <89>;
194 hfront-porch = <164>;
195 vback-porch = <23>;
196 vfront-porch = <10>;
197 hsync-len = <11>;
198 vsync-len = <13>;
199 };
200 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700201 };
202
203 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600204 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700205 compatible = "not,compatible";
206 };
207
208 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600209 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700210 };
211
Simon Glass5d9a88f2018-10-01 12:22:40 -0600212 backlight: backlight {
213 compatible = "pwm-backlight";
214 enable-gpios = <&gpio_a 1>;
215 power-supply = <&ldo_1>;
216 pwms = <&pwm 0 1000>;
217 default-brightness-level = <5>;
218 brightness-levels = <0 16 32 64 128 170 202 234 255>;
219 };
220
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200221 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200222 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200223 bind-test-child1 {
224 compatible = "sandbox,phy";
225 #phy-cells = <1>;
226 };
227
228 bind-test-child2 {
229 compatible = "simple-bus";
230 };
231 };
232
Simon Glass2e7d35d2014-02-26 15:59:21 -0700233 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600234 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700235 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600236 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700237 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530238
239 mux-controls = <&muxcontroller0 0>;
240 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700241 };
242
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200243 phy_provider0: gen_phy@0 {
244 compatible = "sandbox,phy";
245 #phy-cells = <1>;
246 };
247
248 phy_provider1: gen_phy@1 {
249 compatible = "sandbox,phy";
250 #phy-cells = <0>;
251 broken;
252 };
253
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200254 phy_provider2: gen_phy@2 {
255 compatible = "sandbox,phy";
256 #phy-cells = <0>;
257 };
258
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200259 gen_phy_user: gen_phy_user {
260 compatible = "simple-bus";
261 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
262 phy-names = "phy1", "phy2", "phy3";
263 };
264
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200265 gen_phy_user1: gen_phy_user1 {
266 compatible = "simple-bus";
267 phys = <&phy_provider0 0>, <&phy_provider2>;
268 phy-names = "phy1", "phy2";
269 };
270
Simon Glass2e7d35d2014-02-26 15:59:21 -0700271 some-bus {
272 #address-cells = <1>;
273 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600274 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600275 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600276 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700277 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600278 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700279 compatible = "denx,u-boot-fdt-test";
280 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600281 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700282 ping-add = <5>;
283 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600284 c-test@0 {
285 compatible = "denx,u-boot-fdt-test";
286 reg = <0>;
287 ping-expect = <6>;
288 ping-add = <6>;
289 };
290 c-test@1 {
291 compatible = "denx,u-boot-fdt-test";
292 reg = <1>;
293 ping-expect = <7>;
294 ping-add = <7>;
295 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700296 };
297
298 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600299 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600300 ping-expect = <6>;
301 ping-add = <6>;
302 compatible = "google,another-fdt-test";
303 };
304
305 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600306 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600307 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700308 ping-add = <6>;
309 compatible = "google,another-fdt-test";
310 };
311
Simon Glass9cc36a22015-01-25 08:27:05 -0700312 f-test {
313 compatible = "denx,u-boot-fdt-test";
314 };
315
316 g-test {
317 compatible = "denx,u-boot-fdt-test";
318 };
319
Bin Meng2786cd72018-10-10 22:07:01 -0700320 h-test {
321 compatible = "denx,u-boot-fdt-test1";
322 };
323
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200324 i-test {
325 compatible = "mediatek,u-boot-fdt-test";
326 #address-cells = <1>;
327 #size-cells = <0>;
328
329 subnode@0 {
330 reg = <0>;
331 };
332
333 subnode@1 {
334 reg = <1>;
335 };
336
337 subnode@2 {
338 reg = <2>;
339 };
340 };
341
Simon Glassdc12ebb2019-12-29 21:19:25 -0700342 devres-test {
343 compatible = "denx,u-boot-devres-test";
344 };
345
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530346 another-test {
347 reg = <0 2>;
348 compatible = "denx,u-boot-fdt-test";
349 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
350 test5-gpios = <&gpio_a 19>;
351 };
352
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100353 mmio-bus@0 {
354 #address-cells = <1>;
355 #size-cells = <1>;
356 compatible = "denx,u-boot-test-bus";
357 dma-ranges = <0x10000000 0x00000000 0x00040000>;
358
359 subnode@0 {
360 compatible = "denx,u-boot-fdt-test";
361 };
362 };
363
364 mmio-bus@1 {
365 #address-cells = <1>;
366 #size-cells = <1>;
367 compatible = "denx,u-boot-test-bus";
368 };
369
Simon Glass0f7b1112020-07-07 13:12:06 -0600370 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600371 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600372 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600373 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600374 child {
375 compatible = "denx,u-boot-acpi-test";
376 };
Simon Glassf50cc952020-04-08 16:57:34 -0600377 };
378
Simon Glass0f7b1112020-07-07 13:12:06 -0600379 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600380 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600381 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600382 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600383 };
384
Patrice Chotardee87a092017-09-04 14:55:57 +0200385 clocks {
386 clk_fixed: clk-fixed {
387 compatible = "fixed-clock";
388 #clock-cells = <0>;
389 clock-frequency = <1234>;
390 };
Anup Patelb630d572019-02-25 08:14:55 +0000391
392 clk_fixed_factor: clk-fixed-factor {
393 compatible = "fixed-factor-clock";
394 #clock-cells = <0>;
395 clock-div = <3>;
396 clock-mult = <2>;
397 clocks = <&clk_fixed>;
398 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200399
400 osc {
401 compatible = "fixed-clock";
402 #clock-cells = <0>;
403 clock-frequency = <20000000>;
404 };
Stephen Warren135aa952016-06-17 09:44:00 -0600405 };
406
407 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600408 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600409 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200410 assigned-clocks = <&clk_sandbox 3>;
411 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600412 };
413
414 clk-test {
415 compatible = "sandbox,clk-test";
416 clocks = <&clk_fixed>,
417 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200418 <&clk_sandbox 0>,
419 <&clk_sandbox 3>,
420 <&clk_sandbox 2>;
421 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600422 };
423
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200424 ccf: clk-ccf {
425 compatible = "sandbox,clk-ccf";
426 };
427
Simon Glass171e9912015-05-22 15:42:15 -0600428 eth@10002000 {
429 compatible = "sandbox,eth";
430 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500431 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600432 };
433
434 eth_5: eth@10003000 {
435 compatible = "sandbox,eth";
436 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500437 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600438 };
439
Bin Meng71d79712015-08-27 22:25:53 -0700440 eth_3: sbe5 {
441 compatible = "sandbox,eth";
442 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500443 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700444 };
445
Simon Glass171e9912015-05-22 15:42:15 -0600446 eth@10004000 {
447 compatible = "sandbox,eth";
448 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500449 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600450 };
451
Rajan Vaja31b82172018-09-19 03:43:46 -0700452 firmware {
453 sandbox_firmware: sandbox-firmware {
454 compatible = "sandbox,firmware";
455 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200456
457 sandbox-scmi-agent@0 {
458 compatible = "sandbox,scmi-agent";
459 #address-cells = <1>;
460 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200461
462 clk_scmi0: protocol@14 {
463 reg = <0x14>;
464 #clock-cells = <1>;
465 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200466
467 reset_scmi0: protocol@16 {
468 reg = <0x16>;
469 #reset-cells = <1>;
470 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200471 };
472
473 sandbox-scmi-agent@1 {
474 compatible = "sandbox,scmi-agent";
475 #address-cells = <1>;
476 #size-cells = <0>;
477
Etienne Carriere87d4f272020-09-09 18:44:05 +0200478 clk_scmi1: protocol@14 {
479 reg = <0x14>;
480 #clock-cells = <1>;
481 };
482
Etienne Carriere358599e2020-09-09 18:44:00 +0200483 protocol@10 {
484 reg = <0x10>;
485 };
486 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700487 };
488
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100489 pinctrl-gpio {
490 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700491
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100492 gpio_a: base-gpios {
493 compatible = "sandbox,gpio";
494 gpio-controller;
495 #gpio-cells = <1>;
496 gpio-bank-name = "a";
497 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200498 hog_input_active_low {
499 gpio-hog;
500 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200501 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200502 };
503 hog_input_active_high {
504 gpio-hog;
505 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200506 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200507 };
508 hog_output_low {
509 gpio-hog;
510 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200511 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200512 };
513 hog_output_high {
514 gpio-hog;
515 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200516 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200517 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100518 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600519
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100520 gpio_b: extra-gpios {
521 compatible = "sandbox,gpio";
522 gpio-controller;
523 #gpio-cells = <5>;
524 gpio-bank-name = "b";
525 sandbox,gpio-count = <10>;
526 };
527
528 gpio_c: pinmux-gpios {
529 compatible = "sandbox,gpio";
530 gpio-controller;
531 #gpio-cells = <2>;
532 gpio-bank-name = "c";
533 sandbox,gpio-count = <10>;
534 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100535 };
536
Simon Glassecc2ed52014-12-10 08:55:55 -0700537 i2c@0 {
538 #address-cells = <1>;
539 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600540 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700541 compatible = "sandbox,i2c";
542 clock-frequency = <100000>;
543 eeprom@2c {
544 reg = <0x2c>;
545 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700546 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200547 partitions {
548 compatible = "fixed-partitions";
549 #address-cells = <1>;
550 #size-cells = <1>;
551 bootcount_i2c: bootcount@10 {
552 reg = <10 2>;
553 };
554 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700555 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200556
Simon Glass52d3bc52015-05-22 15:42:17 -0600557 rtc_0: rtc@43 {
558 reg = <0x43>;
559 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700560 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600561 };
562
563 rtc_1: rtc@61 {
564 reg = <0x61>;
565 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700566 sandbox,emul = <&emul1>;
567 };
568
569 i2c_emul: emul {
570 reg = <0xff>;
571 compatible = "sandbox,i2c-emul-parent";
572 emul_eeprom: emul-eeprom {
573 compatible = "sandbox,i2c-eeprom";
574 sandbox,filename = "i2c.bin";
575 sandbox,size = <256>;
576 };
577 emul0: emul0 {
578 compatible = "sandbox,i2c-rtc";
579 };
580 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600581 compatible = "sandbox,i2c-rtc";
582 };
583 };
584
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200585 sandbox_pmic: sandbox_pmic {
586 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700587 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200588 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200589
590 mc34708: pmic@41 {
591 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700592 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200593 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700594 };
595
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100596 bootcount@0 {
597 compatible = "u-boot,bootcount-rtc";
598 rtc = <&rtc_1>;
599 offset = <0x13>;
600 };
601
Michal Simekf692b472020-05-28 11:48:55 +0200602 bootcount {
603 compatible = "u-boot,bootcount-i2c-eeprom";
604 i2c-eeprom = <&bootcount_i2c>;
605 };
606
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100607 adc@0 {
608 compatible = "sandbox,adc";
609 vdd-supply = <&buck2>;
610 vss-microvolts = <0>;
611 };
612
Simon Glass02554352020-02-06 09:55:00 -0700613 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700614 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700615 interrupt-controller;
616 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700617 };
618
Simon Glass3c97c4f2016-01-18 19:52:26 -0700619 lcd {
620 u-boot,dm-pre-reloc;
621 compatible = "sandbox,lcd-sdl";
622 xres = <1366>;
623 yres = <768>;
624 };
625
Simon Glass3c43fba2015-07-06 12:54:34 -0600626 leds {
627 compatible = "gpio-leds";
628
629 iracibble {
630 gpios = <&gpio_a 1 0>;
631 label = "sandbox:red";
632 };
633
634 martinet {
635 gpios = <&gpio_a 2 0>;
636 label = "sandbox:green";
637 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200638
639 default_on {
640 gpios = <&gpio_a 5 0>;
641 label = "sandbox:default_on";
642 default-state = "on";
643 };
644
645 default_off {
646 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400647 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200648 default-state = "off";
649 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600650 };
651
Stephen Warren8961b522016-05-16 17:41:37 -0600652 mbox: mbox {
653 compatible = "sandbox,mbox";
654 #mbox-cells = <1>;
655 };
656
657 mbox-test {
658 compatible = "sandbox,mbox-test";
659 mboxes = <&mbox 100>, <&mbox 1>;
660 mbox-names = "other", "test";
661 };
662
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900663 cpus {
Sean Anderson7616e362020-09-28 10:52:23 -0400664 timebase-frequency = <2000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900665 cpu-test1 {
Sean Anderson7616e362020-09-28 10:52:23 -0400666 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900667 compatible = "sandbox,cpu_sandbox";
668 u-boot,dm-pre-reloc;
669 };
Mario Sixfa44b532018-08-06 10:23:44 +0200670
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900671 cpu-test2 {
672 compatible = "sandbox,cpu_sandbox";
673 u-boot,dm-pre-reloc;
674 };
Mario Sixfa44b532018-08-06 10:23:44 +0200675
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900676 cpu-test3 {
677 compatible = "sandbox,cpu_sandbox";
678 u-boot,dm-pre-reloc;
679 };
Mario Sixfa44b532018-08-06 10:23:44 +0200680 };
681
Dave Gerlach21e3c212020-07-15 23:39:58 -0500682 chipid: chipid {
683 compatible = "sandbox,soc";
684 };
685
Simon Glasse96fa6c2018-12-10 10:37:34 -0700686 i2s: i2s {
687 compatible = "sandbox,i2s";
688 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700689 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700690 };
691
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200692 nop-test_0 {
693 compatible = "sandbox,nop_sandbox1";
694 nop-test_1 {
695 compatible = "sandbox,nop_sandbox2";
696 bind = "True";
697 };
698 nop-test_2 {
699 compatible = "sandbox,nop_sandbox2";
700 bind = "False";
701 };
702 };
703
Mario Six004e67c2018-07-31 14:24:14 +0200704 misc-test {
705 compatible = "sandbox,misc_sandbox";
706 };
707
Simon Glasse48eeb92017-04-23 20:02:07 -0600708 mmc2 {
709 compatible = "sandbox,mmc";
710 };
711
712 mmc1 {
713 compatible = "sandbox,mmc";
714 };
715
716 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600717 compatible = "sandbox,mmc";
718 };
719
Simon Glassb45c8332019-02-16 20:24:50 -0700720 pch {
721 compatible = "sandbox,pch";
722 };
723
Tom Rini42c64d12020-02-11 12:41:23 -0500724 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700725 compatible = "sandbox,pci";
726 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500727 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700728 #address-cells = <3>;
729 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600730 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700731 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700732 pci@0,0 {
733 compatible = "pci-generic";
734 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600735 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700736 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300737 pci@1,0 {
738 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600739 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
740 reg = <0x02000814 0 0 0 0
741 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600742 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300743 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700744 p2sb-pci@2,0 {
745 compatible = "sandbox,p2sb";
746 reg = <0x02001010 0 0 0 0>;
747 sandbox,emul = <&p2sb_emul>;
748
749 adder {
750 intel,p2sb-port-id = <3>;
751 compatible = "sandbox,adder";
752 };
753 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700754 pci@1e,0 {
755 compatible = "sandbox,pmc";
756 reg = <0xf000 0 0 0 0>;
757 sandbox,emul = <&pmc_emul1e>;
758 acpi-base = <0x400>;
759 gpe0-dwx-mask = <0xf>;
760 gpe0-dwx-shift-base = <4>;
761 gpe0-dw = <6 7 9>;
762 gpe0-sts = <0x20>;
763 gpe0-en = <0x30>;
764 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700765 pci@1f,0 {
766 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600767 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
768 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600769 sandbox,emul = <&swap_case_emul0_1f>;
770 };
771 };
772
773 pci-emul0 {
774 compatible = "sandbox,pci-emul-parent";
775 swap_case_emul0_0: emul0@0,0 {
776 compatible = "sandbox,swap-case";
777 };
778 swap_case_emul0_1: emul0@1,0 {
779 compatible = "sandbox,swap-case";
780 use-ea;
781 };
782 swap_case_emul0_1f: emul0@1f,0 {
783 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700784 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700785 p2sb_emul: emul@2,0 {
786 compatible = "sandbox,p2sb-emul";
787 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700788 pmc_emul1e: emul@1e,0 {
789 compatible = "sandbox,pmc-emul";
790 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700791 };
792
Tom Rini42c64d12020-02-11 12:41:23 -0500793 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700794 compatible = "sandbox,pci";
795 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500796 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700797 #address-cells = <3>;
798 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700799 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
800 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
801 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700802 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200803 0x0c 0x00 0x1234 0x5678
804 0x10 0x00 0x1234 0x5678>;
805 pci@10,0 {
806 reg = <0x8000 0 0 0 0>;
807 };
Bin Mengdee4d752018-08-03 01:14:41 -0700808 };
809
Tom Rini42c64d12020-02-11 12:41:23 -0500810 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700811 compatible = "sandbox,pci";
812 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500813 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700814 #address-cells = <3>;
815 #size-cells = <2>;
816 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
817 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
818 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
819 pci@1f,0 {
820 compatible = "pci-generic";
821 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600822 sandbox,emul = <&swap_case_emul2_1f>;
823 };
824 };
825
826 pci-emul2 {
827 compatible = "sandbox,pci-emul-parent";
828 swap_case_emul2_1f: emul2@1f,0 {
829 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700830 };
831 };
832
Ramon Friedbb413332019-04-27 11:15:23 +0300833 pci_ep: pci_ep {
834 compatible = "sandbox,pci_ep";
835 };
836
Simon Glass98561572017-04-23 20:10:44 -0600837 probing {
838 compatible = "simple-bus";
839 test1 {
840 compatible = "denx,u-boot-probe-test";
841 };
842
843 test2 {
844 compatible = "denx,u-boot-probe-test";
845 };
846
847 test3 {
848 compatible = "denx,u-boot-probe-test";
849 };
850
851 test4 {
852 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100853 first-syscon = <&syscon0>;
854 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100855 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600856 };
857 };
858
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600859 pwrdom: power-domain {
860 compatible = "sandbox,power-domain";
861 #power-domain-cells = <1>;
862 };
863
864 power-domain-test {
865 compatible = "sandbox,power-domain-test";
866 power-domains = <&pwrdom 2>;
867 };
868
Simon Glass5d9a88f2018-10-01 12:22:40 -0600869 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600870 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600871 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600872 };
873
874 pwm2 {
875 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600876 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600877 };
878
Simon Glass64ce0ca2015-07-06 12:54:31 -0600879 ram {
880 compatible = "sandbox,ram";
881 };
882
Simon Glass5010d982015-07-06 12:54:29 -0600883 reset@0 {
884 compatible = "sandbox,warm-reset";
885 };
886
887 reset@1 {
888 compatible = "sandbox,reset";
889 };
890
Stephen Warren4581b712016-06-17 09:43:59 -0600891 resetc: reset-ctl {
892 compatible = "sandbox,reset-ctl";
893 #reset-cells = <1>;
894 };
895
896 reset-ctl-test {
897 compatible = "sandbox,reset-ctl-test";
898 resets = <&resetc 100>, <&resetc 2>;
899 reset-names = "other", "test";
900 };
901
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530902 rng {
903 compatible = "sandbox,sandbox-rng";
904 };
905
Nishanth Menon52159402015-09-17 15:42:41 -0500906 rproc_1: rproc@1 {
907 compatible = "sandbox,test-processor";
908 remoteproc-name = "remoteproc-test-dev1";
909 };
910
911 rproc_2: rproc@2 {
912 compatible = "sandbox,test-processor";
913 internal-memory-mapped;
914 remoteproc-name = "remoteproc-test-dev2";
915 };
916
Simon Glass5d9a88f2018-10-01 12:22:40 -0600917 panel {
918 compatible = "simple-panel";
919 backlight = <&backlight 0 100>;
920 };
921
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300922 smem@0 {
923 compatible = "sandbox,smem";
924 };
925
Simon Glassd4901892018-12-10 10:37:36 -0700926 sound {
927 compatible = "sandbox,sound";
928 cpu {
929 sound-dai = <&i2s 0>;
930 };
931
932 codec {
933 sound-dai = <&audio 0>;
934 };
935 };
936
Simon Glass0ae0cb72014-10-13 23:42:11 -0600937 spi@0 {
938 #address-cells = <1>;
939 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600940 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600941 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +0200942 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600943 spi.bin@0 {
944 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000945 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600946 spi-max-frequency = <40000000>;
947 sandbox,filename = "spi.bin";
948 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +0200949 spi.bin@1 {
950 reg = <1>;
951 compatible = "spansion,m25p16", "jedec,spi-nor";
952 spi-max-frequency = <50000000>;
953 sandbox,filename = "spi.bin";
954 spi-cpol;
955 spi-cpha;
956 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600957 };
958
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100959 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600960 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200961 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600962 };
963
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100964 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600965 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600966 reg = <0x20 5
967 0x28 6
968 0x30 7
969 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600970 };
971
Patrick Delaunaya442e612019-03-07 09:57:13 +0100972 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900973 compatible = "simple-mfd", "syscon";
974 reg = <0x40 5
975 0x48 6
976 0x50 7
977 0x58 8>;
978 };
979
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530980 syscon3: syscon@3 {
981 compatible = "simple-mfd", "syscon";
982 reg = <0x000100 0x10>;
983
984 muxcontroller0: a-mux-controller {
985 compatible = "mmio-mux";
986 #mux-control-cells = <1>;
987
988 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
989 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
990 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
991 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
992 u-boot,mux-autoprobe;
993 };
994 };
995
996 muxcontroller1: emul-mux-controller {
997 compatible = "mux-emul";
998 #mux-control-cells = <0>;
999 u-boot,mux-autoprobe;
1000 idle-state = <0xabcd>;
1001 };
1002
Simon Glass93f44e82020-12-16 21:20:27 -07001003 testfdtm0 {
1004 compatible = "denx,u-boot-fdtm-test";
1005 };
1006
1007 testfdtm1: testfdtm1 {
1008 compatible = "denx,u-boot-fdtm-test";
1009 };
1010
1011 testfdtm2 {
1012 compatible = "denx,u-boot-fdtm-test";
1013 };
1014
Sean Anderson7616e362020-09-28 10:52:23 -04001015 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001016 compatible = "sandbox,timer";
1017 clock-frequency = <1000000>;
1018 };
1019
Sean Anderson7616e362020-09-28 10:52:23 -04001020 timer@1 {
1021 compatible = "sandbox,timer";
1022 sandbox,timebase-frequency-fallback;
1023 };
1024
Miquel Raynalb91ad162018-05-15 11:57:27 +02001025 tpm2 {
1026 compatible = "sandbox,tpm2";
1027 };
1028
Simon Glass171e9912015-05-22 15:42:15 -06001029 uart0: serial {
1030 compatible = "sandbox,serial";
1031 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001032 };
1033
Simon Glasse00cb222015-03-25 12:23:05 -06001034 usb_0: usb@0 {
1035 compatible = "sandbox,usb";
1036 status = "disabled";
1037 hub {
1038 compatible = "sandbox,usb-hub";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1041 flash-stick {
1042 reg = <0>;
1043 compatible = "sandbox,usb-flash";
1044 };
1045 };
1046 };
1047
1048 usb_1: usb@1 {
1049 compatible = "sandbox,usb";
1050 hub {
1051 compatible = "usb-hub";
1052 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001053 #address-cells = <1>;
1054 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001055 hub-emul {
1056 compatible = "sandbox,usb-hub";
1057 #address-cells = <1>;
1058 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001059 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001060 reg = <0>;
1061 compatible = "sandbox,usb-flash";
1062 sandbox,filepath = "testflash.bin";
1063 };
1064
Simon Glass431cbd62015-11-08 23:48:01 -07001065 flash-stick@1 {
1066 reg = <1>;
1067 compatible = "sandbox,usb-flash";
1068 sandbox,filepath = "testflash1.bin";
1069 };
1070
1071 flash-stick@2 {
1072 reg = <2>;
1073 compatible = "sandbox,usb-flash";
1074 sandbox,filepath = "testflash2.bin";
1075 };
1076
Simon Glassbff1a712015-11-08 23:48:08 -07001077 keyb@3 {
1078 reg = <3>;
1079 compatible = "sandbox,usb-keyb";
1080 };
1081
Simon Glasse00cb222015-03-25 12:23:05 -06001082 };
Michael Wallec03b7612020-06-02 01:47:07 +02001083
1084 usbstor@1 {
1085 reg = <1>;
1086 };
1087 usbstor@3 {
1088 reg = <3>;
1089 };
Simon Glasse00cb222015-03-25 12:23:05 -06001090 };
1091 };
1092
1093 usb_2: usb@2 {
1094 compatible = "sandbox,usb";
1095 status = "disabled";
1096 };
1097
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001098 spmi: spmi@0 {
1099 compatible = "sandbox,spmi";
1100 #address-cells = <0x1>;
1101 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001102 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001103 pm8916@0 {
1104 compatible = "qcom,spmi-pmic";
1105 reg = <0x0 0x1>;
1106 #address-cells = <0x1>;
1107 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001108 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001109
1110 spmi_gpios: gpios@c000 {
1111 compatible = "qcom,pm8916-gpio";
1112 reg = <0xc000 0x400>;
1113 gpio-controller;
1114 gpio-count = <4>;
1115 #gpio-cells = <2>;
1116 gpio-bank-name="spmi";
1117 };
1118 };
1119 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001120
1121 wdt0: wdt@0 {
1122 compatible = "sandbox,wdt";
1123 };
Rob Clarkf2006802018-01-10 11:33:30 +01001124
Mario Six957983e2018-08-09 14:51:19 +02001125 axi: axi@0 {
1126 compatible = "sandbox,axi";
1127 #address-cells = <0x1>;
1128 #size-cells = <0x1>;
1129 store@0 {
1130 compatible = "sandbox,sandbox_store";
1131 reg = <0x0 0x400>;
1132 };
1133 };
1134
Rob Clarkf2006802018-01-10 11:33:30 +01001135 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001136 #address-cells = <1>;
1137 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001138 setting = "sunrise ohoka";
1139 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001140 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001141 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001142 chosen-test {
1143 compatible = "denx,u-boot-fdt-test";
1144 reg = <9 1>;
1145 };
1146 };
Mario Sixe8d52912018-03-12 14:53:33 +01001147
1148 translation-test@8000 {
1149 compatible = "simple-bus";
1150 reg = <0x8000 0x4000>;
1151
1152 #address-cells = <0x2>;
1153 #size-cells = <0x1>;
1154
1155 ranges = <0 0x0 0x8000 0x1000
1156 1 0x100 0x9000 0x1000
1157 2 0x200 0xA000 0x1000
1158 3 0x300 0xB000 0x1000
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001159 4 0x400 0xC000 0x1000
Mario Sixe8d52912018-03-12 14:53:33 +01001160 >;
1161
Fabien Dessenne641067f2019-05-31 15:11:30 +02001162 dma-ranges = <0 0x000 0x10000000 0x1000
1163 1 0x100 0x20000000 0x1000
1164 >;
1165
Mario Sixe8d52912018-03-12 14:53:33 +01001166 dev@0,0 {
1167 compatible = "denx,u-boot-fdt-dummy";
1168 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001169 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001170 };
1171
1172 dev@1,100 {
1173 compatible = "denx,u-boot-fdt-dummy";
1174 reg = <1 0x100 0x1000>;
1175
1176 };
1177
1178 dev@2,200 {
1179 compatible = "denx,u-boot-fdt-dummy";
1180 reg = <2 0x200 0x1000>;
1181 };
1182
1183
1184 noxlatebus@3,300 {
1185 compatible = "simple-bus";
1186 reg = <3 0x300 0x1000>;
1187
1188 #address-cells = <0x1>;
1189 #size-cells = <0x0>;
1190
1191 dev@42 {
1192 compatible = "denx,u-boot-fdt-dummy";
1193 reg = <0x42>;
1194 };
1195 };
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001196
1197 xlatebus@4,400 {
1198 compatible = "sandbox,zero-size-cells-bus";
1199 reg = <4 0x400 0x1000>;
1200 #address-cells = <1>;
1201 #size-cells = <1>;
1202 ranges = <0 4 0x400 0x1000>;
1203
1204 devs {
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1207
1208 dev@19 {
1209 compatible = "denx,u-boot-fdt-dummy";
1210 reg = <0x19>;
1211 };
1212 };
1213 };
1214
Mario Sixe8d52912018-03-12 14:53:33 +01001215 };
Mario Six4eea5312018-09-27 09:19:31 +02001216
1217 osd {
1218 compatible = "sandbox,sandbox_osd";
1219 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001220
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001221 sandbox_tee {
1222 compatible = "sandbox,tee";
1223 };
Bin Meng4f89d492018-10-15 02:21:26 -07001224
1225 sandbox_virtio1 {
1226 compatible = "sandbox,virtio1";
1227 };
1228
1229 sandbox_virtio2 {
1230 compatible = "sandbox,virtio2";
1231 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001232
Etienne Carriere87d4f272020-09-09 18:44:05 +02001233 sandbox_scmi {
1234 compatible = "sandbox,scmi-devices";
1235 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001236 resets = <&reset_scmi0 3>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001237 };
1238
Patrice Chotardf41a8242018-10-24 14:10:23 +02001239 pinctrl {
1240 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001241
Sean Anderson7f0f1802020-09-14 11:01:57 -04001242 pinctrl-names = "default", "alternate";
1243 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1244 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001245
Sean Anderson7f0f1802020-09-14 11:01:57 -04001246 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001247 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001248 pins = "P5";
1249 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001250 bias-pull-up;
1251 input-disable;
1252 };
1253 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001254 pins = "P6";
1255 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001256 output-high;
1257 drive-open-drain;
1258 };
1259 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001260 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001261 bias-pull-down;
1262 input-enable;
1263 };
1264 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001265 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001266 bias-disable;
1267 };
1268 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001269
1270 pinctrl_i2c: i2c {
1271 groups {
1272 groups = "I2C_UART";
1273 function = "I2C";
1274 };
1275
1276 pins {
1277 pins = "P0", "P1";
1278 drive-open-drain;
1279 };
1280 };
1281
1282 pinctrl_i2s: i2s {
1283 groups = "SPI_I2S";
1284 function = "I2S";
1285 };
1286
1287 pinctrl_spi: spi {
1288 groups = "SPI_I2S";
1289 function = "SPI";
1290
1291 cs {
1292 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1293 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1294 };
1295 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001296 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001297
1298 hwspinlock@0 {
1299 compatible = "sandbox,hwspinlock";
1300 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001301
1302 dma: dma {
1303 compatible = "sandbox,dma";
1304 #dma-cells = <1>;
1305
1306 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1307 dma-names = "m2m", "tx0", "rx0";
1308 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001309
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001310 /*
1311 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1312 * end of the test. If parent mdio is removed first, clean-up of the
1313 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1314 * active at the end of the test. That it turn doesn't allow the mdio
1315 * class to be destroyed, triggering an error.
1316 */
1317 mdio-mux-test {
1318 compatible = "sandbox,mdio-mux";
1319 #address-cells = <1>;
1320 #size-cells = <0>;
1321 mdio-parent-bus = <&mdio>;
1322
1323 mdio-ch-test@0 {
1324 reg = <0>;
1325 };
1326 mdio-ch-test@1 {
1327 reg = <1>;
1328 };
1329 };
1330
1331 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001332 compatible = "sandbox,mdio";
1333 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001334
1335 pm-bus-test {
1336 compatible = "simple-pm-bus";
1337 clocks = <&clk_sandbox 4>;
1338 power-domains = <&pwrdom 1>;
1339 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001340
1341 resetc2: syscon-reset {
1342 compatible = "syscon-reset";
1343 #reset-cells = <1>;
1344 regmap = <&syscon0>;
1345 offset = <1>;
1346 mask = <0x27FFFFFF>;
1347 assert-high = <0>;
1348 };
1349
1350 syscon-reset-test {
1351 compatible = "sandbox,misc_sandbox";
1352 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1353 reset-names = "valid", "no_mask", "out_of_range";
1354 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301355
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001356 sysinfo {
1357 compatible = "sandbox,sysinfo-sandbox";
1358 };
1359
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301360 some_regmapped-bus {
1361 #address-cells = <0x1>;
1362 #size-cells = <0x1>;
1363
1364 ranges = <0x0 0x0 0x10>;
1365 compatible = "simple-bus";
1366
1367 regmap-test_0 {
1368 reg = <0 0x10>;
1369 compatible = "sandbox,regmap_test";
1370 };
1371 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001372};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001373
1374#include "sandbox_pmic.dtsi"