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Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05306#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01007
Simon Glass2e7d35d2014-02-26 15:59:21 -07008/ {
9 model = "sandbox";
10 compatible = "sandbox";
11 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060012 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070013
Simon Glass00606d72014-07-23 06:55:03 -060014 aliases {
15 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060016 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070017 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060018 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060019 gpio1 = &gpio_a;
20 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010021 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070022 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060023 mmc0 = "/mmc0";
24 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070025 pci0 = &pci0;
26 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070027 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020028 remoteproc0 = &rproc_1;
29 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060030 rtc0 = &rtc_0;
31 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060032 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020033 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070034 testbus3 = "/some-bus";
35 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070036 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070037 testfdt3 = "/b-test";
38 testfdt5 = "/some-bus/c-test@5";
39 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070040 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020041 fdt-dummy0 = "/translation-test@8000/dev@0,0";
42 fdt-dummy1 = "/translation-test@8000/dev@1,100";
43 fdt-dummy2 = "/translation-test@8000/dev@2,200";
44 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchid64b9cd2020-12-30 00:16:21 +010045 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glasse00cb222015-03-25 12:23:05 -060046 usb0 = &usb_0;
47 usb1 = &usb_1;
48 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020049 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020050 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060051 };
52
Simon Glassce6d99a2018-12-10 10:37:33 -070053 audio: audio-codec {
54 compatible = "sandbox,audio-codec";
55 #sound-dai-cells = <1>;
56 };
57
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020058 buttons {
59 compatible = "gpio-keys";
60
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020061 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020062 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020063 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020064 };
65
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020066 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020067 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020068 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020069 };
70 };
71
Simon Glasse96fa6c2018-12-10 10:37:34 -070072 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060073 reg = <0 0>;
74 compatible = "google,cros-ec-sandbox";
75
76 /*
77 * This describes the flash memory within the EC. Note
78 * that the STM32L flash erases to 0, not 0xff.
79 */
80 flash {
81 image-pos = <0x08000000>;
82 size = <0x20000>;
83 erase-value = <0>;
84
85 /* Information for sandbox */
86 ro {
87 image-pos = <0>;
88 size = <0xf000>;
89 };
90 wp-ro {
91 image-pos = <0xf000>;
92 size = <0x1000>;
93 };
94 rw {
95 image-pos = <0x10000>;
96 size = <0x10000>;
97 };
98 };
99 };
100
Yannick Fertré23f965a2019-10-07 15:29:05 +0200101 dsi_host: dsi_host {
102 compatible = "sandbox,dsi-host";
103 };
104
Simon Glass2e7d35d2014-02-26 15:59:21 -0700105 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600106 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700107 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600108 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700109 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600110 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100111 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
112 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700113 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100114 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
115 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
116 <&gpio_b 7 GPIO_IN 3 2 1>,
117 <&gpio_b 8 GPIO_OUT 3 2 1>,
118 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100119 test3-gpios =
120 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
121 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
122 <&gpio_c 2 GPIO_OUT>,
123 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
124 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200125 <&gpio_c 5 GPIO_IN>,
126 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
127 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530128 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
129 test5-gpios = <&gpio_a 19>;
130
Simon Glassa1b17e42018-12-10 10:37:37 -0700131 int-value = <1234>;
132 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200133 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200134 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600135 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700136 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600137 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200138 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530139
140 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
141 <&muxcontroller0 2>, <&muxcontroller0 3>,
142 <&muxcontroller1>;
143 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
144 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100145 display-timings {
146 timing0: 240x320 {
147 clock-frequency = <6500000>;
148 hactive = <240>;
149 vactive = <320>;
150 hfront-porch = <6>;
151 hback-porch = <7>;
152 hsync-len = <1>;
153 vback-porch = <5>;
154 vfront-porch = <8>;
155 vsync-len = <2>;
156 hsync-active = <1>;
157 vsync-active = <0>;
158 de-active = <1>;
159 pixelclk-active = <1>;
160 interlaced;
161 doublescan;
162 doubleclk;
163 };
164 timing1: 480x800 {
165 clock-frequency = <9000000>;
166 hactive = <480>;
167 vactive = <800>;
168 hfront-porch = <10>;
169 hback-porch = <59>;
170 hsync-len = <12>;
171 vback-porch = <15>;
172 vfront-porch = <17>;
173 vsync-len = <16>;
174 hsync-active = <0>;
175 vsync-active = <1>;
176 de-active = <0>;
177 pixelclk-active = <0>;
178 };
179 timing2: 800x480 {
180 clock-frequency = <33500000>;
181 hactive = <800>;
182 vactive = <480>;
183 hback-porch = <89>;
184 hfront-porch = <164>;
185 vback-porch = <23>;
186 vfront-porch = <10>;
187 hsync-len = <11>;
188 vsync-len = <13>;
189 };
190 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700191 };
192
193 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600194 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700195 compatible = "not,compatible";
196 };
197
198 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600199 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700200 };
201
Simon Glass5d9a88f2018-10-01 12:22:40 -0600202 backlight: backlight {
203 compatible = "pwm-backlight";
204 enable-gpios = <&gpio_a 1>;
205 power-supply = <&ldo_1>;
206 pwms = <&pwm 0 1000>;
207 default-brightness-level = <5>;
208 brightness-levels = <0 16 32 64 128 170 202 234 255>;
209 };
210
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200211 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200212 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200213 bind-test-child1 {
214 compatible = "sandbox,phy";
215 #phy-cells = <1>;
216 };
217
218 bind-test-child2 {
219 compatible = "simple-bus";
220 };
221 };
222
Simon Glass2e7d35d2014-02-26 15:59:21 -0700223 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600224 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700225 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600226 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700227 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530228
229 mux-controls = <&muxcontroller0 0>;
230 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700231 };
232
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200233 phy_provider0: gen_phy@0 {
234 compatible = "sandbox,phy";
235 #phy-cells = <1>;
236 };
237
238 phy_provider1: gen_phy@1 {
239 compatible = "sandbox,phy";
240 #phy-cells = <0>;
241 broken;
242 };
243
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200244 phy_provider2: gen_phy@2 {
245 compatible = "sandbox,phy";
246 #phy-cells = <0>;
247 };
248
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200249 gen_phy_user: gen_phy_user {
250 compatible = "simple-bus";
251 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
252 phy-names = "phy1", "phy2", "phy3";
253 };
254
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200255 gen_phy_user1: gen_phy_user1 {
256 compatible = "simple-bus";
257 phys = <&phy_provider0 0>, <&phy_provider2>;
258 phy-names = "phy1", "phy2";
259 };
260
Simon Glass2e7d35d2014-02-26 15:59:21 -0700261 some-bus {
262 #address-cells = <1>;
263 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600264 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600265 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600266 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700267 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600268 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700269 compatible = "denx,u-boot-fdt-test";
270 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600271 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700272 ping-add = <5>;
273 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600274 c-test@0 {
275 compatible = "denx,u-boot-fdt-test";
276 reg = <0>;
277 ping-expect = <6>;
278 ping-add = <6>;
279 };
280 c-test@1 {
281 compatible = "denx,u-boot-fdt-test";
282 reg = <1>;
283 ping-expect = <7>;
284 ping-add = <7>;
285 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700286 };
287
288 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600289 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600290 ping-expect = <6>;
291 ping-add = <6>;
292 compatible = "google,another-fdt-test";
293 };
294
295 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600296 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600297 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700298 ping-add = <6>;
299 compatible = "google,another-fdt-test";
300 };
301
Simon Glass9cc36a22015-01-25 08:27:05 -0700302 f-test {
303 compatible = "denx,u-boot-fdt-test";
304 };
305
306 g-test {
307 compatible = "denx,u-boot-fdt-test";
308 };
309
Bin Meng2786cd72018-10-10 22:07:01 -0700310 h-test {
311 compatible = "denx,u-boot-fdt-test1";
312 };
313
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200314 i-test {
315 compatible = "mediatek,u-boot-fdt-test";
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 subnode@0 {
320 reg = <0>;
321 };
322
323 subnode@1 {
324 reg = <1>;
325 };
326
327 subnode@2 {
328 reg = <2>;
329 };
330 };
331
Simon Glassdc12ebb2019-12-29 21:19:25 -0700332 devres-test {
333 compatible = "denx,u-boot-devres-test";
334 };
335
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530336 another-test {
337 reg = <0 2>;
338 compatible = "denx,u-boot-fdt-test";
339 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
340 test5-gpios = <&gpio_a 19>;
341 };
342
Simon Glass0f7b1112020-07-07 13:12:06 -0600343 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600344 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600345 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600346 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600347 child {
348 compatible = "denx,u-boot-acpi-test";
349 };
Simon Glassf50cc952020-04-08 16:57:34 -0600350 };
351
Simon Glass0f7b1112020-07-07 13:12:06 -0600352 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600353 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600354 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600355 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600356 };
357
Patrice Chotardee87a092017-09-04 14:55:57 +0200358 clocks {
359 clk_fixed: clk-fixed {
360 compatible = "fixed-clock";
361 #clock-cells = <0>;
362 clock-frequency = <1234>;
363 };
Anup Patelb630d572019-02-25 08:14:55 +0000364
365 clk_fixed_factor: clk-fixed-factor {
366 compatible = "fixed-factor-clock";
367 #clock-cells = <0>;
368 clock-div = <3>;
369 clock-mult = <2>;
370 clocks = <&clk_fixed>;
371 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200372
373 osc {
374 compatible = "fixed-clock";
375 #clock-cells = <0>;
376 clock-frequency = <20000000>;
377 };
Stephen Warren135aa952016-06-17 09:44:00 -0600378 };
379
380 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600381 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600382 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200383 assigned-clocks = <&clk_sandbox 3>;
384 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600385 };
386
387 clk-test {
388 compatible = "sandbox,clk-test";
389 clocks = <&clk_fixed>,
390 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200391 <&clk_sandbox 0>,
392 <&clk_sandbox 3>,
393 <&clk_sandbox 2>;
394 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600395 };
396
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200397 ccf: clk-ccf {
398 compatible = "sandbox,clk-ccf";
399 };
400
Simon Glass171e9912015-05-22 15:42:15 -0600401 eth@10002000 {
402 compatible = "sandbox,eth";
403 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500404 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600405 };
406
407 eth_5: eth@10003000 {
408 compatible = "sandbox,eth";
409 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500410 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600411 };
412
Bin Meng71d79712015-08-27 22:25:53 -0700413 eth_3: sbe5 {
414 compatible = "sandbox,eth";
415 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500416 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700417 };
418
Simon Glass171e9912015-05-22 15:42:15 -0600419 eth@10004000 {
420 compatible = "sandbox,eth";
421 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500422 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600423 };
424
Rajan Vaja31b82172018-09-19 03:43:46 -0700425 firmware {
426 sandbox_firmware: sandbox-firmware {
427 compatible = "sandbox,firmware";
428 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200429
430 sandbox-scmi-agent@0 {
431 compatible = "sandbox,scmi-agent";
432 #address-cells = <1>;
433 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200434
435 clk_scmi0: protocol@14 {
436 reg = <0x14>;
437 #clock-cells = <1>;
438 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200439
440 reset_scmi0: protocol@16 {
441 reg = <0x16>;
442 #reset-cells = <1>;
443 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200444 };
445
446 sandbox-scmi-agent@1 {
447 compatible = "sandbox,scmi-agent";
448 #address-cells = <1>;
449 #size-cells = <0>;
450
Etienne Carriere87d4f272020-09-09 18:44:05 +0200451 clk_scmi1: protocol@14 {
452 reg = <0x14>;
453 #clock-cells = <1>;
454 };
455
Etienne Carriere358599e2020-09-09 18:44:00 +0200456 protocol@10 {
457 reg = <0x10>;
458 };
459 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700460 };
461
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100462 pinctrl-gpio {
463 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700464
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100465 gpio_a: base-gpios {
466 compatible = "sandbox,gpio";
467 gpio-controller;
468 #gpio-cells = <1>;
469 gpio-bank-name = "a";
470 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200471 hog_input_active_low {
472 gpio-hog;
473 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200474 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200475 };
476 hog_input_active_high {
477 gpio-hog;
478 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200479 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200480 };
481 hog_output_low {
482 gpio-hog;
483 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200484 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200485 };
486 hog_output_high {
487 gpio-hog;
488 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200489 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200490 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100491 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600492
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100493 gpio_b: extra-gpios {
494 compatible = "sandbox,gpio";
495 gpio-controller;
496 #gpio-cells = <5>;
497 gpio-bank-name = "b";
498 sandbox,gpio-count = <10>;
499 };
500
501 gpio_c: pinmux-gpios {
502 compatible = "sandbox,gpio";
503 gpio-controller;
504 #gpio-cells = <2>;
505 gpio-bank-name = "c";
506 sandbox,gpio-count = <10>;
507 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100508 };
509
Simon Glassecc2ed52014-12-10 08:55:55 -0700510 i2c@0 {
511 #address-cells = <1>;
512 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600513 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700514 compatible = "sandbox,i2c";
515 clock-frequency = <100000>;
516 eeprom@2c {
517 reg = <0x2c>;
518 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700519 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200520 partitions {
521 compatible = "fixed-partitions";
522 #address-cells = <1>;
523 #size-cells = <1>;
524 bootcount_i2c: bootcount@10 {
525 reg = <10 2>;
526 };
527 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700528 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200529
Simon Glass52d3bc52015-05-22 15:42:17 -0600530 rtc_0: rtc@43 {
531 reg = <0x43>;
532 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700533 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600534 };
535
536 rtc_1: rtc@61 {
537 reg = <0x61>;
538 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700539 sandbox,emul = <&emul1>;
540 };
541
542 i2c_emul: emul {
543 reg = <0xff>;
544 compatible = "sandbox,i2c-emul-parent";
545 emul_eeprom: emul-eeprom {
546 compatible = "sandbox,i2c-eeprom";
547 sandbox,filename = "i2c.bin";
548 sandbox,size = <256>;
549 };
550 emul0: emul0 {
551 compatible = "sandbox,i2c-rtc";
552 };
553 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600554 compatible = "sandbox,i2c-rtc";
555 };
556 };
557
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200558 sandbox_pmic: sandbox_pmic {
559 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700560 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200561 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200562
563 mc34708: pmic@41 {
564 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700565 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200566 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700567 };
568
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100569 bootcount@0 {
570 compatible = "u-boot,bootcount-rtc";
571 rtc = <&rtc_1>;
572 offset = <0x13>;
573 };
574
Michal Simekf692b472020-05-28 11:48:55 +0200575 bootcount {
576 compatible = "u-boot,bootcount-i2c-eeprom";
577 i2c-eeprom = <&bootcount_i2c>;
578 };
579
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100580 adc@0 {
581 compatible = "sandbox,adc";
582 vdd-supply = <&buck2>;
583 vss-microvolts = <0>;
584 };
585
Simon Glass02554352020-02-06 09:55:00 -0700586 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700587 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700588 interrupt-controller;
589 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700590 };
591
Simon Glass3c97c4f2016-01-18 19:52:26 -0700592 lcd {
593 u-boot,dm-pre-reloc;
594 compatible = "sandbox,lcd-sdl";
595 xres = <1366>;
596 yres = <768>;
597 };
598
Simon Glass3c43fba2015-07-06 12:54:34 -0600599 leds {
600 compatible = "gpio-leds";
601
602 iracibble {
603 gpios = <&gpio_a 1 0>;
604 label = "sandbox:red";
605 };
606
607 martinet {
608 gpios = <&gpio_a 2 0>;
609 label = "sandbox:green";
610 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200611
612 default_on {
613 gpios = <&gpio_a 5 0>;
614 label = "sandbox:default_on";
615 default-state = "on";
616 };
617
618 default_off {
619 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400620 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200621 default-state = "off";
622 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600623 };
624
Stephen Warren8961b522016-05-16 17:41:37 -0600625 mbox: mbox {
626 compatible = "sandbox,mbox";
627 #mbox-cells = <1>;
628 };
629
630 mbox-test {
631 compatible = "sandbox,mbox-test";
632 mboxes = <&mbox 100>, <&mbox 1>;
633 mbox-names = "other", "test";
634 };
635
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900636 cpus {
Sean Anderson7616e362020-09-28 10:52:23 -0400637 timebase-frequency = <2000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900638 cpu-test1 {
Sean Anderson7616e362020-09-28 10:52:23 -0400639 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900640 compatible = "sandbox,cpu_sandbox";
641 u-boot,dm-pre-reloc;
642 };
Mario Sixfa44b532018-08-06 10:23:44 +0200643
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900644 cpu-test2 {
645 compatible = "sandbox,cpu_sandbox";
646 u-boot,dm-pre-reloc;
647 };
Mario Sixfa44b532018-08-06 10:23:44 +0200648
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900649 cpu-test3 {
650 compatible = "sandbox,cpu_sandbox";
651 u-boot,dm-pre-reloc;
652 };
Mario Sixfa44b532018-08-06 10:23:44 +0200653 };
654
Dave Gerlach21e3c212020-07-15 23:39:58 -0500655 chipid: chipid {
656 compatible = "sandbox,soc";
657 };
658
Simon Glasse96fa6c2018-12-10 10:37:34 -0700659 i2s: i2s {
660 compatible = "sandbox,i2s";
661 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700662 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700663 };
664
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200665 nop-test_0 {
666 compatible = "sandbox,nop_sandbox1";
667 nop-test_1 {
668 compatible = "sandbox,nop_sandbox2";
669 bind = "True";
670 };
671 nop-test_2 {
672 compatible = "sandbox,nop_sandbox2";
673 bind = "False";
674 };
675 };
676
Mario Six004e67c2018-07-31 14:24:14 +0200677 misc-test {
678 compatible = "sandbox,misc_sandbox";
679 };
680
Simon Glasse48eeb92017-04-23 20:02:07 -0600681 mmc2 {
682 compatible = "sandbox,mmc";
683 };
684
685 mmc1 {
686 compatible = "sandbox,mmc";
687 };
688
689 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600690 compatible = "sandbox,mmc";
691 };
692
Simon Glassb45c8332019-02-16 20:24:50 -0700693 pch {
694 compatible = "sandbox,pch";
695 };
696
Tom Rini42c64d12020-02-11 12:41:23 -0500697 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700698 compatible = "sandbox,pci";
699 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500700 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700701 #address-cells = <3>;
702 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600703 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700704 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700705 pci@0,0 {
706 compatible = "pci-generic";
707 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600708 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700709 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300710 pci@1,0 {
711 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600712 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
713 reg = <0x02000814 0 0 0 0
714 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600715 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300716 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700717 p2sb-pci@2,0 {
718 compatible = "sandbox,p2sb";
719 reg = <0x02001010 0 0 0 0>;
720 sandbox,emul = <&p2sb_emul>;
721
722 adder {
723 intel,p2sb-port-id = <3>;
724 compatible = "sandbox,adder";
725 };
726 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700727 pci@1e,0 {
728 compatible = "sandbox,pmc";
729 reg = <0xf000 0 0 0 0>;
730 sandbox,emul = <&pmc_emul1e>;
731 acpi-base = <0x400>;
732 gpe0-dwx-mask = <0xf>;
733 gpe0-dwx-shift-base = <4>;
734 gpe0-dw = <6 7 9>;
735 gpe0-sts = <0x20>;
736 gpe0-en = <0x30>;
737 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700738 pci@1f,0 {
739 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600740 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
741 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600742 sandbox,emul = <&swap_case_emul0_1f>;
743 };
744 };
745
746 pci-emul0 {
747 compatible = "sandbox,pci-emul-parent";
748 swap_case_emul0_0: emul0@0,0 {
749 compatible = "sandbox,swap-case";
750 };
751 swap_case_emul0_1: emul0@1,0 {
752 compatible = "sandbox,swap-case";
753 use-ea;
754 };
755 swap_case_emul0_1f: emul0@1f,0 {
756 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700757 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700758 p2sb_emul: emul@2,0 {
759 compatible = "sandbox,p2sb-emul";
760 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700761 pmc_emul1e: emul@1e,0 {
762 compatible = "sandbox,pmc-emul";
763 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700764 };
765
Tom Rini42c64d12020-02-11 12:41:23 -0500766 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700767 compatible = "sandbox,pci";
768 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500769 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700770 #address-cells = <3>;
771 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700772 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
773 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
774 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700775 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200776 0x0c 0x00 0x1234 0x5678
777 0x10 0x00 0x1234 0x5678>;
778 pci@10,0 {
779 reg = <0x8000 0 0 0 0>;
780 };
Bin Mengdee4d752018-08-03 01:14:41 -0700781 };
782
Tom Rini42c64d12020-02-11 12:41:23 -0500783 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700784 compatible = "sandbox,pci";
785 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500786 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700787 #address-cells = <3>;
788 #size-cells = <2>;
789 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
790 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
791 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
792 pci@1f,0 {
793 compatible = "pci-generic";
794 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600795 sandbox,emul = <&swap_case_emul2_1f>;
796 };
797 };
798
799 pci-emul2 {
800 compatible = "sandbox,pci-emul-parent";
801 swap_case_emul2_1f: emul2@1f,0 {
802 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700803 };
804 };
805
Ramon Friedbb413332019-04-27 11:15:23 +0300806 pci_ep: pci_ep {
807 compatible = "sandbox,pci_ep";
808 };
809
Simon Glass98561572017-04-23 20:10:44 -0600810 probing {
811 compatible = "simple-bus";
812 test1 {
813 compatible = "denx,u-boot-probe-test";
814 };
815
816 test2 {
817 compatible = "denx,u-boot-probe-test";
818 };
819
820 test3 {
821 compatible = "denx,u-boot-probe-test";
822 };
823
824 test4 {
825 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100826 first-syscon = <&syscon0>;
827 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100828 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600829 };
830 };
831
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600832 pwrdom: power-domain {
833 compatible = "sandbox,power-domain";
834 #power-domain-cells = <1>;
835 };
836
837 power-domain-test {
838 compatible = "sandbox,power-domain-test";
839 power-domains = <&pwrdom 2>;
840 };
841
Simon Glass5d9a88f2018-10-01 12:22:40 -0600842 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600843 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600844 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600845 };
846
847 pwm2 {
848 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600849 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600850 };
851
Simon Glass64ce0ca2015-07-06 12:54:31 -0600852 ram {
853 compatible = "sandbox,ram";
854 };
855
Simon Glass5010d982015-07-06 12:54:29 -0600856 reset@0 {
857 compatible = "sandbox,warm-reset";
858 };
859
860 reset@1 {
861 compatible = "sandbox,reset";
862 };
863
Stephen Warren4581b712016-06-17 09:43:59 -0600864 resetc: reset-ctl {
865 compatible = "sandbox,reset-ctl";
866 #reset-cells = <1>;
867 };
868
869 reset-ctl-test {
870 compatible = "sandbox,reset-ctl-test";
871 resets = <&resetc 100>, <&resetc 2>;
872 reset-names = "other", "test";
873 };
874
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530875 rng {
876 compatible = "sandbox,sandbox-rng";
877 };
878
Nishanth Menon52159402015-09-17 15:42:41 -0500879 rproc_1: rproc@1 {
880 compatible = "sandbox,test-processor";
881 remoteproc-name = "remoteproc-test-dev1";
882 };
883
884 rproc_2: rproc@2 {
885 compatible = "sandbox,test-processor";
886 internal-memory-mapped;
887 remoteproc-name = "remoteproc-test-dev2";
888 };
889
Simon Glass5d9a88f2018-10-01 12:22:40 -0600890 panel {
891 compatible = "simple-panel";
892 backlight = <&backlight 0 100>;
893 };
894
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300895 smem@0 {
896 compatible = "sandbox,smem";
897 };
898
Simon Glassd4901892018-12-10 10:37:36 -0700899 sound {
900 compatible = "sandbox,sound";
901 cpu {
902 sound-dai = <&i2s 0>;
903 };
904
905 codec {
906 sound-dai = <&audio 0>;
907 };
908 };
909
Simon Glass0ae0cb72014-10-13 23:42:11 -0600910 spi@0 {
911 #address-cells = <1>;
912 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600913 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600914 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +0200915 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600916 spi.bin@0 {
917 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000918 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600919 spi-max-frequency = <40000000>;
920 sandbox,filename = "spi.bin";
921 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +0200922 spi.bin@1 {
923 reg = <1>;
924 compatible = "spansion,m25p16", "jedec,spi-nor";
925 spi-max-frequency = <50000000>;
926 sandbox,filename = "spi.bin";
927 spi-cpol;
928 spi-cpha;
929 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600930 };
931
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100932 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600933 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200934 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600935 };
936
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100937 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600938 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600939 reg = <0x20 5
940 0x28 6
941 0x30 7
942 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600943 };
944
Patrick Delaunaya442e612019-03-07 09:57:13 +0100945 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900946 compatible = "simple-mfd", "syscon";
947 reg = <0x40 5
948 0x48 6
949 0x50 7
950 0x58 8>;
951 };
952
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530953 syscon3: syscon@3 {
954 compatible = "simple-mfd", "syscon";
955 reg = <0x000100 0x10>;
956
957 muxcontroller0: a-mux-controller {
958 compatible = "mmio-mux";
959 #mux-control-cells = <1>;
960
961 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
962 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
963 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
964 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
965 u-boot,mux-autoprobe;
966 };
967 };
968
969 muxcontroller1: emul-mux-controller {
970 compatible = "mux-emul";
971 #mux-control-cells = <0>;
972 u-boot,mux-autoprobe;
973 idle-state = <0xabcd>;
974 };
975
Simon Glass93f44e82020-12-16 21:20:27 -0700976 testfdtm0 {
977 compatible = "denx,u-boot-fdtm-test";
978 };
979
980 testfdtm1: testfdtm1 {
981 compatible = "denx,u-boot-fdtm-test";
982 };
983
984 testfdtm2 {
985 compatible = "denx,u-boot-fdtm-test";
986 };
987
Sean Anderson7616e362020-09-28 10:52:23 -0400988 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +0800989 compatible = "sandbox,timer";
990 clock-frequency = <1000000>;
991 };
992
Sean Anderson7616e362020-09-28 10:52:23 -0400993 timer@1 {
994 compatible = "sandbox,timer";
995 sandbox,timebase-frequency-fallback;
996 };
997
Miquel Raynalb91ad162018-05-15 11:57:27 +0200998 tpm2 {
999 compatible = "sandbox,tpm2";
1000 };
1001
Simon Glass171e9912015-05-22 15:42:15 -06001002 uart0: serial {
1003 compatible = "sandbox,serial";
1004 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001005 };
1006
Simon Glasse00cb222015-03-25 12:23:05 -06001007 usb_0: usb@0 {
1008 compatible = "sandbox,usb";
1009 status = "disabled";
1010 hub {
1011 compatible = "sandbox,usb-hub";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 flash-stick {
1015 reg = <0>;
1016 compatible = "sandbox,usb-flash";
1017 };
1018 };
1019 };
1020
1021 usb_1: usb@1 {
1022 compatible = "sandbox,usb";
1023 hub {
1024 compatible = "usb-hub";
1025 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001026 #address-cells = <1>;
1027 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001028 hub-emul {
1029 compatible = "sandbox,usb-hub";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001032 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001033 reg = <0>;
1034 compatible = "sandbox,usb-flash";
1035 sandbox,filepath = "testflash.bin";
1036 };
1037
Simon Glass431cbd62015-11-08 23:48:01 -07001038 flash-stick@1 {
1039 reg = <1>;
1040 compatible = "sandbox,usb-flash";
1041 sandbox,filepath = "testflash1.bin";
1042 };
1043
1044 flash-stick@2 {
1045 reg = <2>;
1046 compatible = "sandbox,usb-flash";
1047 sandbox,filepath = "testflash2.bin";
1048 };
1049
Simon Glassbff1a712015-11-08 23:48:08 -07001050 keyb@3 {
1051 reg = <3>;
1052 compatible = "sandbox,usb-keyb";
1053 };
1054
Simon Glasse00cb222015-03-25 12:23:05 -06001055 };
Michael Wallec03b7612020-06-02 01:47:07 +02001056
1057 usbstor@1 {
1058 reg = <1>;
1059 };
1060 usbstor@3 {
1061 reg = <3>;
1062 };
Simon Glasse00cb222015-03-25 12:23:05 -06001063 };
1064 };
1065
1066 usb_2: usb@2 {
1067 compatible = "sandbox,usb";
1068 status = "disabled";
1069 };
1070
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001071 spmi: spmi@0 {
1072 compatible = "sandbox,spmi";
1073 #address-cells = <0x1>;
1074 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001075 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001076 pm8916@0 {
1077 compatible = "qcom,spmi-pmic";
1078 reg = <0x0 0x1>;
1079 #address-cells = <0x1>;
1080 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001081 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001082
1083 spmi_gpios: gpios@c000 {
1084 compatible = "qcom,pm8916-gpio";
1085 reg = <0xc000 0x400>;
1086 gpio-controller;
1087 gpio-count = <4>;
1088 #gpio-cells = <2>;
1089 gpio-bank-name="spmi";
1090 };
1091 };
1092 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001093
1094 wdt0: wdt@0 {
1095 compatible = "sandbox,wdt";
1096 };
Rob Clarkf2006802018-01-10 11:33:30 +01001097
Mario Six957983e2018-08-09 14:51:19 +02001098 axi: axi@0 {
1099 compatible = "sandbox,axi";
1100 #address-cells = <0x1>;
1101 #size-cells = <0x1>;
1102 store@0 {
1103 compatible = "sandbox,sandbox_store";
1104 reg = <0x0 0x400>;
1105 };
1106 };
1107
Rob Clarkf2006802018-01-10 11:33:30 +01001108 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001109 #address-cells = <1>;
1110 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001111 setting = "sunrise ohoka";
1112 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001113 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001114 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001115 chosen-test {
1116 compatible = "denx,u-boot-fdt-test";
1117 reg = <9 1>;
1118 };
1119 };
Mario Sixe8d52912018-03-12 14:53:33 +01001120
1121 translation-test@8000 {
1122 compatible = "simple-bus";
1123 reg = <0x8000 0x4000>;
1124
1125 #address-cells = <0x2>;
1126 #size-cells = <0x1>;
1127
1128 ranges = <0 0x0 0x8000 0x1000
1129 1 0x100 0x9000 0x1000
1130 2 0x200 0xA000 0x1000
1131 3 0x300 0xB000 0x1000
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001132 4 0x400 0xC000 0x1000
Mario Sixe8d52912018-03-12 14:53:33 +01001133 >;
1134
Fabien Dessenne641067f2019-05-31 15:11:30 +02001135 dma-ranges = <0 0x000 0x10000000 0x1000
1136 1 0x100 0x20000000 0x1000
1137 >;
1138
Mario Sixe8d52912018-03-12 14:53:33 +01001139 dev@0,0 {
1140 compatible = "denx,u-boot-fdt-dummy";
1141 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001142 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001143 };
1144
1145 dev@1,100 {
1146 compatible = "denx,u-boot-fdt-dummy";
1147 reg = <1 0x100 0x1000>;
1148
1149 };
1150
1151 dev@2,200 {
1152 compatible = "denx,u-boot-fdt-dummy";
1153 reg = <2 0x200 0x1000>;
1154 };
1155
1156
1157 noxlatebus@3,300 {
1158 compatible = "simple-bus";
1159 reg = <3 0x300 0x1000>;
1160
1161 #address-cells = <0x1>;
1162 #size-cells = <0x0>;
1163
1164 dev@42 {
1165 compatible = "denx,u-boot-fdt-dummy";
1166 reg = <0x42>;
1167 };
1168 };
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001169
1170 xlatebus@4,400 {
1171 compatible = "sandbox,zero-size-cells-bus";
1172 reg = <4 0x400 0x1000>;
1173 #address-cells = <1>;
1174 #size-cells = <1>;
1175 ranges = <0 4 0x400 0x1000>;
1176
1177 devs {
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180
1181 dev@19 {
1182 compatible = "denx,u-boot-fdt-dummy";
1183 reg = <0x19>;
1184 };
1185 };
1186 };
1187
Mario Sixe8d52912018-03-12 14:53:33 +01001188 };
Mario Six4eea5312018-09-27 09:19:31 +02001189
1190 osd {
1191 compatible = "sandbox,sandbox_osd";
1192 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001193
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001194 sandbox_tee {
1195 compatible = "sandbox,tee";
1196 };
Bin Meng4f89d492018-10-15 02:21:26 -07001197
1198 sandbox_virtio1 {
1199 compatible = "sandbox,virtio1";
1200 };
1201
1202 sandbox_virtio2 {
1203 compatible = "sandbox,virtio2";
1204 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001205
Etienne Carriere87d4f272020-09-09 18:44:05 +02001206 sandbox_scmi {
1207 compatible = "sandbox,scmi-devices";
1208 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001209 resets = <&reset_scmi0 3>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001210 };
1211
Patrice Chotardf41a8242018-10-24 14:10:23 +02001212 pinctrl {
1213 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001214
Sean Anderson7f0f1802020-09-14 11:01:57 -04001215 pinctrl-names = "default", "alternate";
1216 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1217 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001218
Sean Anderson7f0f1802020-09-14 11:01:57 -04001219 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001220 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001221 pins = "P5";
1222 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001223 bias-pull-up;
1224 input-disable;
1225 };
1226 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001227 pins = "P6";
1228 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001229 output-high;
1230 drive-open-drain;
1231 };
1232 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001233 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001234 bias-pull-down;
1235 input-enable;
1236 };
1237 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001238 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001239 bias-disable;
1240 };
1241 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001242
1243 pinctrl_i2c: i2c {
1244 groups {
1245 groups = "I2C_UART";
1246 function = "I2C";
1247 };
1248
1249 pins {
1250 pins = "P0", "P1";
1251 drive-open-drain;
1252 };
1253 };
1254
1255 pinctrl_i2s: i2s {
1256 groups = "SPI_I2S";
1257 function = "I2S";
1258 };
1259
1260 pinctrl_spi: spi {
1261 groups = "SPI_I2S";
1262 function = "SPI";
1263
1264 cs {
1265 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1266 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1267 };
1268 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001269 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001270
1271 hwspinlock@0 {
1272 compatible = "sandbox,hwspinlock";
1273 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001274
1275 dma: dma {
1276 compatible = "sandbox,dma";
1277 #dma-cells = <1>;
1278
1279 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1280 dma-names = "m2m", "tx0", "rx0";
1281 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001282
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001283 /*
1284 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1285 * end of the test. If parent mdio is removed first, clean-up of the
1286 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1287 * active at the end of the test. That it turn doesn't allow the mdio
1288 * class to be destroyed, triggering an error.
1289 */
1290 mdio-mux-test {
1291 compatible = "sandbox,mdio-mux";
1292 #address-cells = <1>;
1293 #size-cells = <0>;
1294 mdio-parent-bus = <&mdio>;
1295
1296 mdio-ch-test@0 {
1297 reg = <0>;
1298 };
1299 mdio-ch-test@1 {
1300 reg = <1>;
1301 };
1302 };
1303
1304 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001305 compatible = "sandbox,mdio";
1306 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001307
1308 pm-bus-test {
1309 compatible = "simple-pm-bus";
1310 clocks = <&clk_sandbox 4>;
1311 power-domains = <&pwrdom 1>;
1312 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001313
1314 resetc2: syscon-reset {
1315 compatible = "syscon-reset";
1316 #reset-cells = <1>;
1317 regmap = <&syscon0>;
1318 offset = <1>;
1319 mask = <0x27FFFFFF>;
1320 assert-high = <0>;
1321 };
1322
1323 syscon-reset-test {
1324 compatible = "sandbox,misc_sandbox";
1325 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1326 reset-names = "valid", "no_mask", "out_of_range";
1327 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301328
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001329 sysinfo {
1330 compatible = "sandbox,sysinfo-sandbox";
1331 };
1332
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301333 some_regmapped-bus {
1334 #address-cells = <0x1>;
1335 #size-cells = <0x1>;
1336
1337 ranges = <0x0 0x0 0x10>;
1338 compatible = "simple-bus";
1339
1340 regmap-test_0 {
1341 reg = <0 0x10>;
1342 compatible = "sandbox,regmap_test";
1343 };
1344 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001345};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001346
1347#include "sandbox_pmic.dtsi"