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Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01008
Simon Glass2e7d35d2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070014
Simon Glass00606d72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060017 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070018 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060019 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060020 gpio1 = &gpio_a;
21 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010022 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070023 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060024 mmc0 = "/mmc0";
25 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070026 pci0 = &pci0;
27 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070028 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020029 remoteproc0 = &rproc_1;
30 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060031 rtc0 = &rtc_0;
32 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060033 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020034 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070035 testbus3 = "/some-bus";
36 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070037 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070038 testfdt3 = "/b-test";
39 testfdt5 = "/some-bus/c-test@5";
40 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070041 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020042 fdt-dummy0 = "/translation-test@8000/dev@0,0";
43 fdt-dummy1 = "/translation-test@8000/dev@1,100";
44 fdt-dummy2 = "/translation-test@8000/dev@2,200";
45 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchid64b9cd2020-12-30 00:16:21 +010046 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glasse00cb222015-03-25 12:23:05 -060047 usb0 = &usb_0;
48 usb1 = &usb_1;
49 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020050 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020051 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060052 };
53
Simon Glassce6d99a2018-12-10 10:37:33 -070054 audio: audio-codec {
55 compatible = "sandbox,audio-codec";
56 #sound-dai-cells = <1>;
57 };
58
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020059 buttons {
60 compatible = "gpio-keys";
61
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020062 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020063 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020064 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020065 };
66
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020067 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020068 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020069 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020070 };
71 };
72
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010073 buttons2 {
74 compatible = "adc-keys";
75 io-channels = <&adc 3>;
76 keyup-threshold-microvolt = <3000000>;
77
78 button-up {
79 label = "button3";
80 linux,code = <KEY_F3>;
81 press-threshold-microvolt = <1500000>;
82 };
83
84 button-down {
85 label = "button4";
86 linux,code = <KEY_F4>;
87 press-threshold-microvolt = <1000000>;
88 };
89
90 button-enter {
91 label = "button5";
92 linux,code = <KEY_F5>;
93 press-threshold-microvolt = <500000>;
94 };
95 };
96
Simon Glasse96fa6c2018-12-10 10:37:34 -070097 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060098 reg = <0 0>;
99 compatible = "google,cros-ec-sandbox";
100
101 /*
102 * This describes the flash memory within the EC. Note
103 * that the STM32L flash erases to 0, not 0xff.
104 */
105 flash {
106 image-pos = <0x08000000>;
107 size = <0x20000>;
108 erase-value = <0>;
109
110 /* Information for sandbox */
111 ro {
112 image-pos = <0>;
113 size = <0xf000>;
114 };
115 wp-ro {
116 image-pos = <0xf000>;
117 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700118 used = <0x884>;
119 compress = "lz4";
120 uncomp-size = <0xcf8>;
121 hash {
122 algo = "sha256";
123 value = [00 01 02 03 04 05 06 07
124 08 09 0a 0b 0c 0d 0e 0f
125 10 11 12 13 14 15 16 17
126 18 19 1a 1b 1c 1d 1e 1f];
127 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600128 };
129 rw {
130 image-pos = <0x10000>;
131 size = <0x10000>;
132 };
133 };
134 };
135
Yannick Fertré23f965a2019-10-07 15:29:05 +0200136 dsi_host: dsi_host {
137 compatible = "sandbox,dsi-host";
138 };
139
Simon Glass2e7d35d2014-02-26 15:59:21 -0700140 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600141 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700142 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600143 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700144 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600145 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100146 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
147 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700148 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100149 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
150 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
151 <&gpio_b 7 GPIO_IN 3 2 1>,
152 <&gpio_b 8 GPIO_OUT 3 2 1>,
153 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100154 test3-gpios =
155 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
156 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
157 <&gpio_c 2 GPIO_OUT>,
158 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
159 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200160 <&gpio_c 5 GPIO_IN>,
161 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
162 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530163 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
164 test5-gpios = <&gpio_a 19>;
165
Simon Glassa1b17e42018-12-10 10:37:37 -0700166 int-value = <1234>;
167 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200168 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200169 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600170 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700171 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600172 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200173 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530174
175 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
176 <&muxcontroller0 2>, <&muxcontroller0 3>,
177 <&muxcontroller1>;
178 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
179 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100180 display-timings {
181 timing0: 240x320 {
182 clock-frequency = <6500000>;
183 hactive = <240>;
184 vactive = <320>;
185 hfront-porch = <6>;
186 hback-porch = <7>;
187 hsync-len = <1>;
188 vback-porch = <5>;
189 vfront-porch = <8>;
190 vsync-len = <2>;
191 hsync-active = <1>;
192 vsync-active = <0>;
193 de-active = <1>;
194 pixelclk-active = <1>;
195 interlaced;
196 doublescan;
197 doubleclk;
198 };
199 timing1: 480x800 {
200 clock-frequency = <9000000>;
201 hactive = <480>;
202 vactive = <800>;
203 hfront-porch = <10>;
204 hback-porch = <59>;
205 hsync-len = <12>;
206 vback-porch = <15>;
207 vfront-porch = <17>;
208 vsync-len = <16>;
209 hsync-active = <0>;
210 vsync-active = <1>;
211 de-active = <0>;
212 pixelclk-active = <0>;
213 };
214 timing2: 800x480 {
215 clock-frequency = <33500000>;
216 hactive = <800>;
217 vactive = <480>;
218 hback-porch = <89>;
219 hfront-porch = <164>;
220 vback-porch = <23>;
221 vfront-porch = <10>;
222 hsync-len = <11>;
223 vsync-len = <13>;
224 };
225 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700226 };
227
228 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600229 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700230 compatible = "not,compatible";
231 };
232
233 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600234 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700235 };
236
Simon Glass5d9a88f2018-10-01 12:22:40 -0600237 backlight: backlight {
238 compatible = "pwm-backlight";
239 enable-gpios = <&gpio_a 1>;
240 power-supply = <&ldo_1>;
241 pwms = <&pwm 0 1000>;
242 default-brightness-level = <5>;
243 brightness-levels = <0 16 32 64 128 170 202 234 255>;
244 };
245
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200246 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200247 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200248 bind-test-child1 {
249 compatible = "sandbox,phy";
250 #phy-cells = <1>;
251 };
252
253 bind-test-child2 {
254 compatible = "simple-bus";
255 };
256 };
257
Simon Glass2e7d35d2014-02-26 15:59:21 -0700258 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600259 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700260 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600261 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700262 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530263
264 mux-controls = <&muxcontroller0 0>;
265 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700266 };
267
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200268 phy_provider0: gen_phy@0 {
269 compatible = "sandbox,phy";
270 #phy-cells = <1>;
271 };
272
273 phy_provider1: gen_phy@1 {
274 compatible = "sandbox,phy";
275 #phy-cells = <0>;
276 broken;
277 };
278
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200279 phy_provider2: gen_phy@2 {
280 compatible = "sandbox,phy";
281 #phy-cells = <0>;
282 };
283
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200284 gen_phy_user: gen_phy_user {
285 compatible = "simple-bus";
286 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
287 phy-names = "phy1", "phy2", "phy3";
288 };
289
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200290 gen_phy_user1: gen_phy_user1 {
291 compatible = "simple-bus";
292 phys = <&phy_provider0 0>, <&phy_provider2>;
293 phy-names = "phy1", "phy2";
294 };
295
Simon Glass2e7d35d2014-02-26 15:59:21 -0700296 some-bus {
297 #address-cells = <1>;
298 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600299 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600300 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600301 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700302 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600303 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700304 compatible = "denx,u-boot-fdt-test";
305 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600306 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700307 ping-add = <5>;
308 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600309 c-test@0 {
310 compatible = "denx,u-boot-fdt-test";
311 reg = <0>;
312 ping-expect = <6>;
313 ping-add = <6>;
314 };
315 c-test@1 {
316 compatible = "denx,u-boot-fdt-test";
317 reg = <1>;
318 ping-expect = <7>;
319 ping-add = <7>;
320 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700321 };
322
323 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600324 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600325 ping-expect = <6>;
326 ping-add = <6>;
327 compatible = "google,another-fdt-test";
328 };
329
330 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600331 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600332 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700333 ping-add = <6>;
334 compatible = "google,another-fdt-test";
335 };
336
Simon Glass9cc36a22015-01-25 08:27:05 -0700337 f-test {
338 compatible = "denx,u-boot-fdt-test";
339 };
340
341 g-test {
342 compatible = "denx,u-boot-fdt-test";
343 };
344
Bin Meng2786cd72018-10-10 22:07:01 -0700345 h-test {
346 compatible = "denx,u-boot-fdt-test1";
347 };
348
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200349 i-test {
350 compatible = "mediatek,u-boot-fdt-test";
351 #address-cells = <1>;
352 #size-cells = <0>;
353
354 subnode@0 {
355 reg = <0>;
356 };
357
358 subnode@1 {
359 reg = <1>;
360 };
361
362 subnode@2 {
363 reg = <2>;
364 };
365 };
366
Simon Glassdc12ebb2019-12-29 21:19:25 -0700367 devres-test {
368 compatible = "denx,u-boot-devres-test";
369 };
370
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530371 another-test {
372 reg = <0 2>;
373 compatible = "denx,u-boot-fdt-test";
374 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
375 test5-gpios = <&gpio_a 19>;
376 };
377
Simon Glass0f7b1112020-07-07 13:12:06 -0600378 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600379 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600380 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600381 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600382 child {
383 compatible = "denx,u-boot-acpi-test";
384 };
Simon Glassf50cc952020-04-08 16:57:34 -0600385 };
386
Simon Glass0f7b1112020-07-07 13:12:06 -0600387 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600388 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600389 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600390 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600391 };
392
Patrice Chotardee87a092017-09-04 14:55:57 +0200393 clocks {
394 clk_fixed: clk-fixed {
395 compatible = "fixed-clock";
396 #clock-cells = <0>;
397 clock-frequency = <1234>;
398 };
Anup Patelb630d572019-02-25 08:14:55 +0000399
400 clk_fixed_factor: clk-fixed-factor {
401 compatible = "fixed-factor-clock";
402 #clock-cells = <0>;
403 clock-div = <3>;
404 clock-mult = <2>;
405 clocks = <&clk_fixed>;
406 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200407
408 osc {
409 compatible = "fixed-clock";
410 #clock-cells = <0>;
411 clock-frequency = <20000000>;
412 };
Stephen Warren135aa952016-06-17 09:44:00 -0600413 };
414
415 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600416 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600417 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200418 assigned-clocks = <&clk_sandbox 3>;
419 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600420 };
421
422 clk-test {
423 compatible = "sandbox,clk-test";
424 clocks = <&clk_fixed>,
425 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200426 <&clk_sandbox 0>,
427 <&clk_sandbox 3>,
428 <&clk_sandbox 2>;
429 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600430 };
431
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200432 ccf: clk-ccf {
433 compatible = "sandbox,clk-ccf";
434 };
435
Simon Glass171e9912015-05-22 15:42:15 -0600436 eth@10002000 {
437 compatible = "sandbox,eth";
438 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500439 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600440 };
441
442 eth_5: eth@10003000 {
443 compatible = "sandbox,eth";
444 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500445 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600446 };
447
Bin Meng71d79712015-08-27 22:25:53 -0700448 eth_3: sbe5 {
449 compatible = "sandbox,eth";
450 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500451 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700452 };
453
Simon Glass171e9912015-05-22 15:42:15 -0600454 eth@10004000 {
455 compatible = "sandbox,eth";
456 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500457 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600458 };
459
Rajan Vaja31b82172018-09-19 03:43:46 -0700460 firmware {
461 sandbox_firmware: sandbox-firmware {
462 compatible = "sandbox,firmware";
463 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200464
465 sandbox-scmi-agent@0 {
466 compatible = "sandbox,scmi-agent";
467 #address-cells = <1>;
468 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200469
470 clk_scmi0: protocol@14 {
471 reg = <0x14>;
472 #clock-cells = <1>;
473 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200474
475 reset_scmi0: protocol@16 {
476 reg = <0x16>;
477 #reset-cells = <1>;
478 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200479 };
480
481 sandbox-scmi-agent@1 {
482 compatible = "sandbox,scmi-agent";
483 #address-cells = <1>;
484 #size-cells = <0>;
485
Etienne Carriere87d4f272020-09-09 18:44:05 +0200486 clk_scmi1: protocol@14 {
487 reg = <0x14>;
488 #clock-cells = <1>;
489 };
490
Etienne Carriere358599e2020-09-09 18:44:00 +0200491 protocol@10 {
492 reg = <0x10>;
493 };
494 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700495 };
496
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100497 pinctrl-gpio {
498 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700499
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100500 gpio_a: base-gpios {
501 compatible = "sandbox,gpio";
502 gpio-controller;
503 #gpio-cells = <1>;
504 gpio-bank-name = "a";
505 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200506 hog_input_active_low {
507 gpio-hog;
508 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200509 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200510 };
511 hog_input_active_high {
512 gpio-hog;
513 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200514 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200515 };
516 hog_output_low {
517 gpio-hog;
518 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200519 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200520 };
521 hog_output_high {
522 gpio-hog;
523 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200524 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200525 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100526 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600527
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100528 gpio_b: extra-gpios {
529 compatible = "sandbox,gpio";
530 gpio-controller;
531 #gpio-cells = <5>;
532 gpio-bank-name = "b";
533 sandbox,gpio-count = <10>;
534 };
535
536 gpio_c: pinmux-gpios {
537 compatible = "sandbox,gpio";
538 gpio-controller;
539 #gpio-cells = <2>;
540 gpio-bank-name = "c";
541 sandbox,gpio-count = <10>;
542 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100543 };
544
Simon Glassecc2ed52014-12-10 08:55:55 -0700545 i2c@0 {
546 #address-cells = <1>;
547 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600548 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700549 compatible = "sandbox,i2c";
550 clock-frequency = <100000>;
551 eeprom@2c {
552 reg = <0x2c>;
553 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700554 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200555 partitions {
556 compatible = "fixed-partitions";
557 #address-cells = <1>;
558 #size-cells = <1>;
559 bootcount_i2c: bootcount@10 {
560 reg = <10 2>;
561 };
562 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700563 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200564
Simon Glass52d3bc52015-05-22 15:42:17 -0600565 rtc_0: rtc@43 {
566 reg = <0x43>;
567 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700568 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600569 };
570
571 rtc_1: rtc@61 {
572 reg = <0x61>;
573 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700574 sandbox,emul = <&emul1>;
575 };
576
577 i2c_emul: emul {
578 reg = <0xff>;
579 compatible = "sandbox,i2c-emul-parent";
580 emul_eeprom: emul-eeprom {
581 compatible = "sandbox,i2c-eeprom";
582 sandbox,filename = "i2c.bin";
583 sandbox,size = <256>;
584 };
585 emul0: emul0 {
586 compatible = "sandbox,i2c-rtc";
587 };
588 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600589 compatible = "sandbox,i2c-rtc";
590 };
591 };
592
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200593 sandbox_pmic: sandbox_pmic {
594 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700595 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200596 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200597
598 mc34708: pmic@41 {
599 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700600 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200601 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700602 };
603
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100604 bootcount@0 {
605 compatible = "u-boot,bootcount-rtc";
606 rtc = <&rtc_1>;
607 offset = <0x13>;
608 };
609
Michal Simekf692b472020-05-28 11:48:55 +0200610 bootcount {
611 compatible = "u-boot,bootcount-i2c-eeprom";
612 i2c-eeprom = <&bootcount_i2c>;
613 };
614
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100615 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100616 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100617 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100618 vdd-supply = <&buck2>;
619 vss-microvolts = <0>;
620 };
621
Simon Glass02554352020-02-06 09:55:00 -0700622 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700623 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700624 interrupt-controller;
625 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700626 };
627
Simon Glass3c97c4f2016-01-18 19:52:26 -0700628 lcd {
629 u-boot,dm-pre-reloc;
630 compatible = "sandbox,lcd-sdl";
631 xres = <1366>;
632 yres = <768>;
633 };
634
Simon Glass3c43fba2015-07-06 12:54:34 -0600635 leds {
636 compatible = "gpio-leds";
637
638 iracibble {
639 gpios = <&gpio_a 1 0>;
640 label = "sandbox:red";
641 };
642
643 martinet {
644 gpios = <&gpio_a 2 0>;
645 label = "sandbox:green";
646 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200647
648 default_on {
649 gpios = <&gpio_a 5 0>;
650 label = "sandbox:default_on";
651 default-state = "on";
652 };
653
654 default_off {
655 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400656 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200657 default-state = "off";
658 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600659 };
660
Stephen Warren8961b522016-05-16 17:41:37 -0600661 mbox: mbox {
662 compatible = "sandbox,mbox";
663 #mbox-cells = <1>;
664 };
665
666 mbox-test {
667 compatible = "sandbox,mbox-test";
668 mboxes = <&mbox 100>, <&mbox 1>;
669 mbox-names = "other", "test";
670 };
671
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900672 cpus {
Sean Anderson7616e362020-09-28 10:52:23 -0400673 timebase-frequency = <2000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900674 cpu-test1 {
Sean Anderson7616e362020-09-28 10:52:23 -0400675 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900676 compatible = "sandbox,cpu_sandbox";
677 u-boot,dm-pre-reloc;
678 };
Mario Sixfa44b532018-08-06 10:23:44 +0200679
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900680 cpu-test2 {
681 compatible = "sandbox,cpu_sandbox";
682 u-boot,dm-pre-reloc;
683 };
Mario Sixfa44b532018-08-06 10:23:44 +0200684
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900685 cpu-test3 {
686 compatible = "sandbox,cpu_sandbox";
687 u-boot,dm-pre-reloc;
688 };
Mario Sixfa44b532018-08-06 10:23:44 +0200689 };
690
Dave Gerlach21e3c212020-07-15 23:39:58 -0500691 chipid: chipid {
692 compatible = "sandbox,soc";
693 };
694
Simon Glasse96fa6c2018-12-10 10:37:34 -0700695 i2s: i2s {
696 compatible = "sandbox,i2s";
697 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700698 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700699 };
700
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200701 nop-test_0 {
702 compatible = "sandbox,nop_sandbox1";
703 nop-test_1 {
704 compatible = "sandbox,nop_sandbox2";
705 bind = "True";
706 };
707 nop-test_2 {
708 compatible = "sandbox,nop_sandbox2";
709 bind = "False";
710 };
711 };
712
Mario Six004e67c2018-07-31 14:24:14 +0200713 misc-test {
714 compatible = "sandbox,misc_sandbox";
715 };
716
Simon Glasse48eeb92017-04-23 20:02:07 -0600717 mmc2 {
718 compatible = "sandbox,mmc";
719 };
720
721 mmc1 {
722 compatible = "sandbox,mmc";
723 };
724
725 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600726 compatible = "sandbox,mmc";
727 };
728
Simon Glassb45c8332019-02-16 20:24:50 -0700729 pch {
730 compatible = "sandbox,pch";
731 };
732
Tom Rini42c64d12020-02-11 12:41:23 -0500733 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700734 compatible = "sandbox,pci";
735 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500736 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700737 #address-cells = <3>;
738 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600739 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700740 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700741 pci@0,0 {
742 compatible = "pci-generic";
743 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600744 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700745 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300746 pci@1,0 {
747 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600748 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
749 reg = <0x02000814 0 0 0 0
750 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600751 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300752 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700753 p2sb-pci@2,0 {
754 compatible = "sandbox,p2sb";
755 reg = <0x02001010 0 0 0 0>;
756 sandbox,emul = <&p2sb_emul>;
757
758 adder {
759 intel,p2sb-port-id = <3>;
760 compatible = "sandbox,adder";
761 };
762 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700763 pci@1e,0 {
764 compatible = "sandbox,pmc";
765 reg = <0xf000 0 0 0 0>;
766 sandbox,emul = <&pmc_emul1e>;
767 acpi-base = <0x400>;
768 gpe0-dwx-mask = <0xf>;
769 gpe0-dwx-shift-base = <4>;
770 gpe0-dw = <6 7 9>;
771 gpe0-sts = <0x20>;
772 gpe0-en = <0x30>;
773 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700774 pci@1f,0 {
775 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600776 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
777 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600778 sandbox,emul = <&swap_case_emul0_1f>;
779 };
780 };
781
782 pci-emul0 {
783 compatible = "sandbox,pci-emul-parent";
784 swap_case_emul0_0: emul0@0,0 {
785 compatible = "sandbox,swap-case";
786 };
787 swap_case_emul0_1: emul0@1,0 {
788 compatible = "sandbox,swap-case";
789 use-ea;
790 };
791 swap_case_emul0_1f: emul0@1f,0 {
792 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700793 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700794 p2sb_emul: emul@2,0 {
795 compatible = "sandbox,p2sb-emul";
796 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700797 pmc_emul1e: emul@1e,0 {
798 compatible = "sandbox,pmc-emul";
799 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700800 };
801
Tom Rini42c64d12020-02-11 12:41:23 -0500802 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700803 compatible = "sandbox,pci";
804 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500805 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700806 #address-cells = <3>;
807 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700808 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
809 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
810 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700811 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200812 0x0c 0x00 0x1234 0x5678
813 0x10 0x00 0x1234 0x5678>;
814 pci@10,0 {
815 reg = <0x8000 0 0 0 0>;
816 };
Bin Mengdee4d752018-08-03 01:14:41 -0700817 };
818
Tom Rini42c64d12020-02-11 12:41:23 -0500819 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700820 compatible = "sandbox,pci";
821 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500822 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700823 #address-cells = <3>;
824 #size-cells = <2>;
825 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
826 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
827 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
828 pci@1f,0 {
829 compatible = "pci-generic";
830 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600831 sandbox,emul = <&swap_case_emul2_1f>;
832 };
833 };
834
835 pci-emul2 {
836 compatible = "sandbox,pci-emul-parent";
837 swap_case_emul2_1f: emul2@1f,0 {
838 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700839 };
840 };
841
Ramon Friedbb413332019-04-27 11:15:23 +0300842 pci_ep: pci_ep {
843 compatible = "sandbox,pci_ep";
844 };
845
Simon Glass98561572017-04-23 20:10:44 -0600846 probing {
847 compatible = "simple-bus";
848 test1 {
849 compatible = "denx,u-boot-probe-test";
850 };
851
852 test2 {
853 compatible = "denx,u-boot-probe-test";
854 };
855
856 test3 {
857 compatible = "denx,u-boot-probe-test";
858 };
859
860 test4 {
861 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100862 first-syscon = <&syscon0>;
863 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100864 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600865 };
866 };
867
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600868 pwrdom: power-domain {
869 compatible = "sandbox,power-domain";
870 #power-domain-cells = <1>;
871 };
872
873 power-domain-test {
874 compatible = "sandbox,power-domain-test";
875 power-domains = <&pwrdom 2>;
876 };
877
Simon Glass5d9a88f2018-10-01 12:22:40 -0600878 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600879 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600880 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600881 };
882
883 pwm2 {
884 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600885 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600886 };
887
Simon Glass64ce0ca2015-07-06 12:54:31 -0600888 ram {
889 compatible = "sandbox,ram";
890 };
891
Simon Glass5010d982015-07-06 12:54:29 -0600892 reset@0 {
893 compatible = "sandbox,warm-reset";
894 };
895
896 reset@1 {
897 compatible = "sandbox,reset";
898 };
899
Stephen Warren4581b712016-06-17 09:43:59 -0600900 resetc: reset-ctl {
901 compatible = "sandbox,reset-ctl";
902 #reset-cells = <1>;
903 };
904
905 reset-ctl-test {
906 compatible = "sandbox,reset-ctl-test";
907 resets = <&resetc 100>, <&resetc 2>;
908 reset-names = "other", "test";
909 };
910
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530911 rng {
912 compatible = "sandbox,sandbox-rng";
913 };
914
Nishanth Menon52159402015-09-17 15:42:41 -0500915 rproc_1: rproc@1 {
916 compatible = "sandbox,test-processor";
917 remoteproc-name = "remoteproc-test-dev1";
918 };
919
920 rproc_2: rproc@2 {
921 compatible = "sandbox,test-processor";
922 internal-memory-mapped;
923 remoteproc-name = "remoteproc-test-dev2";
924 };
925
Simon Glass5d9a88f2018-10-01 12:22:40 -0600926 panel {
927 compatible = "simple-panel";
928 backlight = <&backlight 0 100>;
929 };
930
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300931 smem@0 {
932 compatible = "sandbox,smem";
933 };
934
Simon Glassd4901892018-12-10 10:37:36 -0700935 sound {
936 compatible = "sandbox,sound";
937 cpu {
938 sound-dai = <&i2s 0>;
939 };
940
941 codec {
942 sound-dai = <&audio 0>;
943 };
944 };
945
Simon Glass0ae0cb72014-10-13 23:42:11 -0600946 spi@0 {
947 #address-cells = <1>;
948 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600949 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600950 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +0200951 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600952 spi.bin@0 {
953 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000954 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600955 spi-max-frequency = <40000000>;
956 sandbox,filename = "spi.bin";
957 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +0200958 spi.bin@1 {
959 reg = <1>;
960 compatible = "spansion,m25p16", "jedec,spi-nor";
961 spi-max-frequency = <50000000>;
962 sandbox,filename = "spi.bin";
963 spi-cpol;
964 spi-cpha;
965 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600966 };
967
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100968 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600969 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200970 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600971 };
972
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100973 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600974 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600975 reg = <0x20 5
976 0x28 6
977 0x30 7
978 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600979 };
980
Patrick Delaunaya442e612019-03-07 09:57:13 +0100981 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900982 compatible = "simple-mfd", "syscon";
983 reg = <0x40 5
984 0x48 6
985 0x50 7
986 0x58 8>;
987 };
988
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530989 syscon3: syscon@3 {
990 compatible = "simple-mfd", "syscon";
991 reg = <0x000100 0x10>;
992
993 muxcontroller0: a-mux-controller {
994 compatible = "mmio-mux";
995 #mux-control-cells = <1>;
996
997 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
998 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
999 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1000 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1001 u-boot,mux-autoprobe;
1002 };
1003 };
1004
1005 muxcontroller1: emul-mux-controller {
1006 compatible = "mux-emul";
1007 #mux-control-cells = <0>;
1008 u-boot,mux-autoprobe;
1009 idle-state = <0xabcd>;
1010 };
1011
Simon Glass93f44e82020-12-16 21:20:27 -07001012 testfdtm0 {
1013 compatible = "denx,u-boot-fdtm-test";
1014 };
1015
1016 testfdtm1: testfdtm1 {
1017 compatible = "denx,u-boot-fdtm-test";
1018 };
1019
1020 testfdtm2 {
1021 compatible = "denx,u-boot-fdtm-test";
1022 };
1023
Sean Anderson7616e362020-09-28 10:52:23 -04001024 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001025 compatible = "sandbox,timer";
1026 clock-frequency = <1000000>;
1027 };
1028
Sean Anderson7616e362020-09-28 10:52:23 -04001029 timer@1 {
1030 compatible = "sandbox,timer";
1031 sandbox,timebase-frequency-fallback;
1032 };
1033
Miquel Raynalb91ad162018-05-15 11:57:27 +02001034 tpm2 {
1035 compatible = "sandbox,tpm2";
1036 };
1037
Simon Glass171e9912015-05-22 15:42:15 -06001038 uart0: serial {
1039 compatible = "sandbox,serial";
1040 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001041 };
1042
Simon Glasse00cb222015-03-25 12:23:05 -06001043 usb_0: usb@0 {
1044 compatible = "sandbox,usb";
1045 status = "disabled";
1046 hub {
1047 compatible = "sandbox,usb-hub";
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 flash-stick {
1051 reg = <0>;
1052 compatible = "sandbox,usb-flash";
1053 };
1054 };
1055 };
1056
1057 usb_1: usb@1 {
1058 compatible = "sandbox,usb";
1059 hub {
1060 compatible = "usb-hub";
1061 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001062 #address-cells = <1>;
1063 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001064 hub-emul {
1065 compatible = "sandbox,usb-hub";
1066 #address-cells = <1>;
1067 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001068 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001069 reg = <0>;
1070 compatible = "sandbox,usb-flash";
1071 sandbox,filepath = "testflash.bin";
1072 };
1073
Simon Glass431cbd62015-11-08 23:48:01 -07001074 flash-stick@1 {
1075 reg = <1>;
1076 compatible = "sandbox,usb-flash";
1077 sandbox,filepath = "testflash1.bin";
1078 };
1079
1080 flash-stick@2 {
1081 reg = <2>;
1082 compatible = "sandbox,usb-flash";
1083 sandbox,filepath = "testflash2.bin";
1084 };
1085
Simon Glassbff1a712015-11-08 23:48:08 -07001086 keyb@3 {
1087 reg = <3>;
1088 compatible = "sandbox,usb-keyb";
1089 };
1090
Simon Glasse00cb222015-03-25 12:23:05 -06001091 };
Michael Wallec03b7612020-06-02 01:47:07 +02001092
1093 usbstor@1 {
1094 reg = <1>;
1095 };
1096 usbstor@3 {
1097 reg = <3>;
1098 };
Simon Glasse00cb222015-03-25 12:23:05 -06001099 };
1100 };
1101
1102 usb_2: usb@2 {
1103 compatible = "sandbox,usb";
1104 status = "disabled";
1105 };
1106
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001107 spmi: spmi@0 {
1108 compatible = "sandbox,spmi";
1109 #address-cells = <0x1>;
1110 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001111 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001112 pm8916@0 {
1113 compatible = "qcom,spmi-pmic";
1114 reg = <0x0 0x1>;
1115 #address-cells = <0x1>;
1116 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001117 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001118
1119 spmi_gpios: gpios@c000 {
1120 compatible = "qcom,pm8916-gpio";
1121 reg = <0xc000 0x400>;
1122 gpio-controller;
1123 gpio-count = <4>;
1124 #gpio-cells = <2>;
1125 gpio-bank-name="spmi";
1126 };
1127 };
1128 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001129
1130 wdt0: wdt@0 {
1131 compatible = "sandbox,wdt";
1132 };
Rob Clarkf2006802018-01-10 11:33:30 +01001133
Mario Six957983e2018-08-09 14:51:19 +02001134 axi: axi@0 {
1135 compatible = "sandbox,axi";
1136 #address-cells = <0x1>;
1137 #size-cells = <0x1>;
1138 store@0 {
1139 compatible = "sandbox,sandbox_store";
1140 reg = <0x0 0x400>;
1141 };
1142 };
1143
Rob Clarkf2006802018-01-10 11:33:30 +01001144 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001145 #address-cells = <1>;
1146 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001147 setting = "sunrise ohoka";
1148 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001149 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001150 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001151 chosen-test {
1152 compatible = "denx,u-boot-fdt-test";
1153 reg = <9 1>;
1154 };
1155 };
Mario Sixe8d52912018-03-12 14:53:33 +01001156
1157 translation-test@8000 {
1158 compatible = "simple-bus";
1159 reg = <0x8000 0x4000>;
1160
1161 #address-cells = <0x2>;
1162 #size-cells = <0x1>;
1163
1164 ranges = <0 0x0 0x8000 0x1000
1165 1 0x100 0x9000 0x1000
1166 2 0x200 0xA000 0x1000
1167 3 0x300 0xB000 0x1000
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001168 4 0x400 0xC000 0x1000
Mario Sixe8d52912018-03-12 14:53:33 +01001169 >;
1170
Fabien Dessenne641067f2019-05-31 15:11:30 +02001171 dma-ranges = <0 0x000 0x10000000 0x1000
1172 1 0x100 0x20000000 0x1000
1173 >;
1174
Mario Sixe8d52912018-03-12 14:53:33 +01001175 dev@0,0 {
1176 compatible = "denx,u-boot-fdt-dummy";
1177 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001178 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001179 };
1180
1181 dev@1,100 {
1182 compatible = "denx,u-boot-fdt-dummy";
1183 reg = <1 0x100 0x1000>;
1184
1185 };
1186
1187 dev@2,200 {
1188 compatible = "denx,u-boot-fdt-dummy";
1189 reg = <2 0x200 0x1000>;
1190 };
1191
1192
1193 noxlatebus@3,300 {
1194 compatible = "simple-bus";
1195 reg = <3 0x300 0x1000>;
1196
1197 #address-cells = <0x1>;
1198 #size-cells = <0x0>;
1199
1200 dev@42 {
1201 compatible = "denx,u-boot-fdt-dummy";
1202 reg = <0x42>;
1203 };
1204 };
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001205
1206 xlatebus@4,400 {
1207 compatible = "sandbox,zero-size-cells-bus";
1208 reg = <4 0x400 0x1000>;
1209 #address-cells = <1>;
1210 #size-cells = <1>;
1211 ranges = <0 4 0x400 0x1000>;
1212
1213 devs {
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216
1217 dev@19 {
1218 compatible = "denx,u-boot-fdt-dummy";
1219 reg = <0x19>;
1220 };
1221 };
1222 };
1223
Mario Sixe8d52912018-03-12 14:53:33 +01001224 };
Mario Six4eea5312018-09-27 09:19:31 +02001225
1226 osd {
1227 compatible = "sandbox,sandbox_osd";
1228 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001229
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001230 sandbox_tee {
1231 compatible = "sandbox,tee";
1232 };
Bin Meng4f89d492018-10-15 02:21:26 -07001233
1234 sandbox_virtio1 {
1235 compatible = "sandbox,virtio1";
1236 };
1237
1238 sandbox_virtio2 {
1239 compatible = "sandbox,virtio2";
1240 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001241
Etienne Carriere87d4f272020-09-09 18:44:05 +02001242 sandbox_scmi {
1243 compatible = "sandbox,scmi-devices";
1244 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001245 resets = <&reset_scmi0 3>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001246 };
1247
Patrice Chotardf41a8242018-10-24 14:10:23 +02001248 pinctrl {
1249 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001250
Sean Anderson7f0f1802020-09-14 11:01:57 -04001251 pinctrl-names = "default", "alternate";
1252 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1253 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001254
Sean Anderson7f0f1802020-09-14 11:01:57 -04001255 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001256 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001257 pins = "P5";
1258 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001259 bias-pull-up;
1260 input-disable;
1261 };
1262 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001263 pins = "P6";
1264 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001265 output-high;
1266 drive-open-drain;
1267 };
1268 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001269 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001270 bias-pull-down;
1271 input-enable;
1272 };
1273 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001274 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001275 bias-disable;
1276 };
1277 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001278
1279 pinctrl_i2c: i2c {
1280 groups {
1281 groups = "I2C_UART";
1282 function = "I2C";
1283 };
1284
1285 pins {
1286 pins = "P0", "P1";
1287 drive-open-drain;
1288 };
1289 };
1290
1291 pinctrl_i2s: i2s {
1292 groups = "SPI_I2S";
1293 function = "I2S";
1294 };
1295
1296 pinctrl_spi: spi {
1297 groups = "SPI_I2S";
1298 function = "SPI";
1299
1300 cs {
1301 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1302 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1303 };
1304 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001305 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001306
1307 hwspinlock@0 {
1308 compatible = "sandbox,hwspinlock";
1309 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001310
1311 dma: dma {
1312 compatible = "sandbox,dma";
1313 #dma-cells = <1>;
1314
1315 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1316 dma-names = "m2m", "tx0", "rx0";
1317 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001318
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001319 /*
1320 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1321 * end of the test. If parent mdio is removed first, clean-up of the
1322 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1323 * active at the end of the test. That it turn doesn't allow the mdio
1324 * class to be destroyed, triggering an error.
1325 */
1326 mdio-mux-test {
1327 compatible = "sandbox,mdio-mux";
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1330 mdio-parent-bus = <&mdio>;
1331
1332 mdio-ch-test@0 {
1333 reg = <0>;
1334 };
1335 mdio-ch-test@1 {
1336 reg = <1>;
1337 };
1338 };
1339
1340 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001341 compatible = "sandbox,mdio";
1342 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001343
1344 pm-bus-test {
1345 compatible = "simple-pm-bus";
1346 clocks = <&clk_sandbox 4>;
1347 power-domains = <&pwrdom 1>;
1348 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001349
1350 resetc2: syscon-reset {
1351 compatible = "syscon-reset";
1352 #reset-cells = <1>;
1353 regmap = <&syscon0>;
1354 offset = <1>;
1355 mask = <0x27FFFFFF>;
1356 assert-high = <0>;
1357 };
1358
1359 syscon-reset-test {
1360 compatible = "sandbox,misc_sandbox";
1361 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1362 reset-names = "valid", "no_mask", "out_of_range";
1363 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301364
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001365 sysinfo {
1366 compatible = "sandbox,sysinfo-sandbox";
1367 };
1368
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301369 some_regmapped-bus {
1370 #address-cells = <0x1>;
1371 #size-cells = <0x1>;
1372
1373 ranges = <0x0 0x0 0x10>;
1374 compatible = "simple-bus";
1375
1376 regmap-test_0 {
1377 reg = <0 0x10>;
1378 compatible = "sandbox,regmap_test";
1379 };
1380 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001381};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001382
1383#include "sandbox_pmic.dtsi"