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Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05306#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01007
Simon Glass2e7d35d2014-02-26 15:59:21 -07008/ {
9 model = "sandbox";
10 compatible = "sandbox";
11 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060012 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070013
Simon Glass00606d72014-07-23 06:55:03 -060014 aliases {
15 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060016 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070017 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060018 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060019 gpio1 = &gpio_a;
20 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010021 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070022 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060023 mmc0 = "/mmc0";
24 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070025 pci0 = &pci0;
26 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070027 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020028 remoteproc0 = &rproc_1;
29 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060030 rtc0 = &rtc_0;
31 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060032 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020033 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070034 testbus3 = "/some-bus";
35 testfdt0 = "/some-bus/c-test@0";
36 testfdt1 = "/some-bus/c-test@1";
37 testfdt3 = "/b-test";
38 testfdt5 = "/some-bus/c-test@5";
39 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +020040 fdt-dummy0 = "/translation-test@8000/dev@0,0";
41 fdt-dummy1 = "/translation-test@8000/dev@1,100";
42 fdt-dummy2 = "/translation-test@8000/dev@2,200";
43 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060044 usb0 = &usb_0;
45 usb1 = &usb_1;
46 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020047 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020048 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060049 };
50
Simon Glassce6d99a2018-12-10 10:37:33 -070051 audio: audio-codec {
52 compatible = "sandbox,audio-codec";
53 #sound-dai-cells = <1>;
54 };
55
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020056 buttons {
57 compatible = "gpio-keys";
58
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020059 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020060 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020061 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020062 };
63
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020064 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020065 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020066 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020067 };
68 };
69
Simon Glasse96fa6c2018-12-10 10:37:34 -070070 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060071 reg = <0 0>;
72 compatible = "google,cros-ec-sandbox";
73
74 /*
75 * This describes the flash memory within the EC. Note
76 * that the STM32L flash erases to 0, not 0xff.
77 */
78 flash {
79 image-pos = <0x08000000>;
80 size = <0x20000>;
81 erase-value = <0>;
82
83 /* Information for sandbox */
84 ro {
85 image-pos = <0>;
86 size = <0xf000>;
87 };
88 wp-ro {
89 image-pos = <0xf000>;
90 size = <0x1000>;
91 };
92 rw {
93 image-pos = <0x10000>;
94 size = <0x10000>;
95 };
96 };
97 };
98
Yannick Fertré23f965a2019-10-07 15:29:05 +020099 dsi_host: dsi_host {
100 compatible = "sandbox,dsi-host";
101 };
102
Simon Glass2e7d35d2014-02-26 15:59:21 -0700103 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600104 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700105 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600106 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700107 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600108 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100109 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
110 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700111 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100112 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
113 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
114 <&gpio_b 7 GPIO_IN 3 2 1>,
115 <&gpio_b 8 GPIO_OUT 3 2 1>,
116 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100117 test3-gpios =
118 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
119 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
120 <&gpio_c 2 GPIO_OUT>,
121 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
122 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200123 <&gpio_c 5 GPIO_IN>,
124 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
125 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530126 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
127 test5-gpios = <&gpio_a 19>;
128
Simon Glassa1b17e42018-12-10 10:37:37 -0700129 int-value = <1234>;
130 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200131 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200132 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600133 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700134 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600135 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200136 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530137
138 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
139 <&muxcontroller0 2>, <&muxcontroller0 3>,
140 <&muxcontroller1>;
141 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
142 mux-syscon = <&syscon3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700143 };
144
145 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600146 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700147 compatible = "not,compatible";
148 };
149
150 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600151 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700152 };
153
Simon Glass5d9a88f2018-10-01 12:22:40 -0600154 backlight: backlight {
155 compatible = "pwm-backlight";
156 enable-gpios = <&gpio_a 1>;
157 power-supply = <&ldo_1>;
158 pwms = <&pwm 0 1000>;
159 default-brightness-level = <5>;
160 brightness-levels = <0 16 32 64 128 170 202 234 255>;
161 };
162
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200163 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200164 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200165 bind-test-child1 {
166 compatible = "sandbox,phy";
167 #phy-cells = <1>;
168 };
169
170 bind-test-child2 {
171 compatible = "simple-bus";
172 };
173 };
174
Simon Glass2e7d35d2014-02-26 15:59:21 -0700175 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600176 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700177 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600178 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700179 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530180
181 mux-controls = <&muxcontroller0 0>;
182 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700183 };
184
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200185 phy_provider0: gen_phy@0 {
186 compatible = "sandbox,phy";
187 #phy-cells = <1>;
188 };
189
190 phy_provider1: gen_phy@1 {
191 compatible = "sandbox,phy";
192 #phy-cells = <0>;
193 broken;
194 };
195
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200196 phy_provider2: gen_phy@2 {
197 compatible = "sandbox,phy";
198 #phy-cells = <0>;
199 };
200
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200201 gen_phy_user: gen_phy_user {
202 compatible = "simple-bus";
203 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
204 phy-names = "phy1", "phy2", "phy3";
205 };
206
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200207 gen_phy_user1: gen_phy_user1 {
208 compatible = "simple-bus";
209 phys = <&phy_provider0 0>, <&phy_provider2>;
210 phy-names = "phy1", "phy2";
211 };
212
Simon Glass2e7d35d2014-02-26 15:59:21 -0700213 some-bus {
214 #address-cells = <1>;
215 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600216 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600217 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600218 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700219 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600220 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700221 compatible = "denx,u-boot-fdt-test";
222 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600223 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700224 ping-add = <5>;
225 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600226 c-test@0 {
227 compatible = "denx,u-boot-fdt-test";
228 reg = <0>;
229 ping-expect = <6>;
230 ping-add = <6>;
231 };
232 c-test@1 {
233 compatible = "denx,u-boot-fdt-test";
234 reg = <1>;
235 ping-expect = <7>;
236 ping-add = <7>;
237 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700238 };
239
240 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600241 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600242 ping-expect = <6>;
243 ping-add = <6>;
244 compatible = "google,another-fdt-test";
245 };
246
247 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600248 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600249 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700250 ping-add = <6>;
251 compatible = "google,another-fdt-test";
252 };
253
Simon Glass9cc36a22015-01-25 08:27:05 -0700254 f-test {
255 compatible = "denx,u-boot-fdt-test";
256 };
257
258 g-test {
259 compatible = "denx,u-boot-fdt-test";
260 };
261
Bin Meng2786cd72018-10-10 22:07:01 -0700262 h-test {
263 compatible = "denx,u-boot-fdt-test1";
264 };
265
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200266 i-test {
267 compatible = "mediatek,u-boot-fdt-test";
268 #address-cells = <1>;
269 #size-cells = <0>;
270
271 subnode@0 {
272 reg = <0>;
273 };
274
275 subnode@1 {
276 reg = <1>;
277 };
278
279 subnode@2 {
280 reg = <2>;
281 };
282 };
283
Simon Glassdc12ebb2019-12-29 21:19:25 -0700284 devres-test {
285 compatible = "denx,u-boot-devres-test";
286 };
287
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530288 another-test {
289 reg = <0 2>;
290 compatible = "denx,u-boot-fdt-test";
291 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
292 test5-gpios = <&gpio_a 19>;
293 };
294
Simon Glass0f7b1112020-07-07 13:12:06 -0600295 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600296 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600297 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600298 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600299 child {
300 compatible = "denx,u-boot-acpi-test";
301 };
Simon Glassf50cc952020-04-08 16:57:34 -0600302 };
303
Simon Glass0f7b1112020-07-07 13:12:06 -0600304 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600305 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600306 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600307 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600308 };
309
Patrice Chotardee87a092017-09-04 14:55:57 +0200310 clocks {
311 clk_fixed: clk-fixed {
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <1234>;
315 };
Anup Patelb630d572019-02-25 08:14:55 +0000316
317 clk_fixed_factor: clk-fixed-factor {
318 compatible = "fixed-factor-clock";
319 #clock-cells = <0>;
320 clock-div = <3>;
321 clock-mult = <2>;
322 clocks = <&clk_fixed>;
323 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200324
325 osc {
326 compatible = "fixed-clock";
327 #clock-cells = <0>;
328 clock-frequency = <20000000>;
329 };
Stephen Warren135aa952016-06-17 09:44:00 -0600330 };
331
332 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600333 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600334 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200335 assigned-clocks = <&clk_sandbox 3>;
336 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600337 };
338
339 clk-test {
340 compatible = "sandbox,clk-test";
341 clocks = <&clk_fixed>,
342 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200343 <&clk_sandbox 0>,
344 <&clk_sandbox 3>,
345 <&clk_sandbox 2>;
346 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600347 };
348
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200349 ccf: clk-ccf {
350 compatible = "sandbox,clk-ccf";
351 };
352
Simon Glass171e9912015-05-22 15:42:15 -0600353 eth@10002000 {
354 compatible = "sandbox,eth";
355 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500356 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600357 };
358
359 eth_5: eth@10003000 {
360 compatible = "sandbox,eth";
361 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500362 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600363 };
364
Bin Meng71d79712015-08-27 22:25:53 -0700365 eth_3: sbe5 {
366 compatible = "sandbox,eth";
367 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500368 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700369 };
370
Simon Glass171e9912015-05-22 15:42:15 -0600371 eth@10004000 {
372 compatible = "sandbox,eth";
373 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500374 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600375 };
376
Rajan Vaja31b82172018-09-19 03:43:46 -0700377 firmware {
378 sandbox_firmware: sandbox-firmware {
379 compatible = "sandbox,firmware";
380 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200381
382 sandbox-scmi-agent@0 {
383 compatible = "sandbox,scmi-agent";
384 #address-cells = <1>;
385 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200386
387 clk_scmi0: protocol@14 {
388 reg = <0x14>;
389 #clock-cells = <1>;
390 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200391
392 reset_scmi0: protocol@16 {
393 reg = <0x16>;
394 #reset-cells = <1>;
395 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200396 };
397
398 sandbox-scmi-agent@1 {
399 compatible = "sandbox,scmi-agent";
400 #address-cells = <1>;
401 #size-cells = <0>;
402
Etienne Carriere87d4f272020-09-09 18:44:05 +0200403 clk_scmi1: protocol@14 {
404 reg = <0x14>;
405 #clock-cells = <1>;
406 };
407
Etienne Carriere358599e2020-09-09 18:44:00 +0200408 protocol@10 {
409 reg = <0x10>;
410 };
411 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700412 };
413
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100414 pinctrl-gpio {
415 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700416
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100417 gpio_a: base-gpios {
418 compatible = "sandbox,gpio";
419 gpio-controller;
420 #gpio-cells = <1>;
421 gpio-bank-name = "a";
422 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200423 hog_input_active_low {
424 gpio-hog;
425 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200426 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200427 };
428 hog_input_active_high {
429 gpio-hog;
430 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200431 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200432 };
433 hog_output_low {
434 gpio-hog;
435 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200436 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200437 };
438 hog_output_high {
439 gpio-hog;
440 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200441 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200442 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100443 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600444
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100445 gpio_b: extra-gpios {
446 compatible = "sandbox,gpio";
447 gpio-controller;
448 #gpio-cells = <5>;
449 gpio-bank-name = "b";
450 sandbox,gpio-count = <10>;
451 };
452
453 gpio_c: pinmux-gpios {
454 compatible = "sandbox,gpio";
455 gpio-controller;
456 #gpio-cells = <2>;
457 gpio-bank-name = "c";
458 sandbox,gpio-count = <10>;
459 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100460 };
461
Simon Glassecc2ed52014-12-10 08:55:55 -0700462 i2c@0 {
463 #address-cells = <1>;
464 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600465 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700466 compatible = "sandbox,i2c";
467 clock-frequency = <100000>;
468 eeprom@2c {
469 reg = <0x2c>;
470 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700471 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200472 partitions {
473 compatible = "fixed-partitions";
474 #address-cells = <1>;
475 #size-cells = <1>;
476 bootcount_i2c: bootcount@10 {
477 reg = <10 2>;
478 };
479 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700480 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200481
Simon Glass52d3bc52015-05-22 15:42:17 -0600482 rtc_0: rtc@43 {
483 reg = <0x43>;
484 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700485 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600486 };
487
488 rtc_1: rtc@61 {
489 reg = <0x61>;
490 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700491 sandbox,emul = <&emul1>;
492 };
493
494 i2c_emul: emul {
495 reg = <0xff>;
496 compatible = "sandbox,i2c-emul-parent";
497 emul_eeprom: emul-eeprom {
498 compatible = "sandbox,i2c-eeprom";
499 sandbox,filename = "i2c.bin";
500 sandbox,size = <256>;
501 };
502 emul0: emul0 {
503 compatible = "sandbox,i2c-rtc";
504 };
505 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600506 compatible = "sandbox,i2c-rtc";
507 };
508 };
509
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200510 sandbox_pmic: sandbox_pmic {
511 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700512 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200513 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200514
515 mc34708: pmic@41 {
516 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700517 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200518 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700519 };
520
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100521 bootcount@0 {
522 compatible = "u-boot,bootcount-rtc";
523 rtc = <&rtc_1>;
524 offset = <0x13>;
525 };
526
Michal Simekf692b472020-05-28 11:48:55 +0200527 bootcount {
528 compatible = "u-boot,bootcount-i2c-eeprom";
529 i2c-eeprom = <&bootcount_i2c>;
530 };
531
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100532 adc@0 {
533 compatible = "sandbox,adc";
534 vdd-supply = <&buck2>;
535 vss-microvolts = <0>;
536 };
537
Simon Glass02554352020-02-06 09:55:00 -0700538 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700539 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700540 interrupt-controller;
541 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700542 };
543
Simon Glass3c97c4f2016-01-18 19:52:26 -0700544 lcd {
545 u-boot,dm-pre-reloc;
546 compatible = "sandbox,lcd-sdl";
547 xres = <1366>;
548 yres = <768>;
549 };
550
Simon Glass3c43fba2015-07-06 12:54:34 -0600551 leds {
552 compatible = "gpio-leds";
553
554 iracibble {
555 gpios = <&gpio_a 1 0>;
556 label = "sandbox:red";
557 };
558
559 martinet {
560 gpios = <&gpio_a 2 0>;
561 label = "sandbox:green";
562 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200563
564 default_on {
565 gpios = <&gpio_a 5 0>;
566 label = "sandbox:default_on";
567 default-state = "on";
568 };
569
570 default_off {
571 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400572 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200573 default-state = "off";
574 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600575 };
576
Stephen Warren8961b522016-05-16 17:41:37 -0600577 mbox: mbox {
578 compatible = "sandbox,mbox";
579 #mbox-cells = <1>;
580 };
581
582 mbox-test {
583 compatible = "sandbox,mbox-test";
584 mboxes = <&mbox 100>, <&mbox 1>;
585 mbox-names = "other", "test";
586 };
587
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900588 cpus {
Sean Anderson7616e362020-09-28 10:52:23 -0400589 timebase-frequency = <2000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900590 cpu-test1 {
Sean Anderson7616e362020-09-28 10:52:23 -0400591 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900592 compatible = "sandbox,cpu_sandbox";
593 u-boot,dm-pre-reloc;
594 };
Mario Sixfa44b532018-08-06 10:23:44 +0200595
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900596 cpu-test2 {
597 compatible = "sandbox,cpu_sandbox";
598 u-boot,dm-pre-reloc;
599 };
Mario Sixfa44b532018-08-06 10:23:44 +0200600
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900601 cpu-test3 {
602 compatible = "sandbox,cpu_sandbox";
603 u-boot,dm-pre-reloc;
604 };
Mario Sixfa44b532018-08-06 10:23:44 +0200605 };
606
Dave Gerlach21e3c212020-07-15 23:39:58 -0500607 chipid: chipid {
608 compatible = "sandbox,soc";
609 };
610
Simon Glasse96fa6c2018-12-10 10:37:34 -0700611 i2s: i2s {
612 compatible = "sandbox,i2s";
613 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700614 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700615 };
616
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200617 nop-test_0 {
618 compatible = "sandbox,nop_sandbox1";
619 nop-test_1 {
620 compatible = "sandbox,nop_sandbox2";
621 bind = "True";
622 };
623 nop-test_2 {
624 compatible = "sandbox,nop_sandbox2";
625 bind = "False";
626 };
627 };
628
Mario Six004e67c2018-07-31 14:24:14 +0200629 misc-test {
630 compatible = "sandbox,misc_sandbox";
631 };
632
Simon Glasse48eeb92017-04-23 20:02:07 -0600633 mmc2 {
634 compatible = "sandbox,mmc";
635 };
636
637 mmc1 {
638 compatible = "sandbox,mmc";
639 };
640
641 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600642 compatible = "sandbox,mmc";
643 };
644
Simon Glassb45c8332019-02-16 20:24:50 -0700645 pch {
646 compatible = "sandbox,pch";
647 };
648
Tom Rini42c64d12020-02-11 12:41:23 -0500649 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700650 compatible = "sandbox,pci";
651 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500652 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700653 #address-cells = <3>;
654 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600655 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700656 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700657 pci@0,0 {
658 compatible = "pci-generic";
659 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600660 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700661 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300662 pci@1,0 {
663 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600664 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
665 reg = <0x02000814 0 0 0 0
666 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600667 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300668 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700669 p2sb-pci@2,0 {
670 compatible = "sandbox,p2sb";
671 reg = <0x02001010 0 0 0 0>;
672 sandbox,emul = <&p2sb_emul>;
673
674 adder {
675 intel,p2sb-port-id = <3>;
676 compatible = "sandbox,adder";
677 };
678 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700679 pci@1e,0 {
680 compatible = "sandbox,pmc";
681 reg = <0xf000 0 0 0 0>;
682 sandbox,emul = <&pmc_emul1e>;
683 acpi-base = <0x400>;
684 gpe0-dwx-mask = <0xf>;
685 gpe0-dwx-shift-base = <4>;
686 gpe0-dw = <6 7 9>;
687 gpe0-sts = <0x20>;
688 gpe0-en = <0x30>;
689 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700690 pci@1f,0 {
691 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600692 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
693 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600694 sandbox,emul = <&swap_case_emul0_1f>;
695 };
696 };
697
698 pci-emul0 {
699 compatible = "sandbox,pci-emul-parent";
700 swap_case_emul0_0: emul0@0,0 {
701 compatible = "sandbox,swap-case";
702 };
703 swap_case_emul0_1: emul0@1,0 {
704 compatible = "sandbox,swap-case";
705 use-ea;
706 };
707 swap_case_emul0_1f: emul0@1f,0 {
708 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700709 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700710 p2sb_emul: emul@2,0 {
711 compatible = "sandbox,p2sb-emul";
712 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700713 pmc_emul1e: emul@1e,0 {
714 compatible = "sandbox,pmc-emul";
715 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700716 };
717
Tom Rini42c64d12020-02-11 12:41:23 -0500718 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700719 compatible = "sandbox,pci";
720 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500721 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700722 #address-cells = <3>;
723 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700724 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
725 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
726 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700727 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200728 0x0c 0x00 0x1234 0x5678
729 0x10 0x00 0x1234 0x5678>;
730 pci@10,0 {
731 reg = <0x8000 0 0 0 0>;
732 };
Bin Mengdee4d752018-08-03 01:14:41 -0700733 };
734
Tom Rini42c64d12020-02-11 12:41:23 -0500735 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700736 compatible = "sandbox,pci";
737 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500738 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700739 #address-cells = <3>;
740 #size-cells = <2>;
741 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
742 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
743 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
744 pci@1f,0 {
745 compatible = "pci-generic";
746 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600747 sandbox,emul = <&swap_case_emul2_1f>;
748 };
749 };
750
751 pci-emul2 {
752 compatible = "sandbox,pci-emul-parent";
753 swap_case_emul2_1f: emul2@1f,0 {
754 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700755 };
756 };
757
Ramon Friedbb413332019-04-27 11:15:23 +0300758 pci_ep: pci_ep {
759 compatible = "sandbox,pci_ep";
760 };
761
Simon Glass98561572017-04-23 20:10:44 -0600762 probing {
763 compatible = "simple-bus";
764 test1 {
765 compatible = "denx,u-boot-probe-test";
766 };
767
768 test2 {
769 compatible = "denx,u-boot-probe-test";
770 };
771
772 test3 {
773 compatible = "denx,u-boot-probe-test";
774 };
775
776 test4 {
777 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100778 first-syscon = <&syscon0>;
779 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100780 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600781 };
782 };
783
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600784 pwrdom: power-domain {
785 compatible = "sandbox,power-domain";
786 #power-domain-cells = <1>;
787 };
788
789 power-domain-test {
790 compatible = "sandbox,power-domain-test";
791 power-domains = <&pwrdom 2>;
792 };
793
Simon Glass5d9a88f2018-10-01 12:22:40 -0600794 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600795 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600796 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600797 };
798
799 pwm2 {
800 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600801 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600802 };
803
Simon Glass64ce0ca2015-07-06 12:54:31 -0600804 ram {
805 compatible = "sandbox,ram";
806 };
807
Simon Glass5010d982015-07-06 12:54:29 -0600808 reset@0 {
809 compatible = "sandbox,warm-reset";
810 };
811
812 reset@1 {
813 compatible = "sandbox,reset";
814 };
815
Stephen Warren4581b712016-06-17 09:43:59 -0600816 resetc: reset-ctl {
817 compatible = "sandbox,reset-ctl";
818 #reset-cells = <1>;
819 };
820
821 reset-ctl-test {
822 compatible = "sandbox,reset-ctl-test";
823 resets = <&resetc 100>, <&resetc 2>;
824 reset-names = "other", "test";
825 };
826
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530827 rng {
828 compatible = "sandbox,sandbox-rng";
829 };
830
Nishanth Menon52159402015-09-17 15:42:41 -0500831 rproc_1: rproc@1 {
832 compatible = "sandbox,test-processor";
833 remoteproc-name = "remoteproc-test-dev1";
834 };
835
836 rproc_2: rproc@2 {
837 compatible = "sandbox,test-processor";
838 internal-memory-mapped;
839 remoteproc-name = "remoteproc-test-dev2";
840 };
841
Simon Glass5d9a88f2018-10-01 12:22:40 -0600842 panel {
843 compatible = "simple-panel";
844 backlight = <&backlight 0 100>;
845 };
846
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300847 smem@0 {
848 compatible = "sandbox,smem";
849 };
850
Simon Glassd4901892018-12-10 10:37:36 -0700851 sound {
852 compatible = "sandbox,sound";
853 cpu {
854 sound-dai = <&i2s 0>;
855 };
856
857 codec {
858 sound-dai = <&audio 0>;
859 };
860 };
861
Simon Glass0ae0cb72014-10-13 23:42:11 -0600862 spi@0 {
863 #address-cells = <1>;
864 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600865 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600866 compatible = "sandbox,spi";
867 cs-gpios = <0>, <&gpio_a 0>;
868 spi.bin@0 {
869 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000870 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600871 spi-max-frequency = <40000000>;
872 sandbox,filename = "spi.bin";
873 };
874 };
875
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100876 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600877 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200878 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600879 };
880
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100881 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600882 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600883 reg = <0x20 5
884 0x28 6
885 0x30 7
886 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600887 };
888
Patrick Delaunaya442e612019-03-07 09:57:13 +0100889 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900890 compatible = "simple-mfd", "syscon";
891 reg = <0x40 5
892 0x48 6
893 0x50 7
894 0x58 8>;
895 };
896
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530897 syscon3: syscon@3 {
898 compatible = "simple-mfd", "syscon";
899 reg = <0x000100 0x10>;
900
901 muxcontroller0: a-mux-controller {
902 compatible = "mmio-mux";
903 #mux-control-cells = <1>;
904
905 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
906 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
907 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
908 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
909 u-boot,mux-autoprobe;
910 };
911 };
912
913 muxcontroller1: emul-mux-controller {
914 compatible = "mux-emul";
915 #mux-control-cells = <0>;
916 u-boot,mux-autoprobe;
917 idle-state = <0xabcd>;
918 };
919
Sean Anderson7616e362020-09-28 10:52:23 -0400920 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +0800921 compatible = "sandbox,timer";
922 clock-frequency = <1000000>;
923 };
924
Sean Anderson7616e362020-09-28 10:52:23 -0400925 timer@1 {
926 compatible = "sandbox,timer";
927 sandbox,timebase-frequency-fallback;
928 };
929
Miquel Raynalb91ad162018-05-15 11:57:27 +0200930 tpm2 {
931 compatible = "sandbox,tpm2";
932 };
933
Simon Glass171e9912015-05-22 15:42:15 -0600934 uart0: serial {
935 compatible = "sandbox,serial";
936 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500937 };
938
Simon Glasse00cb222015-03-25 12:23:05 -0600939 usb_0: usb@0 {
940 compatible = "sandbox,usb";
941 status = "disabled";
942 hub {
943 compatible = "sandbox,usb-hub";
944 #address-cells = <1>;
945 #size-cells = <0>;
946 flash-stick {
947 reg = <0>;
948 compatible = "sandbox,usb-flash";
949 };
950 };
951 };
952
953 usb_1: usb@1 {
954 compatible = "sandbox,usb";
955 hub {
956 compatible = "usb-hub";
957 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +0200958 #address-cells = <1>;
959 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -0600960 hub-emul {
961 compatible = "sandbox,usb-hub";
962 #address-cells = <1>;
963 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700964 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600965 reg = <0>;
966 compatible = "sandbox,usb-flash";
967 sandbox,filepath = "testflash.bin";
968 };
969
Simon Glass431cbd62015-11-08 23:48:01 -0700970 flash-stick@1 {
971 reg = <1>;
972 compatible = "sandbox,usb-flash";
973 sandbox,filepath = "testflash1.bin";
974 };
975
976 flash-stick@2 {
977 reg = <2>;
978 compatible = "sandbox,usb-flash";
979 sandbox,filepath = "testflash2.bin";
980 };
981
Simon Glassbff1a712015-11-08 23:48:08 -0700982 keyb@3 {
983 reg = <3>;
984 compatible = "sandbox,usb-keyb";
985 };
986
Simon Glasse00cb222015-03-25 12:23:05 -0600987 };
Michael Wallec03b7612020-06-02 01:47:07 +0200988
989 usbstor@1 {
990 reg = <1>;
991 };
992 usbstor@3 {
993 reg = <3>;
994 };
Simon Glasse00cb222015-03-25 12:23:05 -0600995 };
996 };
997
998 usb_2: usb@2 {
999 compatible = "sandbox,usb";
1000 status = "disabled";
1001 };
1002
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001003 spmi: spmi@0 {
1004 compatible = "sandbox,spmi";
1005 #address-cells = <0x1>;
1006 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001007 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001008 pm8916@0 {
1009 compatible = "qcom,spmi-pmic";
1010 reg = <0x0 0x1>;
1011 #address-cells = <0x1>;
1012 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001013 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001014
1015 spmi_gpios: gpios@c000 {
1016 compatible = "qcom,pm8916-gpio";
1017 reg = <0xc000 0x400>;
1018 gpio-controller;
1019 gpio-count = <4>;
1020 #gpio-cells = <2>;
1021 gpio-bank-name="spmi";
1022 };
1023 };
1024 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001025
1026 wdt0: wdt@0 {
1027 compatible = "sandbox,wdt";
1028 };
Rob Clarkf2006802018-01-10 11:33:30 +01001029
Mario Six957983e2018-08-09 14:51:19 +02001030 axi: axi@0 {
1031 compatible = "sandbox,axi";
1032 #address-cells = <0x1>;
1033 #size-cells = <0x1>;
1034 store@0 {
1035 compatible = "sandbox,sandbox_store";
1036 reg = <0x0 0x400>;
1037 };
1038 };
1039
Rob Clarkf2006802018-01-10 11:33:30 +01001040 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001041 #address-cells = <1>;
1042 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001043 setting = "sunrise ohoka";
1044 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001045 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001046 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001047 chosen-test {
1048 compatible = "denx,u-boot-fdt-test";
1049 reg = <9 1>;
1050 };
1051 };
Mario Sixe8d52912018-03-12 14:53:33 +01001052
1053 translation-test@8000 {
1054 compatible = "simple-bus";
1055 reg = <0x8000 0x4000>;
1056
1057 #address-cells = <0x2>;
1058 #size-cells = <0x1>;
1059
1060 ranges = <0 0x0 0x8000 0x1000
1061 1 0x100 0x9000 0x1000
1062 2 0x200 0xA000 0x1000
1063 3 0x300 0xB000 0x1000
1064 >;
1065
Fabien Dessenne641067f2019-05-31 15:11:30 +02001066 dma-ranges = <0 0x000 0x10000000 0x1000
1067 1 0x100 0x20000000 0x1000
1068 >;
1069
Mario Sixe8d52912018-03-12 14:53:33 +01001070 dev@0,0 {
1071 compatible = "denx,u-boot-fdt-dummy";
1072 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001073 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001074 };
1075
1076 dev@1,100 {
1077 compatible = "denx,u-boot-fdt-dummy";
1078 reg = <1 0x100 0x1000>;
1079
1080 };
1081
1082 dev@2,200 {
1083 compatible = "denx,u-boot-fdt-dummy";
1084 reg = <2 0x200 0x1000>;
1085 };
1086
1087
1088 noxlatebus@3,300 {
1089 compatible = "simple-bus";
1090 reg = <3 0x300 0x1000>;
1091
1092 #address-cells = <0x1>;
1093 #size-cells = <0x0>;
1094
1095 dev@42 {
1096 compatible = "denx,u-boot-fdt-dummy";
1097 reg = <0x42>;
1098 };
1099 };
1100 };
Mario Six4eea5312018-09-27 09:19:31 +02001101
1102 osd {
1103 compatible = "sandbox,sandbox_osd";
1104 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001105
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001106 sandbox_tee {
1107 compatible = "sandbox,tee";
1108 };
Bin Meng4f89d492018-10-15 02:21:26 -07001109
1110 sandbox_virtio1 {
1111 compatible = "sandbox,virtio1";
1112 };
1113
1114 sandbox_virtio2 {
1115 compatible = "sandbox,virtio2";
1116 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001117
Etienne Carriere87d4f272020-09-09 18:44:05 +02001118 sandbox_scmi {
1119 compatible = "sandbox,scmi-devices";
1120 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001121 resets = <&reset_scmi0 3>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001122 };
1123
Patrice Chotardf41a8242018-10-24 14:10:23 +02001124 pinctrl {
1125 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001126
Sean Anderson7f0f1802020-09-14 11:01:57 -04001127 pinctrl-names = "default", "alternate";
1128 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1129 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001130
Sean Anderson7f0f1802020-09-14 11:01:57 -04001131 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001132 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001133 pins = "P5";
1134 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001135 bias-pull-up;
1136 input-disable;
1137 };
1138 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001139 pins = "P6";
1140 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001141 output-high;
1142 drive-open-drain;
1143 };
1144 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001145 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001146 bias-pull-down;
1147 input-enable;
1148 };
1149 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001150 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001151 bias-disable;
1152 };
1153 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001154
1155 pinctrl_i2c: i2c {
1156 groups {
1157 groups = "I2C_UART";
1158 function = "I2C";
1159 };
1160
1161 pins {
1162 pins = "P0", "P1";
1163 drive-open-drain;
1164 };
1165 };
1166
1167 pinctrl_i2s: i2s {
1168 groups = "SPI_I2S";
1169 function = "I2S";
1170 };
1171
1172 pinctrl_spi: spi {
1173 groups = "SPI_I2S";
1174 function = "SPI";
1175
1176 cs {
1177 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1178 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1179 };
1180 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001181 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001182
1183 hwspinlock@0 {
1184 compatible = "sandbox,hwspinlock";
1185 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001186
1187 dma: dma {
1188 compatible = "sandbox,dma";
1189 #dma-cells = <1>;
1190
1191 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1192 dma-names = "m2m", "tx0", "rx0";
1193 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001194
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001195 /*
1196 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1197 * end of the test. If parent mdio is removed first, clean-up of the
1198 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1199 * active at the end of the test. That it turn doesn't allow the mdio
1200 * class to be destroyed, triggering an error.
1201 */
1202 mdio-mux-test {
1203 compatible = "sandbox,mdio-mux";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1206 mdio-parent-bus = <&mdio>;
1207
1208 mdio-ch-test@0 {
1209 reg = <0>;
1210 };
1211 mdio-ch-test@1 {
1212 reg = <1>;
1213 };
1214 };
1215
1216 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001217 compatible = "sandbox,mdio";
1218 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001219
1220 pm-bus-test {
1221 compatible = "simple-pm-bus";
1222 clocks = <&clk_sandbox 4>;
1223 power-domains = <&pwrdom 1>;
1224 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001225
1226 resetc2: syscon-reset {
1227 compatible = "syscon-reset";
1228 #reset-cells = <1>;
1229 regmap = <&syscon0>;
1230 offset = <1>;
1231 mask = <0x27FFFFFF>;
1232 assert-high = <0>;
1233 };
1234
1235 syscon-reset-test {
1236 compatible = "sandbox,misc_sandbox";
1237 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1238 reset-names = "valid", "no_mask", "out_of_range";
1239 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301240
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001241 sysinfo {
1242 compatible = "sandbox,sysinfo-sandbox";
1243 };
1244
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301245 some_regmapped-bus {
1246 #address-cells = <0x1>;
1247 #size-cells = <0x1>;
1248
1249 ranges = <0x0 0x0 0x10>;
1250 compatible = "simple-bus";
1251
1252 regmap-test_0 {
1253 reg = <0 0x10>;
1254 compatible = "sandbox,regmap_test";
1255 };
1256 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001257};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001258
1259#include "sandbox_pmic.dtsi"