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Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01006
Simon Glass2e7d35d2014-02-26 15:59:21 -07007/ {
8 model = "sandbox";
9 compatible = "sandbox";
10 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060011 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070012
Simon Glass00606d72014-07-23 06:55:03 -060013 aliases {
14 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060015 eth0 = "/eth@10002000";
Bin Meng71d79712015-08-27 22:25:53 -070016 eth3 = &eth_3;
Simon Glass171e9912015-05-22 15:42:15 -060017 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060018 gpio1 = &gpio_a;
19 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010020 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070021 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060022 mmc0 = "/mmc0";
23 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070024 pci0 = &pci0;
25 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070026 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020027 remoteproc0 = &rproc_1;
28 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060029 rtc0 = &rtc_0;
30 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060031 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020032 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070033 testbus3 = "/some-bus";
34 testfdt0 = "/some-bus/c-test@0";
35 testfdt1 = "/some-bus/c-test@1";
36 testfdt3 = "/b-test";
37 testfdt5 = "/some-bus/c-test@5";
38 testfdt8 = "/a-test";
Eugeniu Rosca507cef32018-05-19 14:13:55 +020039 fdt-dummy0 = "/translation-test@8000/dev@0,0";
40 fdt-dummy1 = "/translation-test@8000/dev@1,100";
41 fdt-dummy2 = "/translation-test@8000/dev@2,200";
42 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060043 usb0 = &usb_0;
44 usb1 = &usb_1;
45 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020046 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020047 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060048 };
49
Simon Glassce6d99a2018-12-10 10:37:33 -070050 audio: audio-codec {
51 compatible = "sandbox,audio-codec";
52 #sound-dai-cells = <1>;
53 };
54
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020055 buttons {
56 compatible = "gpio-keys";
57
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020058 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020059 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020060 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020061 };
62
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020063 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020064 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020065 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020066 };
67 };
68
Simon Glasse96fa6c2018-12-10 10:37:34 -070069 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -060070 reg = <0 0>;
71 compatible = "google,cros-ec-sandbox";
72
73 /*
74 * This describes the flash memory within the EC. Note
75 * that the STM32L flash erases to 0, not 0xff.
76 */
77 flash {
78 image-pos = <0x08000000>;
79 size = <0x20000>;
80 erase-value = <0>;
81
82 /* Information for sandbox */
83 ro {
84 image-pos = <0>;
85 size = <0xf000>;
86 };
87 wp-ro {
88 image-pos = <0xf000>;
89 size = <0x1000>;
90 };
91 rw {
92 image-pos = <0x10000>;
93 size = <0x10000>;
94 };
95 };
96 };
97
Yannick Fertré23f965a2019-10-07 15:29:05 +020098 dsi_host: dsi_host {
99 compatible = "sandbox,dsi-host";
100 };
101
Simon Glass2e7d35d2014-02-26 15:59:21 -0700102 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600103 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700104 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600105 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700106 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600107 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100108 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
109 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700110 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100111 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
112 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
113 <&gpio_b 7 GPIO_IN 3 2 1>,
114 <&gpio_b 8 GPIO_OUT 3 2 1>,
115 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100116 test3-gpios =
117 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
118 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
119 <&gpio_c 2 GPIO_OUT>,
120 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
121 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200122 <&gpio_c 5 GPIO_IN>,
123 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
124 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530125 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
126 test5-gpios = <&gpio_a 19>;
127
Simon Glassa1b17e42018-12-10 10:37:37 -0700128 int-value = <1234>;
129 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200130 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200131 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600132 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700133 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600134 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200135 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700136 };
137
138 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600139 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700140 compatible = "not,compatible";
141 };
142
143 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600144 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700145 };
146
Simon Glass5d9a88f2018-10-01 12:22:40 -0600147 backlight: backlight {
148 compatible = "pwm-backlight";
149 enable-gpios = <&gpio_a 1>;
150 power-supply = <&ldo_1>;
151 pwms = <&pwm 0 1000>;
152 default-brightness-level = <5>;
153 brightness-levels = <0 16 32 64 128 170 202 234 255>;
154 };
155
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200156 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200157 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200158 bind-test-child1 {
159 compatible = "sandbox,phy";
160 #phy-cells = <1>;
161 };
162
163 bind-test-child2 {
164 compatible = "simple-bus";
165 };
166 };
167
Simon Glass2e7d35d2014-02-26 15:59:21 -0700168 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600169 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700170 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600171 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700172 ping-add = <3>;
173 };
174
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200175 phy_provider0: gen_phy@0 {
176 compatible = "sandbox,phy";
177 #phy-cells = <1>;
178 };
179
180 phy_provider1: gen_phy@1 {
181 compatible = "sandbox,phy";
182 #phy-cells = <0>;
183 broken;
184 };
185
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200186 phy_provider2: gen_phy@2 {
187 compatible = "sandbox,phy";
188 #phy-cells = <0>;
189 };
190
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200191 gen_phy_user: gen_phy_user {
192 compatible = "simple-bus";
193 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
194 phy-names = "phy1", "phy2", "phy3";
195 };
196
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200197 gen_phy_user1: gen_phy_user1 {
198 compatible = "simple-bus";
199 phys = <&phy_provider0 0>, <&phy_provider2>;
200 phy-names = "phy1", "phy2";
201 };
202
Simon Glass2e7d35d2014-02-26 15:59:21 -0700203 some-bus {
204 #address-cells = <1>;
205 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600206 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600207 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600208 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700209 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600210 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700211 compatible = "denx,u-boot-fdt-test";
212 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600213 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700214 ping-add = <5>;
215 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600216 c-test@0 {
217 compatible = "denx,u-boot-fdt-test";
218 reg = <0>;
219 ping-expect = <6>;
220 ping-add = <6>;
221 };
222 c-test@1 {
223 compatible = "denx,u-boot-fdt-test";
224 reg = <1>;
225 ping-expect = <7>;
226 ping-add = <7>;
227 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700228 };
229
230 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600231 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600232 ping-expect = <6>;
233 ping-add = <6>;
234 compatible = "google,another-fdt-test";
235 };
236
237 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600238 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600239 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700240 ping-add = <6>;
241 compatible = "google,another-fdt-test";
242 };
243
Simon Glass9cc36a22015-01-25 08:27:05 -0700244 f-test {
245 compatible = "denx,u-boot-fdt-test";
246 };
247
248 g-test {
249 compatible = "denx,u-boot-fdt-test";
250 };
251
Bin Meng2786cd72018-10-10 22:07:01 -0700252 h-test {
253 compatible = "denx,u-boot-fdt-test1";
254 };
255
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200256 i-test {
257 compatible = "mediatek,u-boot-fdt-test";
258 #address-cells = <1>;
259 #size-cells = <0>;
260
261 subnode@0 {
262 reg = <0>;
263 };
264
265 subnode@1 {
266 reg = <1>;
267 };
268
269 subnode@2 {
270 reg = <2>;
271 };
272 };
273
Simon Glassdc12ebb2019-12-29 21:19:25 -0700274 devres-test {
275 compatible = "denx,u-boot-devres-test";
276 };
277
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530278 another-test {
279 reg = <0 2>;
280 compatible = "denx,u-boot-fdt-test";
281 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
282 test5-gpios = <&gpio_a 19>;
283 };
284
Simon Glass0f7b1112020-07-07 13:12:06 -0600285 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600286 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600287 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600288 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600289 child {
290 compatible = "denx,u-boot-acpi-test";
291 };
Simon Glassf50cc952020-04-08 16:57:34 -0600292 };
293
Simon Glass0f7b1112020-07-07 13:12:06 -0600294 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600295 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600296 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600297 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600298 };
299
Patrice Chotardee87a092017-09-04 14:55:57 +0200300 clocks {
301 clk_fixed: clk-fixed {
302 compatible = "fixed-clock";
303 #clock-cells = <0>;
304 clock-frequency = <1234>;
305 };
Anup Patelb630d572019-02-25 08:14:55 +0000306
307 clk_fixed_factor: clk-fixed-factor {
308 compatible = "fixed-factor-clock";
309 #clock-cells = <0>;
310 clock-div = <3>;
311 clock-mult = <2>;
312 clocks = <&clk_fixed>;
313 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200314
315 osc {
316 compatible = "fixed-clock";
317 #clock-cells = <0>;
318 clock-frequency = <20000000>;
319 };
Stephen Warren135aa952016-06-17 09:44:00 -0600320 };
321
322 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600323 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600324 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200325 assigned-clocks = <&clk_sandbox 3>;
326 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600327 };
328
329 clk-test {
330 compatible = "sandbox,clk-test";
331 clocks = <&clk_fixed>,
332 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200333 <&clk_sandbox 0>,
334 <&clk_sandbox 3>,
335 <&clk_sandbox 2>;
336 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600337 };
338
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200339 ccf: clk-ccf {
340 compatible = "sandbox,clk-ccf";
341 };
342
Simon Glass171e9912015-05-22 15:42:15 -0600343 eth@10002000 {
344 compatible = "sandbox,eth";
345 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500346 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600347 };
348
349 eth_5: eth@10003000 {
350 compatible = "sandbox,eth";
351 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500352 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600353 };
354
Bin Meng71d79712015-08-27 22:25:53 -0700355 eth_3: sbe5 {
356 compatible = "sandbox,eth";
357 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500358 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700359 };
360
Simon Glass171e9912015-05-22 15:42:15 -0600361 eth@10004000 {
362 compatible = "sandbox,eth";
363 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500364 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600365 };
366
Rajan Vaja31b82172018-09-19 03:43:46 -0700367 firmware {
368 sandbox_firmware: sandbox-firmware {
369 compatible = "sandbox,firmware";
370 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200371
372 sandbox-scmi-agent@0 {
373 compatible = "sandbox,scmi-agent";
374 #address-cells = <1>;
375 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200376
377 clk_scmi0: protocol@14 {
378 reg = <0x14>;
379 #clock-cells = <1>;
380 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200381
382 reset_scmi0: protocol@16 {
383 reg = <0x16>;
384 #reset-cells = <1>;
385 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200386 };
387
388 sandbox-scmi-agent@1 {
389 compatible = "sandbox,scmi-agent";
390 #address-cells = <1>;
391 #size-cells = <0>;
392
Etienne Carriere87d4f272020-09-09 18:44:05 +0200393 clk_scmi1: protocol@14 {
394 reg = <0x14>;
395 #clock-cells = <1>;
396 };
397
Etienne Carriere358599e2020-09-09 18:44:00 +0200398 protocol@10 {
399 reg = <0x10>;
400 };
401 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700402 };
403
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100404 pinctrl-gpio {
405 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700406
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100407 gpio_a: base-gpios {
408 compatible = "sandbox,gpio";
409 gpio-controller;
410 #gpio-cells = <1>;
411 gpio-bank-name = "a";
412 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200413 hog_input_active_low {
414 gpio-hog;
415 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200416 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200417 };
418 hog_input_active_high {
419 gpio-hog;
420 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200421 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200422 };
423 hog_output_low {
424 gpio-hog;
425 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200426 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200427 };
428 hog_output_high {
429 gpio-hog;
430 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200431 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200432 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100433 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600434
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100435 gpio_b: extra-gpios {
436 compatible = "sandbox,gpio";
437 gpio-controller;
438 #gpio-cells = <5>;
439 gpio-bank-name = "b";
440 sandbox,gpio-count = <10>;
441 };
442
443 gpio_c: pinmux-gpios {
444 compatible = "sandbox,gpio";
445 gpio-controller;
446 #gpio-cells = <2>;
447 gpio-bank-name = "c";
448 sandbox,gpio-count = <10>;
449 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100450 };
451
Simon Glassecc2ed52014-12-10 08:55:55 -0700452 i2c@0 {
453 #address-cells = <1>;
454 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600455 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700456 compatible = "sandbox,i2c";
457 clock-frequency = <100000>;
458 eeprom@2c {
459 reg = <0x2c>;
460 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700461 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200462 partitions {
463 compatible = "fixed-partitions";
464 #address-cells = <1>;
465 #size-cells = <1>;
466 bootcount_i2c: bootcount@10 {
467 reg = <10 2>;
468 };
469 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700470 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200471
Simon Glass52d3bc52015-05-22 15:42:17 -0600472 rtc_0: rtc@43 {
473 reg = <0x43>;
474 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700475 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600476 };
477
478 rtc_1: rtc@61 {
479 reg = <0x61>;
480 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700481 sandbox,emul = <&emul1>;
482 };
483
484 i2c_emul: emul {
485 reg = <0xff>;
486 compatible = "sandbox,i2c-emul-parent";
487 emul_eeprom: emul-eeprom {
488 compatible = "sandbox,i2c-eeprom";
489 sandbox,filename = "i2c.bin";
490 sandbox,size = <256>;
491 };
492 emul0: emul0 {
493 compatible = "sandbox,i2c-rtc";
494 };
495 emul1: emull {
Simon Glass52d3bc52015-05-22 15:42:17 -0600496 compatible = "sandbox,i2c-rtc";
497 };
498 };
499
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200500 sandbox_pmic: sandbox_pmic {
501 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700502 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200503 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200504
505 mc34708: pmic@41 {
506 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700507 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200508 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700509 };
510
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100511 bootcount@0 {
512 compatible = "u-boot,bootcount-rtc";
513 rtc = <&rtc_1>;
514 offset = <0x13>;
515 };
516
Michal Simekf692b472020-05-28 11:48:55 +0200517 bootcount {
518 compatible = "u-boot,bootcount-i2c-eeprom";
519 i2c-eeprom = <&bootcount_i2c>;
520 };
521
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100522 adc@0 {
523 compatible = "sandbox,adc";
524 vdd-supply = <&buck2>;
525 vss-microvolts = <0>;
526 };
527
Simon Glass02554352020-02-06 09:55:00 -0700528 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700529 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700530 interrupt-controller;
531 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700532 };
533
Simon Glass3c97c4f2016-01-18 19:52:26 -0700534 lcd {
535 u-boot,dm-pre-reloc;
536 compatible = "sandbox,lcd-sdl";
537 xres = <1366>;
538 yres = <768>;
539 };
540
Simon Glass3c43fba2015-07-06 12:54:34 -0600541 leds {
542 compatible = "gpio-leds";
543
544 iracibble {
545 gpios = <&gpio_a 1 0>;
546 label = "sandbox:red";
547 };
548
549 martinet {
550 gpios = <&gpio_a 2 0>;
551 label = "sandbox:green";
552 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200553
554 default_on {
555 gpios = <&gpio_a 5 0>;
556 label = "sandbox:default_on";
557 default-state = "on";
558 };
559
560 default_off {
561 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400562 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200563 default-state = "off";
564 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600565 };
566
Stephen Warren8961b522016-05-16 17:41:37 -0600567 mbox: mbox {
568 compatible = "sandbox,mbox";
569 #mbox-cells = <1>;
570 };
571
572 mbox-test {
573 compatible = "sandbox,mbox-test";
574 mboxes = <&mbox 100>, <&mbox 1>;
575 mbox-names = "other", "test";
576 };
577
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900578 cpus {
Sean Anderson7616e362020-09-28 10:52:23 -0400579 timebase-frequency = <2000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900580 cpu-test1 {
Sean Anderson7616e362020-09-28 10:52:23 -0400581 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900582 compatible = "sandbox,cpu_sandbox";
583 u-boot,dm-pre-reloc;
584 };
Mario Sixfa44b532018-08-06 10:23:44 +0200585
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900586 cpu-test2 {
587 compatible = "sandbox,cpu_sandbox";
588 u-boot,dm-pre-reloc;
589 };
Mario Sixfa44b532018-08-06 10:23:44 +0200590
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900591 cpu-test3 {
592 compatible = "sandbox,cpu_sandbox";
593 u-boot,dm-pre-reloc;
594 };
Mario Sixfa44b532018-08-06 10:23:44 +0200595 };
596
Dave Gerlach21e3c212020-07-15 23:39:58 -0500597 chipid: chipid {
598 compatible = "sandbox,soc";
599 };
600
Simon Glasse96fa6c2018-12-10 10:37:34 -0700601 i2s: i2s {
602 compatible = "sandbox,i2s";
603 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700604 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700605 };
606
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200607 nop-test_0 {
608 compatible = "sandbox,nop_sandbox1";
609 nop-test_1 {
610 compatible = "sandbox,nop_sandbox2";
611 bind = "True";
612 };
613 nop-test_2 {
614 compatible = "sandbox,nop_sandbox2";
615 bind = "False";
616 };
617 };
618
Mario Six004e67c2018-07-31 14:24:14 +0200619 misc-test {
620 compatible = "sandbox,misc_sandbox";
621 };
622
Simon Glasse48eeb92017-04-23 20:02:07 -0600623 mmc2 {
624 compatible = "sandbox,mmc";
625 };
626
627 mmc1 {
628 compatible = "sandbox,mmc";
629 };
630
631 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600632 compatible = "sandbox,mmc";
633 };
634
Simon Glassb45c8332019-02-16 20:24:50 -0700635 pch {
636 compatible = "sandbox,pch";
637 };
638
Tom Rini42c64d12020-02-11 12:41:23 -0500639 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700640 compatible = "sandbox,pci";
641 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500642 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700643 #address-cells = <3>;
644 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600645 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700646 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700647 pci@0,0 {
648 compatible = "pci-generic";
649 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600650 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700651 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300652 pci@1,0 {
653 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600654 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
655 reg = <0x02000814 0 0 0 0
656 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600657 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300658 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700659 p2sb-pci@2,0 {
660 compatible = "sandbox,p2sb";
661 reg = <0x02001010 0 0 0 0>;
662 sandbox,emul = <&p2sb_emul>;
663
664 adder {
665 intel,p2sb-port-id = <3>;
666 compatible = "sandbox,adder";
667 };
668 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700669 pci@1e,0 {
670 compatible = "sandbox,pmc";
671 reg = <0xf000 0 0 0 0>;
672 sandbox,emul = <&pmc_emul1e>;
673 acpi-base = <0x400>;
674 gpe0-dwx-mask = <0xf>;
675 gpe0-dwx-shift-base = <4>;
676 gpe0-dw = <6 7 9>;
677 gpe0-sts = <0x20>;
678 gpe0-en = <0x30>;
679 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700680 pci@1f,0 {
681 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600682 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
683 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600684 sandbox,emul = <&swap_case_emul0_1f>;
685 };
686 };
687
688 pci-emul0 {
689 compatible = "sandbox,pci-emul-parent";
690 swap_case_emul0_0: emul0@0,0 {
691 compatible = "sandbox,swap-case";
692 };
693 swap_case_emul0_1: emul0@1,0 {
694 compatible = "sandbox,swap-case";
695 use-ea;
696 };
697 swap_case_emul0_1f: emul0@1f,0 {
698 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700699 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700700 p2sb_emul: emul@2,0 {
701 compatible = "sandbox,p2sb-emul";
702 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700703 pmc_emul1e: emul@1e,0 {
704 compatible = "sandbox,pmc-emul";
705 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700706 };
707
Tom Rini42c64d12020-02-11 12:41:23 -0500708 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700709 compatible = "sandbox,pci";
710 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500711 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700712 #address-cells = <3>;
713 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700714 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
715 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
716 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700717 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200718 0x0c 0x00 0x1234 0x5678
719 0x10 0x00 0x1234 0x5678>;
720 pci@10,0 {
721 reg = <0x8000 0 0 0 0>;
722 };
Bin Mengdee4d752018-08-03 01:14:41 -0700723 };
724
Tom Rini42c64d12020-02-11 12:41:23 -0500725 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700726 compatible = "sandbox,pci";
727 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500728 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700729 #address-cells = <3>;
730 #size-cells = <2>;
731 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
732 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
733 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
734 pci@1f,0 {
735 compatible = "pci-generic";
736 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600737 sandbox,emul = <&swap_case_emul2_1f>;
738 };
739 };
740
741 pci-emul2 {
742 compatible = "sandbox,pci-emul-parent";
743 swap_case_emul2_1f: emul2@1f,0 {
744 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700745 };
746 };
747
Ramon Friedbb413332019-04-27 11:15:23 +0300748 pci_ep: pci_ep {
749 compatible = "sandbox,pci_ep";
750 };
751
Simon Glass98561572017-04-23 20:10:44 -0600752 probing {
753 compatible = "simple-bus";
754 test1 {
755 compatible = "denx,u-boot-probe-test";
756 };
757
758 test2 {
759 compatible = "denx,u-boot-probe-test";
760 };
761
762 test3 {
763 compatible = "denx,u-boot-probe-test";
764 };
765
766 test4 {
767 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100768 first-syscon = <&syscon0>;
769 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100770 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600771 };
772 };
773
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600774 pwrdom: power-domain {
775 compatible = "sandbox,power-domain";
776 #power-domain-cells = <1>;
777 };
778
779 power-domain-test {
780 compatible = "sandbox,power-domain-test";
781 power-domains = <&pwrdom 2>;
782 };
783
Simon Glass5d9a88f2018-10-01 12:22:40 -0600784 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600785 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600786 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600787 };
788
789 pwm2 {
790 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600791 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600792 };
793
Simon Glass64ce0ca2015-07-06 12:54:31 -0600794 ram {
795 compatible = "sandbox,ram";
796 };
797
Simon Glass5010d982015-07-06 12:54:29 -0600798 reset@0 {
799 compatible = "sandbox,warm-reset";
800 };
801
802 reset@1 {
803 compatible = "sandbox,reset";
804 };
805
Stephen Warren4581b712016-06-17 09:43:59 -0600806 resetc: reset-ctl {
807 compatible = "sandbox,reset-ctl";
808 #reset-cells = <1>;
809 };
810
811 reset-ctl-test {
812 compatible = "sandbox,reset-ctl-test";
813 resets = <&resetc 100>, <&resetc 2>;
814 reset-names = "other", "test";
815 };
816
Sughosh Ganuff0dada2019-12-28 23:58:31 +0530817 rng {
818 compatible = "sandbox,sandbox-rng";
819 };
820
Nishanth Menon52159402015-09-17 15:42:41 -0500821 rproc_1: rproc@1 {
822 compatible = "sandbox,test-processor";
823 remoteproc-name = "remoteproc-test-dev1";
824 };
825
826 rproc_2: rproc@2 {
827 compatible = "sandbox,test-processor";
828 internal-memory-mapped;
829 remoteproc-name = "remoteproc-test-dev2";
830 };
831
Simon Glass5d9a88f2018-10-01 12:22:40 -0600832 panel {
833 compatible = "simple-panel";
834 backlight = <&backlight 0 100>;
835 };
836
Ramon Fried7fd7e2c2018-07-02 02:57:59 +0300837 smem@0 {
838 compatible = "sandbox,smem";
839 };
840
Simon Glassd4901892018-12-10 10:37:36 -0700841 sound {
842 compatible = "sandbox,sound";
843 cpu {
844 sound-dai = <&i2s 0>;
845 };
846
847 codec {
848 sound-dai = <&audio 0>;
849 };
850 };
851
Simon Glass0ae0cb72014-10-13 23:42:11 -0600852 spi@0 {
853 #address-cells = <1>;
854 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600855 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -0600856 compatible = "sandbox,spi";
857 cs-gpios = <0>, <&gpio_a 0>;
858 spi.bin@0 {
859 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000860 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -0600861 spi-max-frequency = <40000000>;
862 sandbox,filename = "spi.bin";
863 };
864 };
865
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100866 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -0600867 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +0200868 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -0600869 };
870
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100871 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -0600872 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -0600873 reg = <0x20 5
874 0x28 6
875 0x30 7
876 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -0600877 };
878
Patrick Delaunaya442e612019-03-07 09:57:13 +0100879 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +0900880 compatible = "simple-mfd", "syscon";
881 reg = <0x40 5
882 0x48 6
883 0x50 7
884 0x58 8>;
885 };
886
Sean Anderson7616e362020-09-28 10:52:23 -0400887 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +0800888 compatible = "sandbox,timer";
889 clock-frequency = <1000000>;
890 };
891
Sean Anderson7616e362020-09-28 10:52:23 -0400892 timer@1 {
893 compatible = "sandbox,timer";
894 sandbox,timebase-frequency-fallback;
895 };
896
Miquel Raynalb91ad162018-05-15 11:57:27 +0200897 tpm2 {
898 compatible = "sandbox,tpm2";
899 };
900
Simon Glass171e9912015-05-22 15:42:15 -0600901 uart0: serial {
902 compatible = "sandbox,serial";
903 u-boot,dm-pre-reloc;
Joe Hershbergerbfacad72015-03-22 17:09:15 -0500904 };
905
Simon Glasse00cb222015-03-25 12:23:05 -0600906 usb_0: usb@0 {
907 compatible = "sandbox,usb";
908 status = "disabled";
909 hub {
910 compatible = "sandbox,usb-hub";
911 #address-cells = <1>;
912 #size-cells = <0>;
913 flash-stick {
914 reg = <0>;
915 compatible = "sandbox,usb-flash";
916 };
917 };
918 };
919
920 usb_1: usb@1 {
921 compatible = "sandbox,usb";
922 hub {
923 compatible = "usb-hub";
924 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +0200925 #address-cells = <1>;
926 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -0600927 hub-emul {
928 compatible = "sandbox,usb-hub";
929 #address-cells = <1>;
930 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -0700931 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -0600932 reg = <0>;
933 compatible = "sandbox,usb-flash";
934 sandbox,filepath = "testflash.bin";
935 };
936
Simon Glass431cbd62015-11-08 23:48:01 -0700937 flash-stick@1 {
938 reg = <1>;
939 compatible = "sandbox,usb-flash";
940 sandbox,filepath = "testflash1.bin";
941 };
942
943 flash-stick@2 {
944 reg = <2>;
945 compatible = "sandbox,usb-flash";
946 sandbox,filepath = "testflash2.bin";
947 };
948
Simon Glassbff1a712015-11-08 23:48:08 -0700949 keyb@3 {
950 reg = <3>;
951 compatible = "sandbox,usb-keyb";
952 };
953
Simon Glasse00cb222015-03-25 12:23:05 -0600954 };
Michael Wallec03b7612020-06-02 01:47:07 +0200955
956 usbstor@1 {
957 reg = <1>;
958 };
959 usbstor@3 {
960 reg = <3>;
961 };
Simon Glasse00cb222015-03-25 12:23:05 -0600962 };
963 };
964
965 usb_2: usb@2 {
966 compatible = "sandbox,usb";
967 status = "disabled";
968 };
969
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200970 spmi: spmi@0 {
971 compatible = "sandbox,spmi";
972 #address-cells = <0x1>;
973 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600974 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200975 pm8916@0 {
976 compatible = "qcom,spmi-pmic";
977 reg = <0x0 0x1>;
978 #address-cells = <0x1>;
979 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -0600980 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +0200981
982 spmi_gpios: gpios@c000 {
983 compatible = "qcom,pm8916-gpio";
984 reg = <0xc000 0x400>;
985 gpio-controller;
986 gpio-count = <4>;
987 #gpio-cells = <2>;
988 gpio-bank-name="spmi";
989 };
990 };
991 };
maxims@google.com0753bc22017-04-17 12:00:21 -0700992
993 wdt0: wdt@0 {
994 compatible = "sandbox,wdt";
995 };
Rob Clarkf2006802018-01-10 11:33:30 +0100996
Mario Six957983e2018-08-09 14:51:19 +0200997 axi: axi@0 {
998 compatible = "sandbox,axi";
999 #address-cells = <0x1>;
1000 #size-cells = <0x1>;
1001 store@0 {
1002 compatible = "sandbox,sandbox_store";
1003 reg = <0x0 0x400>;
1004 };
1005 };
1006
Rob Clarkf2006802018-01-10 11:33:30 +01001007 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001008 #address-cells = <1>;
1009 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001010 setting = "sunrise ohoka";
1011 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001012 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001013 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001014 chosen-test {
1015 compatible = "denx,u-boot-fdt-test";
1016 reg = <9 1>;
1017 };
1018 };
Mario Sixe8d52912018-03-12 14:53:33 +01001019
1020 translation-test@8000 {
1021 compatible = "simple-bus";
1022 reg = <0x8000 0x4000>;
1023
1024 #address-cells = <0x2>;
1025 #size-cells = <0x1>;
1026
1027 ranges = <0 0x0 0x8000 0x1000
1028 1 0x100 0x9000 0x1000
1029 2 0x200 0xA000 0x1000
1030 3 0x300 0xB000 0x1000
1031 >;
1032
Fabien Dessenne641067f2019-05-31 15:11:30 +02001033 dma-ranges = <0 0x000 0x10000000 0x1000
1034 1 0x100 0x20000000 0x1000
1035 >;
1036
Mario Sixe8d52912018-03-12 14:53:33 +01001037 dev@0,0 {
1038 compatible = "denx,u-boot-fdt-dummy";
1039 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001040 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001041 };
1042
1043 dev@1,100 {
1044 compatible = "denx,u-boot-fdt-dummy";
1045 reg = <1 0x100 0x1000>;
1046
1047 };
1048
1049 dev@2,200 {
1050 compatible = "denx,u-boot-fdt-dummy";
1051 reg = <2 0x200 0x1000>;
1052 };
1053
1054
1055 noxlatebus@3,300 {
1056 compatible = "simple-bus";
1057 reg = <3 0x300 0x1000>;
1058
1059 #address-cells = <0x1>;
1060 #size-cells = <0x0>;
1061
1062 dev@42 {
1063 compatible = "denx,u-boot-fdt-dummy";
1064 reg = <0x42>;
1065 };
1066 };
1067 };
Mario Six4eea5312018-09-27 09:19:31 +02001068
1069 osd {
1070 compatible = "sandbox,sandbox_osd";
1071 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001072
Mario Sixe6fd0182018-07-31 11:44:13 +02001073 board {
1074 compatible = "sandbox,board_sandbox";
1075 };
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001076
1077 sandbox_tee {
1078 compatible = "sandbox,tee";
1079 };
Bin Meng4f89d492018-10-15 02:21:26 -07001080
1081 sandbox_virtio1 {
1082 compatible = "sandbox,virtio1";
1083 };
1084
1085 sandbox_virtio2 {
1086 compatible = "sandbox,virtio2";
1087 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001088
Etienne Carriere87d4f272020-09-09 18:44:05 +02001089 sandbox_scmi {
1090 compatible = "sandbox,scmi-devices";
1091 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001092 resets = <&reset_scmi0 3>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001093 };
1094
Patrice Chotardf41a8242018-10-24 14:10:23 +02001095 pinctrl {
1096 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001097
Sean Anderson7f0f1802020-09-14 11:01:57 -04001098 pinctrl-names = "default", "alternate";
1099 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1100 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001101
Sean Anderson7f0f1802020-09-14 11:01:57 -04001102 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001103 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001104 pins = "P5";
1105 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001106 bias-pull-up;
1107 input-disable;
1108 };
1109 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001110 pins = "P6";
1111 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001112 output-high;
1113 drive-open-drain;
1114 };
1115 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001116 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001117 bias-pull-down;
1118 input-enable;
1119 };
1120 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001121 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001122 bias-disable;
1123 };
1124 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001125
1126 pinctrl_i2c: i2c {
1127 groups {
1128 groups = "I2C_UART";
1129 function = "I2C";
1130 };
1131
1132 pins {
1133 pins = "P0", "P1";
1134 drive-open-drain;
1135 };
1136 };
1137
1138 pinctrl_i2s: i2s {
1139 groups = "SPI_I2S";
1140 function = "I2S";
1141 };
1142
1143 pinctrl_spi: spi {
1144 groups = "SPI_I2S";
1145 function = "SPI";
1146
1147 cs {
1148 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1149 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1150 };
1151 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001152 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001153
1154 hwspinlock@0 {
1155 compatible = "sandbox,hwspinlock";
1156 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001157
1158 dma: dma {
1159 compatible = "sandbox,dma";
1160 #dma-cells = <1>;
1161
1162 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1163 dma-names = "m2m", "tx0", "rx0";
1164 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001165
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001166 /*
1167 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1168 * end of the test. If parent mdio is removed first, clean-up of the
1169 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1170 * active at the end of the test. That it turn doesn't allow the mdio
1171 * class to be destroyed, triggering an error.
1172 */
1173 mdio-mux-test {
1174 compatible = "sandbox,mdio-mux";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 mdio-parent-bus = <&mdio>;
1178
1179 mdio-ch-test@0 {
1180 reg = <0>;
1181 };
1182 mdio-ch-test@1 {
1183 reg = <1>;
1184 };
1185 };
1186
1187 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001188 compatible = "sandbox,mdio";
1189 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001190
1191 pm-bus-test {
1192 compatible = "simple-pm-bus";
1193 clocks = <&clk_sandbox 4>;
1194 power-domains = <&pwrdom 1>;
1195 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001196
1197 resetc2: syscon-reset {
1198 compatible = "syscon-reset";
1199 #reset-cells = <1>;
1200 regmap = <&syscon0>;
1201 offset = <1>;
1202 mask = <0x27FFFFFF>;
1203 assert-high = <0>;
1204 };
1205
1206 syscon-reset-test {
1207 compatible = "sandbox,misc_sandbox";
1208 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1209 reset-names = "valid", "no_mask", "out_of_range";
1210 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301211
1212 some_regmapped-bus {
1213 #address-cells = <0x1>;
1214 #size-cells = <0x1>;
1215
1216 ranges = <0x0 0x0 0x10>;
1217 compatible = "simple-bus";
1218
1219 regmap-test_0 {
1220 reg = <0 0x10>;
1221 compatible = "sandbox,regmap_test";
1222 };
1223 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001224};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001225
1226#include "sandbox_pmic.dtsi"