Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 1 | if ARCH_SUNXI |
| 2 | |
Siva Durga Prasad Paladugu | a4d8892 | 2016-07-29 15:31:47 +0530 | [diff] [blame] | 3 | config IDENT_STRING |
| 4 | default " Allwinner Technology" |
| 5 | |
Alexandru Gagniuc | 0dcf18c | 2017-04-04 10:02:58 -0700 | [diff] [blame] | 6 | # FIXME: Should not redefine these Kconfig symbols |
Simon Glass | 8f92558 | 2016-10-17 20:12:36 -0600 | [diff] [blame] | 7 | config PRE_CONSOLE_BUFFER |
| 8 | default y |
| 9 | |
Simon Glass | 53b5bf3 | 2016-09-12 23:18:39 -0600 | [diff] [blame] | 10 | config SPL_GPIO_SUPPORT |
| 11 | default y |
| 12 | |
Simon Glass | 77d2f7f | 2016-09-12 23:18:41 -0600 | [diff] [blame] | 13 | config SPL_LIBCOMMON_SUPPORT |
| 14 | default y |
| 15 | |
Simon Glass | 1646eba | 2016-09-12 23:18:42 -0600 | [diff] [blame] | 16 | config SPL_LIBDISK_SUPPORT |
| 17 | default y |
| 18 | |
Simon Glass | cc4288e | 2016-09-12 23:18:43 -0600 | [diff] [blame] | 19 | config SPL_LIBGENERIC_SUPPORT |
| 20 | default y |
| 21 | |
Simon Glass | 1fdf7c6 | 2016-09-12 23:18:44 -0600 | [diff] [blame] | 22 | config SPL_MMC_SUPPORT |
Alexandru Gagniuc | 0dcf18c | 2017-04-04 10:02:58 -0700 | [diff] [blame] | 23 | depends on SPL && GENERIC_MMC |
Simon Glass | 1fdf7c6 | 2016-09-12 23:18:44 -0600 | [diff] [blame] | 24 | default y |
| 25 | |
Simon Glass | 2253797 | 2016-09-12 23:18:54 -0600 | [diff] [blame] | 26 | config SPL_POWER_SUPPORT |
| 27 | default y |
| 28 | |
Simon Glass | e00f76c | 2016-09-12 23:18:56 -0600 | [diff] [blame] | 29 | config SPL_SERIAL_SUPPORT |
| 30 | default y |
| 31 | |
Andre Przywara | bc613d8 | 2017-02-16 01:20:23 +0000 | [diff] [blame] | 32 | config SUNXI_HIGH_SRAM |
| 33 | bool |
| 34 | default n |
| 35 | ---help--- |
| 36 | Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, |
| 37 | with the first SRAM region being located at address 0. |
| 38 | Some newer SoCs map the boot ROM at address 0 instead and move the |
| 39 | SRAM to 64KB, just behind the mask ROM. |
| 40 | Chips using the latter setup are supposed to select this option to |
| 41 | adjust the addresses accordingly. |
| 42 | |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 43 | # Note only one of these may be selected at a time! But hidden choices are |
| 44 | # not supported by Kconfig |
| 45 | config SUNXI_GEN_SUN4I |
| 46 | bool |
| 47 | ---help--- |
| 48 | Select this for sunxi SoCs which have resets and clocks set up |
| 49 | as the original A10 (mach-sun4i). |
| 50 | |
| 51 | config SUNXI_GEN_SUN6I |
| 52 | bool |
| 53 | ---help--- |
| 54 | Select this for sunxi SoCs which have sun6i like periphery, like |
| 55 | separate ahb reset control registers, custom pmic bus, new style |
| 56 | watchdog, etc. |
| 57 | |
| 58 | |
Andre Przywara | 7b82a22 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 59 | config MACH_SUNXI_H3_H5 |
| 60 | bool |
Jernej Skrabec | 1ae5def | 2017-03-27 19:22:31 +0200 | [diff] [blame^] | 61 | select SUNXI_DE2 |
Andre Przywara | 7b82a22 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 62 | select SUNXI_GEN_SUN6I |
| 63 | select SUPPORT_SPL |
| 64 | |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 65 | choice |
| 66 | prompt "Sunxi SoC Variant" |
Hans de Goede | 3da9536 | 2016-06-12 11:57:07 +0200 | [diff] [blame] | 67 | optional |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 68 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 69 | config MACH_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 70 | bool "sun4i (Allwinner A10)" |
| 71 | select CPU_V7 |
Andre Przywara | 85db583 | 2017-02-16 01:20:21 +0000 | [diff] [blame] | 72 | select ARM_CORTEX_CPU_IS_UP |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 73 | select SUNXI_GEN_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 74 | select SUPPORT_SPL |
| 75 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 76 | config MACH_SUN5I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 77 | bool "sun5i (Allwinner A13)" |
| 78 | select CPU_V7 |
Andre Przywara | 85db583 | 2017-02-16 01:20:21 +0000 | [diff] [blame] | 79 | select ARM_CORTEX_CPU_IS_UP |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 80 | select SUNXI_GEN_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 81 | select SUPPORT_SPL |
| 82 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 83 | config MACH_SUN6I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 84 | bool "sun6i (Allwinner A31)" |
| 85 | select CPU_V7 |
Chen-Yu Tsai | cc08ea4 | 2015-05-28 21:25:32 +0800 | [diff] [blame] | 86 | select CPU_V7_HAS_NONSEC |
| 87 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | 217f92b | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 88 | select ARCH_SUPPORT_PSCI |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 89 | select SUNXI_GEN_SUN6I |
Hans de Goede | 8c2c9cf | 2014-10-25 20:18:10 +0200 | [diff] [blame] | 90 | select SUPPORT_SPL |
Chen-Yu Tsai | cc08ea4 | 2015-05-28 21:25:32 +0800 | [diff] [blame] | 91 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 92 | |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 93 | config MACH_SUN7I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 94 | bool "sun7i (Allwinner A20)" |
| 95 | select CPU_V7 |
Hans de Goede | ea624e1 | 2014-11-14 09:34:30 +0100 | [diff] [blame] | 96 | select CPU_V7_HAS_NONSEC |
| 97 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | 217f92b | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 98 | select ARCH_SUPPORT_PSCI |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 99 | select SUNXI_GEN_SUN4I |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 100 | select SUPPORT_SPL |
Hans de Goede | b366fb9 | 2014-10-24 20:12:04 +0200 | [diff] [blame] | 101 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 102 | |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 103 | config MACH_SUN8I_A23 |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 104 | bool "sun8i (Allwinner A23)" |
| 105 | select CPU_V7 |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 106 | select CPU_V7_HAS_NONSEC |
| 107 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | 217f92b | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 108 | select ARCH_SUPPORT_PSCI |
Hans de Goede | 44d8ae5 | 2015-04-06 20:33:34 +0200 | [diff] [blame] | 109 | select SUNXI_GEN_SUN6I |
Hans de Goede | 08fd147 | 2014-12-07 14:34:27 +0100 | [diff] [blame] | 110 | select SUPPORT_SPL |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 111 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 112 | |
Vishnu Patekar | 8c3dacf | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 113 | config MACH_SUN8I_A33 |
| 114 | bool "sun8i (Allwinner A33)" |
| 115 | select CPU_V7 |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 116 | select CPU_V7_HAS_NONSEC |
| 117 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | 217f92b | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 118 | select ARCH_SUPPORT_PSCI |
Vishnu Patekar | 8c3dacf | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 119 | select SUNXI_GEN_SUN6I |
| 120 | select SUPPORT_SPL |
Chen-Yu Tsai | 014414f | 2015-05-28 21:25:34 +0800 | [diff] [blame] | 121 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Vishnu Patekar | 8c3dacf | 2015-03-01 23:47:48 +0530 | [diff] [blame] | 122 | |
Chen-Yu Tsai | a81b799 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 123 | config MACH_SUN8I_A83T |
| 124 | bool "sun8i (Allwinner A83T)" |
| 125 | select CPU_V7 |
| 126 | select SUNXI_GEN_SUN6I |
| 127 | select SUPPORT_SPL |
| 128 | |
Jens Kuske | 1c27b7d | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 129 | config MACH_SUN8I_H3 |
| 130 | bool "sun8i (Allwinner H3)" |
| 131 | select CPU_V7 |
Chen-Yu Tsai | 853f6d1 | 2016-01-06 15:13:09 +0800 | [diff] [blame] | 132 | select CPU_V7_HAS_NONSEC |
| 133 | select CPU_V7_HAS_VIRT |
Masahiro Yamada | 217f92b | 2016-08-30 16:22:22 +0900 | [diff] [blame] | 134 | select ARCH_SUPPORT_PSCI |
Andre Przywara | 7b82a22 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 135 | select MACH_SUNXI_H3_H5 |
Chen-Yu Tsai | 853f6d1 | 2016-01-06 15:13:09 +0800 | [diff] [blame] | 136 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
Jens Kuske | 1c27b7d | 2015-11-17 15:12:58 +0100 | [diff] [blame] | 137 | |
Chen-Yu Tsai | 379feba | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 138 | config MACH_SUN8I_R40 |
| 139 | bool "sun8i (Allwinner R40)" |
| 140 | select CPU_V7 |
Chen-Yu Tsai | 0918648 | 2017-03-01 11:03:15 +0800 | [diff] [blame] | 141 | select CPU_V7_HAS_NONSEC |
| 142 | select CPU_V7_HAS_VIRT |
| 143 | select ARCH_SUPPORT_PSCI |
Chen-Yu Tsai | 379feba | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 144 | select SUNXI_GEN_SUN6I |
Chen-Yu Tsai | 50ae7ae | 2016-12-02 16:09:49 +0800 | [diff] [blame] | 145 | select SUPPORT_SPL |
Chen-Yu Tsai | 379feba | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 146 | |
Hans de Goede | 1871a8c | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 147 | config MACH_SUN9I |
| 148 | bool "sun9i (Allwinner A80)" |
| 149 | select CPU_V7 |
Andre Przywara | bc613d8 | 2017-02-16 01:20:23 +0000 | [diff] [blame] | 150 | select SUNXI_HIGH_SRAM |
Hans de Goede | 1871a8c | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 151 | select SUNXI_GEN_SUN6I |
Philipp Tomsich | a98c296 | 2016-10-28 18:21:32 +0800 | [diff] [blame] | 152 | select SUPPORT_SPL |
Hans de Goede | 1871a8c | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 153 | |
Chen-Yu Tsai | a81b799 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 154 | config MACH_SUN50I |
| 155 | bool "sun50i (Allwinner A64)" |
| 156 | select ARM64 |
Jernej Skrabec | 1ae5def | 2017-03-27 19:22:31 +0200 | [diff] [blame^] | 157 | select SUNXI_DE2 |
Chen-Yu Tsai | a81b799 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 158 | select SUNXI_GEN_SUN6I |
Andre Przywara | bc613d8 | 2017-02-16 01:20:23 +0000 | [diff] [blame] | 159 | select SUNXI_HIGH_SRAM |
Andre Przywara | eb77f5c | 2017-01-02 11:48:45 +0000 | [diff] [blame] | 160 | select SUPPORT_SPL |
Chen-Yu Tsai | a81b799 | 2016-05-02 10:28:07 +0800 | [diff] [blame] | 161 | |
Andre Przywara | 997bde6 | 2017-02-16 01:20:28 +0000 | [diff] [blame] | 162 | config MACH_SUN50I_H5 |
| 163 | bool "sun50i (Allwinner H5)" |
| 164 | select ARM64 |
| 165 | select MACH_SUNXI_H3_H5 |
| 166 | select SUNXI_HIGH_SRAM |
| 167 | |
Ian Campbell | 2c7e3b9 | 2014-10-24 21:20:44 +0100 | [diff] [blame] | 168 | endchoice |
Maxime Ripard | 8a6564d | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 169 | |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 170 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
| 171 | config MACH_SUN8I |
| 172 | bool |
Chen-Yu Tsai | 301791c | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 173 | default y if MACH_SUN8I_A23 |
| 174 | default y if MACH_SUN8I_A33 |
| 175 | default y if MACH_SUN8I_A83T |
| 176 | default y if MACH_SUNXI_H3_H5 |
Chen-Yu Tsai | 379feba | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 177 | default y if MACH_SUN8I_R40 |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 178 | |
Andre Przywara | b5402d1 | 2017-01-02 11:48:35 +0000 | [diff] [blame] | 179 | config RESERVE_ALLWINNER_BOOT0_HEADER |
| 180 | bool "reserve space for Allwinner boot0 header" |
| 181 | select ENABLE_ARM_SOC_BOOT0_HOOK |
| 182 | ---help--- |
| 183 | Prepend a 1536 byte (empty) header to the U-Boot image file, to be |
| 184 | filled with magic values post build. The Allwinner provided boot0 |
| 185 | blob relies on this information to load and execute U-Boot. |
| 186 | Only needed on 64-bit Allwinner boards so far when using boot0. |
| 187 | |
Andre Przywara | 83843c9 | 2017-01-02 11:48:36 +0000 | [diff] [blame] | 188 | config ARM_BOOT_HOOK_RMR |
| 189 | bool |
| 190 | depends on ARM64 |
| 191 | default y |
| 192 | select ENABLE_ARM_SOC_BOOT0_HOOK |
| 193 | ---help--- |
| 194 | Insert some ARM32 code at the very beginning of the U-Boot binary |
| 195 | which uses an RMR register write to bring the core into AArch64 mode. |
| 196 | The very first instruction acts as a switch, since it's carefully |
| 197 | chosen to be a NOP in one mode and a branch in the other, so the |
| 198 | code would only be executed if not already in AArch64. |
| 199 | This allows both the SPL and the U-Boot proper to be entered in |
| 200 | either mode and switch to AArch64 if needed. |
| 201 | |
Vishnu Patekar | f5fd8ca | 2016-01-12 01:20:58 +0800 | [diff] [blame] | 202 | config DRAM_TYPE |
| 203 | int "sunxi dram type" |
| 204 | depends on MACH_SUN8I_A83T |
| 205 | default 3 |
| 206 | ---help--- |
| 207 | Set the dram type, 3: DDR3, 7: LPDDR3 |
Hans de Goede | 5e6bacd | 2015-04-06 20:55:39 +0200 | [diff] [blame] | 208 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 209 | config DRAM_CLK |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 210 | int "sunxi dram clock speed" |
Philipp Tomsich | 297bb9e | 2016-10-28 18:21:28 +0800 | [diff] [blame] | 211 | default 792 if MACH_SUN9I |
Chen-Yu Tsai | fab03e3 | 2016-11-30 16:58:35 +0800 | [diff] [blame] | 212 | default 648 if MACH_SUN8I_R40 |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 213 | default 312 if MACH_SUN6I || MACH_SUN8I |
| 214 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
Andre Przywara | 52e3182 | 2017-01-02 11:48:37 +0000 | [diff] [blame] | 215 | default 672 if MACH_SUN50I |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 216 | ---help--- |
Philipp Tomsich | 297bb9e | 2016-10-28 18:21:28 +0800 | [diff] [blame] | 217 | Set the dram clock speed, valid range 240 - 480 (prior to sun9i), |
| 218 | must be a multiple of 24. For the sun9i (A80), the tested values |
| 219 | (for DDR3-1600) are 312 to 792. |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 220 | |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 221 | if MACH_SUN5I || MACH_SUN7I |
| 222 | config DRAM_MBUS_CLK |
| 223 | int "sunxi mbus clock speed" |
| 224 | default 300 |
| 225 | ---help--- |
| 226 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. |
| 227 | |
| 228 | endif |
| 229 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 230 | config DRAM_ZQ |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 231 | int "sunxi dram zq value" |
| 232 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I |
| 233 | default 127 if MACH_SUN7I |
Chen-Yu Tsai | fab03e3 | 2016-11-30 16:58:35 +0800 | [diff] [blame] | 234 | default 3881979 if MACH_SUN8I_R40 |
Chen-Yu Tsai | 58b628e | 2016-10-28 18:21:36 +0800 | [diff] [blame] | 235 | default 4145117 if MACH_SUN9I |
Andre Przywara | 52e3182 | 2017-01-02 11:48:37 +0000 | [diff] [blame] | 236 | default 3881915 if MACH_SUN50I |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 237 | ---help--- |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 238 | Set the dram zq value. |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 239 | |
Hans de Goede | 8975cdf | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 240 | config DRAM_ODT_EN |
| 241 | bool "sunxi dram odt enable" |
| 242 | default n if !MACH_SUN8I_A23 |
| 243 | default y if MACH_SUN8I_A23 |
Chen-Yu Tsai | fab03e3 | 2016-11-30 16:58:35 +0800 | [diff] [blame] | 244 | default y if MACH_SUN8I_R40 |
Andre Przywara | eb77f5c | 2017-01-02 11:48:45 +0000 | [diff] [blame] | 245 | default y if MACH_SUN50I |
Hans de Goede | 8975cdf | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 246 | ---help--- |
| 247 | Select this to enable dram odt (on die termination). |
| 248 | |
Hans de Goede | 8ffc487 | 2015-01-17 14:24:55 +0100 | [diff] [blame] | 249 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
| 250 | config DRAM_EMR1 |
| 251 | int "sunxi dram emr1 value" |
| 252 | default 0 if MACH_SUN4I |
| 253 | default 4 if MACH_SUN5I || MACH_SUN7I |
| 254 | ---help--- |
Hans de Goede | e1a0888 | 2015-01-25 11:29:27 +0100 | [diff] [blame] | 255 | Set the dram controller emr1 value. |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 256 | |
Siarhei Siamashka | 47e3501 | 2015-02-01 00:27:06 +0200 | [diff] [blame] | 257 | config DRAM_TPR3 |
| 258 | hex "sunxi dram tpr3 value" |
| 259 | default 0 |
| 260 | ---help--- |
| 261 | Set the dram controller tpr3 parameter. This parameter configures |
| 262 | the delay on the command lane and also phase shifts, which are |
| 263 | applied for sampling incoming read data. The default value 0 |
| 264 | means that no phase/delay adjustments are necessary. Properly |
| 265 | configuring this parameter increases reliability at high DRAM |
| 266 | clock speeds. |
| 267 | |
| 268 | config DRAM_DQS_GATING_DELAY |
| 269 | hex "sunxi dram dqs_gating_delay value" |
| 270 | default 0 |
| 271 | ---help--- |
| 272 | Set the dram controller dqs_gating_delay parmeter. Each byte |
| 273 | encodes the DQS gating delay for each byte lane. The delay |
| 274 | granularity is 1/4 cycle. For example, the value 0x05060606 |
| 275 | means that the delay is 5 quarter-cycles for one lane (1.25 |
| 276 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. |
| 277 | The default value 0 means autodetection. The results of hardware |
| 278 | autodetection are not very reliable and depend on the chip |
| 279 | temperature (sometimes producing different results on cold start |
| 280 | and warm reboot). But the accuracy of hardware autodetection |
| 281 | is usually good enough, unless running at really high DRAM |
| 282 | clocks speeds (up to 600MHz). If unsure, keep as 0. |
| 283 | |
Siarhei Siamashka | d133647 | 2015-02-01 00:27:05 +0200 | [diff] [blame] | 284 | choice |
| 285 | prompt "sunxi dram timings" |
| 286 | default DRAM_TIMINGS_VENDOR_MAGIC |
| 287 | ---help--- |
| 288 | Select the timings of the DDR3 chips. |
| 289 | |
| 290 | config DRAM_TIMINGS_VENDOR_MAGIC |
| 291 | bool "Magic vendor timings from Android" |
| 292 | ---help--- |
| 293 | The same DRAM timings as in the Allwinner boot0 bootloader. |
| 294 | |
| 295 | config DRAM_TIMINGS_DDR3_1066F_1333H |
| 296 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" |
| 297 | ---help--- |
| 298 | Use the timings of the standard JEDEC DDR3-1066F speed bin for |
| 299 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin |
| 300 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips |
| 301 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 |
| 302 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm |
| 303 | that down binning to DDR3-1066F is supported (because DDR3-1066F |
| 304 | uses a bit faster timings than DDR3-1333H). |
| 305 | |
| 306 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J |
| 307 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" |
| 308 | ---help--- |
| 309 | Use the timings of the slowest possible JEDEC speed bin for the |
| 310 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be |
| 311 | DDR3-800E, DDR3-1066G or DDR3-1333J. |
| 312 | |
| 313 | endchoice |
| 314 | |
Hans de Goede | 37781a1 | 2014-11-15 19:46:39 +0100 | [diff] [blame] | 315 | endif |
| 316 | |
Hans de Goede | 8975cdf | 2015-05-13 15:00:46 +0200 | [diff] [blame] | 317 | if MACH_SUN8I_A23 |
| 318 | config DRAM_ODT_CORRECTION |
| 319 | int "sunxi dram odt correction value" |
| 320 | default 0 |
| 321 | ---help--- |
| 322 | Set the dram odt correction value (range -255 - 255). In allwinner |
| 323 | fex files, this option is found in bits 8-15 of the u32 odt_en variable |
| 324 | in the [dram] section. When bit 31 of the odt_en variable is set |
| 325 | then the correction is negative. Usually the value for this is 0. |
| 326 | endif |
| 327 | |
Iain Paton | e71b422 | 2015-03-28 10:26:38 +0000 | [diff] [blame] | 328 | config SYS_CLK_FREQ |
Chen-Yu Tsai | 301791c | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 329 | default 1008000000 if MACH_SUN4I |
| 330 | default 1008000000 if MACH_SUN5I |
| 331 | default 1008000000 if MACH_SUN6I |
Iain Paton | e71b422 | 2015-03-28 10:26:38 +0000 | [diff] [blame] | 332 | default 912000000 if MACH_SUN7I |
Chen-Yu Tsai | 301791c | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 333 | default 1008000000 if MACH_SUN8I |
| 334 | default 1008000000 if MACH_SUN9I |
| 335 | default 816000000 if MACH_SUN50I |
Iain Paton | e71b422 | 2015-03-28 10:26:38 +0000 | [diff] [blame] | 336 | |
Maxime Ripard | 8a6564d | 2014-10-03 20:16:29 +0800 | [diff] [blame] | 337 | config SYS_CONFIG_NAME |
Ian Campbell | c3be279 | 2014-10-24 21:20:45 +0100 | [diff] [blame] | 338 | default "sun4i" if MACH_SUN4I |
| 339 | default "sun5i" if MACH_SUN5I |
| 340 | default "sun6i" if MACH_SUN6I |
| 341 | default "sun7i" if MACH_SUN7I |
| 342 | default "sun8i" if MACH_SUN8I |
Hans de Goede | 1871a8c | 2015-01-13 19:25:06 +0100 | [diff] [blame] | 343 | default "sun9i" if MACH_SUN9I |
Siarhei Siamashka | d96ebc4 | 2016-03-29 17:29:10 +0200 | [diff] [blame] | 344 | default "sun50i" if MACH_SUN50I |
Hans de Goede | 6ae66f2 | 2014-08-01 09:28:24 +0200 | [diff] [blame] | 345 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 346 | config SYS_BOARD |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 347 | default "sunxi" |
| 348 | |
| 349 | config SYS_SOC |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 350 | default "sunxi" |
| 351 | |
Siarhei Siamashka | f0ce28e | 2014-12-25 02:34:47 +0200 | [diff] [blame] | 352 | config UART0_PORT_F |
| 353 | bool "UART0 on MicroSD breakout board" |
Siarhei Siamashka | f0ce28e | 2014-12-25 02:34:47 +0200 | [diff] [blame] | 354 | default n |
| 355 | ---help--- |
| 356 | Repurpose the SD card slot for getting access to the UART0 serial |
| 357 | console. Primarily useful only for low level u-boot debugging on |
| 358 | tablets, where normal UART0 is difficult to access and requires |
| 359 | device disassembly and/or soldering. As the SD card can't be used |
| 360 | at the same time, the system can be only booted in the FEL mode. |
| 361 | Only enable this if you really know what you are doing. |
| 362 | |
Hans de Goede | accc9e4 | 2014-10-22 14:56:36 +0200 | [diff] [blame] | 363 | config OLD_SUNXI_KERNEL_COMPAT |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 364 | bool "Enable workarounds for booting old kernels" |
Hans de Goede | accc9e4 | 2014-10-22 14:56:36 +0200 | [diff] [blame] | 365 | default n |
| 366 | ---help--- |
| 367 | Set this to enable various workarounds for old kernels, this results in |
| 368 | sub-optimal settings for newer kernels, only enable if needed. |
| 369 | |
Mylène Josserand | f5fd788 | 2017-04-02 12:59:10 +0200 | [diff] [blame] | 370 | config MACPWR |
| 371 | string "MAC power pin" |
| 372 | default "" |
| 373 | help |
| 374 | Set the pin used to power the MAC. This takes a string in the format |
| 375 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 376 | |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 377 | config MMC0_CD_PIN |
| 378 | string "Card detect pin for mmc0" |
Andre Przywara | 7b82a22 | 2017-02-16 01:20:27 +0000 | [diff] [blame] | 379 | default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I |
Hans de Goede | cd82113 | 2014-10-02 20:29:26 +0200 | [diff] [blame] | 380 | default "" |
| 381 | ---help--- |
| 382 | Set the card detect pin for mmc0, leave empty to not use cd. This |
| 383 | takes a string in the format understood by sunxi_name_to_gpio, e.g. |
| 384 | PH1 for pin 1 of port H. |
| 385 | |
| 386 | config MMC1_CD_PIN |
| 387 | string "Card detect pin for mmc1" |
| 388 | default "" |
| 389 | ---help--- |
| 390 | See MMC0_CD_PIN help text. |
| 391 | |
| 392 | config MMC2_CD_PIN |
| 393 | string "Card detect pin for mmc2" |
| 394 | default "" |
| 395 | ---help--- |
| 396 | See MMC0_CD_PIN help text. |
| 397 | |
| 398 | config MMC3_CD_PIN |
| 399 | string "Card detect pin for mmc3" |
| 400 | default "" |
| 401 | ---help--- |
| 402 | See MMC0_CD_PIN help text. |
| 403 | |
Paul Kocialkowski | 8deacca | 2015-03-22 18:12:23 +0100 | [diff] [blame] | 404 | config MMC1_PINS |
| 405 | string "Pins for mmc1" |
| 406 | default "" |
| 407 | ---help--- |
| 408 | Set the pins used for mmc1, when applicable. This takes a string in the |
| 409 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. |
| 410 | |
| 411 | config MMC2_PINS |
| 412 | string "Pins for mmc2" |
| 413 | default "" |
| 414 | ---help--- |
| 415 | See MMC1_PINS help text. |
| 416 | |
| 417 | config MMC3_PINS |
| 418 | string "Pins for mmc3" |
| 419 | default "" |
| 420 | ---help--- |
| 421 | See MMC1_PINS help text. |
| 422 | |
Hans de Goede | 2ccfac0 | 2014-10-02 20:43:50 +0200 | [diff] [blame] | 423 | config MMC_SUNXI_SLOT_EXTRA |
| 424 | int "mmc extra slot number" |
| 425 | default -1 |
| 426 | ---help--- |
| 427 | sunxi builds always enable mmc0, some boards also have a second sdcard |
| 428 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable |
| 429 | support for this. |
| 430 | |
Hans de Goede | 2c3c3ec | 2016-04-01 22:39:26 +0200 | [diff] [blame] | 431 | config INITIAL_USB_SCAN_DELAY |
| 432 | int "delay initial usb scan by x ms to allow builtin devices to init" |
| 433 | default 0 |
| 434 | ---help--- |
| 435 | Some boards have on board usb devices which need longer than the |
| 436 | USB spec's 1 second to connect from board powerup. Set this config |
| 437 | option to a non 0 value to add an extra delay before the first usb |
| 438 | bus scan. |
| 439 | |
Hans de Goede | 4458b7a | 2015-01-07 15:26:06 +0100 | [diff] [blame] | 440 | config USB0_VBUS_PIN |
| 441 | string "Vbus enable pin for usb0 (otg)" |
| 442 | default "" |
| 443 | ---help--- |
| 444 | Set the Vbus enable pin for usb0 (otg). This takes a string in the |
| 445 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 446 | |
Hans de Goede | 52defe8 | 2015-02-16 22:13:43 +0100 | [diff] [blame] | 447 | config USB0_VBUS_DET |
| 448 | string "Vbus detect pin for usb0 (otg)" |
Hans de Goede | 52defe8 | 2015-02-16 22:13:43 +0100 | [diff] [blame] | 449 | default "" |
| 450 | ---help--- |
| 451 | Set the Vbus detect pin for usb0 (otg). This takes a string in the |
| 452 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 453 | |
Hans de Goede | 48c06c9 | 2015-06-14 17:29:53 +0200 | [diff] [blame] | 454 | config USB0_ID_DET |
| 455 | string "ID detect pin for usb0 (otg)" |
| 456 | default "" |
| 457 | ---help--- |
| 458 | Set the ID detect pin for usb0 (otg). This takes a string in the |
| 459 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 460 | |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 461 | config USB1_VBUS_PIN |
| 462 | string "Vbus enable pin for usb1 (ehci0)" |
| 463 | default "PH6" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | 76946df | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 464 | default "PH27" if MACH_SUN6I |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 465 | ---help--- |
| 466 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes |
| 467 | a string in the format understood by sunxi_name_to_gpio, e.g. |
| 468 | PH1 for pin 1 of port H. |
| 469 | |
| 470 | config USB2_VBUS_PIN |
| 471 | string "Vbus enable pin for usb2 (ehci1)" |
| 472 | default "PH3" if MACH_SUN4I || MACH_SUN7I |
Hans de Goede | 76946df | 2014-11-07 14:51:12 +0100 | [diff] [blame] | 473 | default "PH24" if MACH_SUN6I |
Hans de Goede | 115200c | 2014-11-07 16:09:00 +0100 | [diff] [blame] | 474 | ---help--- |
| 475 | See USB1_VBUS_PIN help text. |
| 476 | |
Hans de Goede | 60fa630 | 2016-03-18 08:42:01 +0100 | [diff] [blame] | 477 | config USB3_VBUS_PIN |
| 478 | string "Vbus enable pin for usb3 (ehci2)" |
| 479 | default "" |
| 480 | ---help--- |
| 481 | See USB1_VBUS_PIN help text. |
| 482 | |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 483 | config I2C0_ENABLE |
| 484 | bool "Enable I2C/TWI controller 0" |
Chen-Yu Tsai | 409677e | 2016-11-30 15:30:30 +0800 | [diff] [blame] | 485 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 486 | default n if MACH_SUN6I || MACH_SUN8I |
Hans de Goede | 0878a8a | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 487 | select CMD_I2C |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 488 | ---help--- |
| 489 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling |
| 490 | its clock and setting up the bus. This is especially useful on devices |
| 491 | with slaves connected to the bus or with pins exposed through e.g. an |
| 492 | expansion port/header. |
| 493 | |
| 494 | config I2C1_ENABLE |
| 495 | bool "Enable I2C/TWI controller 1" |
| 496 | default n |
Hans de Goede | 0878a8a | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 497 | select CMD_I2C |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 498 | ---help--- |
| 499 | See I2C0_ENABLE help text. |
| 500 | |
| 501 | config I2C2_ENABLE |
| 502 | bool "Enable I2C/TWI controller 2" |
| 503 | default n |
Hans de Goede | 0878a8a | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 504 | select CMD_I2C |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 505 | ---help--- |
| 506 | See I2C0_ENABLE help text. |
| 507 | |
| 508 | if MACH_SUN6I || MACH_SUN7I |
| 509 | config I2C3_ENABLE |
| 510 | bool "Enable I2C/TWI controller 3" |
| 511 | default n |
Hans de Goede | 0878a8a | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 512 | select CMD_I2C |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 513 | ---help--- |
| 514 | See I2C0_ENABLE help text. |
| 515 | endif |
| 516 | |
Jelle van der Waa | 0d8382a | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 517 | if SUNXI_GEN_SUN6I |
Jelle van der Waa | 9d08268 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 518 | config R_I2C_ENABLE |
| 519 | bool "Enable the PRCM I2C/TWI controller" |
Jelle van der Waa | 0d8382a | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 520 | # This is used for the pmic on H3 |
| 521 | default y if SY8106A_POWER |
Hans de Goede | 0878a8a | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 522 | select CMD_I2C |
Jelle van der Waa | 9d08268 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 523 | ---help--- |
| 524 | Set this to y to enable the I2C controller which is part of the PRCM. |
Jelle van der Waa | 0d8382a | 2016-02-23 18:47:19 +0100 | [diff] [blame] | 525 | endif |
Jelle van der Waa | 9d08268 | 2016-01-14 14:06:26 +0100 | [diff] [blame] | 526 | |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 527 | if MACH_SUN7I |
| 528 | config I2C4_ENABLE |
| 529 | bool "Enable I2C/TWI controller 4" |
| 530 | default n |
Hans de Goede | 0878a8a | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 531 | select CMD_I2C |
Paul Kocialkowski | 6c739c5 | 2015-04-10 23:09:52 +0200 | [diff] [blame] | 532 | ---help--- |
| 533 | See I2C0_ENABLE help text. |
| 534 | endif |
| 535 | |
Hans de Goede | 2fcf033 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 536 | config AXP_GPIO |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 537 | bool "Enable support for gpio-s on axp PMICs" |
Hans de Goede | 2fcf033 | 2015-04-25 17:25:14 +0200 | [diff] [blame] | 538 | default n |
| 539 | ---help--- |
| 540 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. |
| 541 | |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 542 | config VIDEO |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 543 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
Chen-Yu Tsai | 301791c | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 544 | depends on !MACH_SUN8I_A83T |
| 545 | depends on !MACH_SUNXI_H3_H5 |
Chen-Yu Tsai | 379feba | 2016-11-30 14:57:32 +0800 | [diff] [blame] | 546 | depends on !MACH_SUN8I_R40 |
Chen-Yu Tsai | 301791c | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 547 | depends on !MACH_SUN9I |
| 548 | depends on !MACH_SUN50I |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 549 | default y |
| 550 | ---help--- |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 551 | Say Y here to add support for using a cfb console on the HDMI, LCD |
| 552 | or VGA output found on most sunxi devices. See doc/README.video for |
| 553 | info on how to select the video output and mode. |
| 554 | |
Hans de Goede | 2fbf091 | 2014-12-23 23:04:35 +0100 | [diff] [blame] | 555 | config VIDEO_HDMI |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 556 | bool "HDMI output support" |
Hans de Goede | 2fbf091 | 2014-12-23 23:04:35 +0100 | [diff] [blame] | 557 | depends on VIDEO && !MACH_SUN8I |
| 558 | default y |
| 559 | ---help--- |
| 560 | Say Y here to add support for outputting video over HDMI. |
| 561 | |
Hans de Goede | d9786d2 | 2014-12-25 13:58:06 +0100 | [diff] [blame] | 562 | config VIDEO_VGA |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 563 | bool "VGA output support" |
Hans de Goede | d9786d2 | 2014-12-25 13:58:06 +0100 | [diff] [blame] | 564 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
| 565 | default n |
| 566 | ---help--- |
| 567 | Say Y here to add support for outputting video over VGA. |
| 568 | |
Hans de Goede | e2bbdfb | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 569 | config VIDEO_VGA_VIA_LCD |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 570 | bool "VGA via LCD controller support" |
Chen-Yu Tsai | 2583d5b | 2015-01-12 18:02:10 +0800 | [diff] [blame] | 571 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
Hans de Goede | e2bbdfb | 2014-12-24 12:17:07 +0100 | [diff] [blame] | 572 | default n |
| 573 | ---help--- |
| 574 | Say Y here to add support for external DACs connected to the parallel |
| 575 | LCD interface driving a VGA connector, such as found on the |
| 576 | Olimex A13 boards. |
| 577 | |
Hans de Goede | fb75d97 | 2015-01-25 15:33:07 +0100 | [diff] [blame] | 578 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 579 | bool "Force sync active high for VGA via LCD controller support" |
Hans de Goede | fb75d97 | 2015-01-25 15:33:07 +0100 | [diff] [blame] | 580 | depends on VIDEO_VGA_VIA_LCD |
| 581 | default n |
| 582 | ---help--- |
| 583 | Say Y here if you've a board which uses opendrain drivers for the vga |
| 584 | hsync and vsync signals. Opendrain drivers cannot generate steep enough |
| 585 | positive edges for a stable video output, so on boards with opendrain |
| 586 | drivers the sync signals must always be active high. |
| 587 | |
Chen-Yu Tsai | 507e27d | 2015-01-12 18:02:11 +0800 | [diff] [blame] | 588 | config VIDEO_VGA_EXTERNAL_DAC_EN |
| 589 | string "LCD panel power enable pin" |
| 590 | depends on VIDEO_VGA_VIA_LCD |
| 591 | default "" |
| 592 | ---help--- |
| 593 | Set the enable pin for the external VGA DAC. This takes a string in the |
| 594 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 595 | |
Hans de Goede | 39920c8 | 2015-08-03 19:20:26 +0200 | [diff] [blame] | 596 | config VIDEO_COMPOSITE |
Masahiro Yamada | ab65006 | 2016-08-12 10:26:50 +0900 | [diff] [blame] | 597 | bool "Composite video output support" |
Hans de Goede | 39920c8 | 2015-08-03 19:20:26 +0200 | [diff] [blame] | 598 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
| 599 | default n |
| 600 | ---help--- |
| 601 | Say Y here to add support for outputting composite video. |
| 602 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 603 | config VIDEO_LCD_MODE |
| 604 | string "LCD panel timing details" |
| 605 | depends on VIDEO |
| 606 | default "" |
| 607 | ---help--- |
| 608 | LCD panel timing details string, leave empty if there is no LCD panel. |
| 609 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. |
| 610 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 |
Hans de Goede | 8addd3e | 2015-08-16 11:23:42 +0200 | [diff] [blame] | 611 | Also see: http://linux-sunxi.org/LCD |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 612 | |
Hans de Goede | 6515032 | 2015-01-13 13:21:46 +0100 | [diff] [blame] | 613 | config VIDEO_LCD_DCLK_PHASE |
| 614 | int "LCD panel display clock phase" |
| 615 | depends on VIDEO |
| 616 | default 1 |
| 617 | ---help--- |
| 618 | Select LCD panel display clock phase shift, range 0-3. |
| 619 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 620 | config VIDEO_LCD_POWER |
| 621 | string "LCD panel power enable pin" |
| 622 | depends on VIDEO |
| 623 | default "" |
| 624 | ---help--- |
| 625 | Set the power enable pin for the LCD panel. This takes a string in the |
| 626 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 627 | |
Hans de Goede | 242e3d8 | 2015-02-16 17:26:41 +0100 | [diff] [blame] | 628 | config VIDEO_LCD_RESET |
| 629 | string "LCD panel reset pin" |
| 630 | depends on VIDEO |
| 631 | default "" |
| 632 | ---help--- |
| 633 | Set the reset pin for the LCD panel. This takes a string in the format |
| 634 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 635 | |
Hans de Goede | 2dae800 | 2014-12-21 16:28:32 +0100 | [diff] [blame] | 636 | config VIDEO_LCD_BL_EN |
| 637 | string "LCD panel backlight enable pin" |
| 638 | depends on VIDEO |
| 639 | default "" |
| 640 | ---help--- |
| 641 | Set the backlight enable pin for the LCD panel. This takes a string in the |
| 642 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of |
| 643 | port H. |
| 644 | |
| 645 | config VIDEO_LCD_BL_PWM |
| 646 | string "LCD panel backlight pwm pin" |
| 647 | depends on VIDEO |
| 648 | default "" |
| 649 | ---help--- |
| 650 | Set the backlight pwm pin for the LCD panel. This takes a string in the |
| 651 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
Luc Verhaegen | 7f2c521 | 2014-08-13 07:55:06 +0200 | [diff] [blame] | 652 | |
Hans de Goede | a7403ae | 2015-01-22 21:02:42 +0100 | [diff] [blame] | 653 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
| 654 | bool "LCD panel backlight pwm is inverted" |
| 655 | depends on VIDEO |
| 656 | default y |
| 657 | ---help--- |
| 658 | Set this if the backlight pwm output is active low. |
| 659 | |
Hans de Goede | 5541008 | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 660 | config VIDEO_LCD_PANEL_I2C |
| 661 | bool "LCD panel needs to be configured via i2c" |
| 662 | depends on VIDEO |
Hans de Goede | 1fc4201 | 2015-03-07 12:00:02 +0100 | [diff] [blame] | 663 | default n |
Hans de Goede | 0878a8a | 2016-05-15 13:51:58 +0200 | [diff] [blame] | 664 | select CMD_I2C |
Hans de Goede | 5541008 | 2015-02-16 17:23:25 +0100 | [diff] [blame] | 665 | ---help--- |
| 666 | Say y here if the LCD panel needs to be configured via i2c. This |
| 667 | will add a bitbang i2c controller using gpios to talk to the LCD. |
| 668 | |
| 669 | config VIDEO_LCD_PANEL_I2C_SDA |
| 670 | string "LCD panel i2c interface SDA pin" |
| 671 | depends on VIDEO_LCD_PANEL_I2C |
| 672 | default "PG12" |
| 673 | ---help--- |
| 674 | Set the SDA pin for the LCD i2c interface. This takes a string in the |
| 675 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 676 | |
| 677 | config VIDEO_LCD_PANEL_I2C_SCL |
| 678 | string "LCD panel i2c interface SCL pin" |
| 679 | depends on VIDEO_LCD_PANEL_I2C |
| 680 | default "PG10" |
| 681 | ---help--- |
| 682 | Set the SCL pin for the LCD i2c interface. This takes a string in the |
| 683 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. |
| 684 | |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 685 | |
| 686 | # Note only one of these may be selected at a time! But hidden choices are |
| 687 | # not supported by Kconfig |
| 688 | config VIDEO_LCD_IF_PARALLEL |
| 689 | bool |
| 690 | |
| 691 | config VIDEO_LCD_IF_LVDS |
| 692 | bool |
| 693 | |
Jernej Skrabec | 1ae5def | 2017-03-27 19:22:31 +0200 | [diff] [blame^] | 694 | config SUNXI_DE2 |
| 695 | bool |
| 696 | default n |
| 697 | |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 698 | |
| 699 | choice |
| 700 | prompt "LCD panel support" |
| 701 | depends on VIDEO |
| 702 | ---help--- |
| 703 | Select which type of LCD panel to support. |
| 704 | |
| 705 | config VIDEO_LCD_PANEL_PARALLEL |
| 706 | bool "Generic parallel interface LCD panel" |
| 707 | select VIDEO_LCD_IF_PARALLEL |
| 708 | |
| 709 | config VIDEO_LCD_PANEL_LVDS |
| 710 | bool "Generic lvds interface LCD panel" |
| 711 | select VIDEO_LCD_IF_LVDS |
| 712 | |
Siarhei Siamashka | 97ece83 | 2015-01-19 05:23:33 +0200 | [diff] [blame] | 713 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
| 714 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" |
| 715 | select VIDEO_LCD_SSD2828 |
| 716 | select VIDEO_LCD_IF_PARALLEL |
| 717 | ---help--- |
Hans de Goede | c1cfd51 | 2015-08-08 16:13:53 +0200 | [diff] [blame] | 718 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
| 719 | |
| 720 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 |
| 721 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" |
| 722 | select VIDEO_LCD_ANX9804 |
| 723 | select VIDEO_LCD_IF_PARALLEL |
| 724 | select VIDEO_LCD_PANEL_I2C |
| 725 | ---help--- |
| 726 | Select this for eDP LCD panels with 4 lanes running at 1.62G, |
| 727 | connected via an ANX9804 bridge chip. |
Siarhei Siamashka | 97ece83 | 2015-01-19 05:23:33 +0200 | [diff] [blame] | 728 | |
Hans de Goede | 27515b2 | 2015-01-20 09:23:36 +0100 | [diff] [blame] | 729 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
| 730 | bool "Hitachi tx18d42vm LCD panel" |
| 731 | select VIDEO_LCD_HITACHI_TX18D42VM |
| 732 | select VIDEO_LCD_IF_LVDS |
| 733 | ---help--- |
| 734 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support |
| 735 | |
Hans de Goede | aad2ac2 | 2015-02-16 17:49:47 +0100 | [diff] [blame] | 736 | config VIDEO_LCD_TL059WV5C0 |
| 737 | bool "tl059wv5c0 LCD panel" |
| 738 | select VIDEO_LCD_PANEL_I2C |
| 739 | select VIDEO_LCD_IF_PARALLEL |
| 740 | ---help--- |
| 741 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and |
| 742 | Aigo M60/M608/M606 tablets. |
| 743 | |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 744 | endchoice |
| 745 | |
Mylène Josserand | d7b560e | 2017-04-02 12:59:09 +0200 | [diff] [blame] | 746 | config SATAPWR |
| 747 | string "SATA power pin" |
| 748 | default "" |
| 749 | help |
| 750 | Set the pins used to power the SATA. This takes a string in the |
| 751 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of |
| 752 | port H. |
Hans de Goede | 213480e | 2015-01-01 22:04:34 +0100 | [diff] [blame] | 753 | |
Hans de Goede | c13f60d | 2015-01-25 12:10:48 +0100 | [diff] [blame] | 754 | config GMAC_TX_DELAY |
| 755 | int "GMAC Transmit Clock Delay Chain" |
| 756 | default 0 |
| 757 | ---help--- |
| 758 | Set the GMAC Transmit Clock Delay Chain value. |
| 759 | |
Hans de Goede | ff42d10 | 2015-09-13 13:02:48 +0200 | [diff] [blame] | 760 | config SPL_STACK_R_ADDR |
Chen-Yu Tsai | 301791c | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 761 | default 0x4fe00000 if MACH_SUN4I |
| 762 | default 0x4fe00000 if MACH_SUN5I |
| 763 | default 0x4fe00000 if MACH_SUN6I |
| 764 | default 0x4fe00000 if MACH_SUN7I |
| 765 | default 0x4fe00000 if MACH_SUN8I |
Hans de Goede | ff42d10 | 2015-09-13 13:02:48 +0200 | [diff] [blame] | 766 | default 0x2fe00000 if MACH_SUN9I |
Chen-Yu Tsai | 301791c | 2017-03-02 16:03:06 +0800 | [diff] [blame] | 767 | default 0x4fe00000 if MACH_SUN50I |
Hans de Goede | ff42d10 | 2015-09-13 13:02:48 +0200 | [diff] [blame] | 768 | |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 769 | endif |