blob: 7350e25e289581ab4ae348c47bae113d72f4f6e1 [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Siva Durga Prasad Paladugua4d88922016-07-29 15:31:47 +05303config IDENT_STRING
4 default " Allwinner Technology"
5
Alexandru Gagniuc0dcf18c2017-04-04 10:02:58 -07006# FIXME: Should not redefine these Kconfig symbols
Simon Glass8f925582016-10-17 20:12:36 -06007config PRE_CONSOLE_BUFFER
8 default y
9
Simon Glass53b5bf32016-09-12 23:18:39 -060010config SPL_GPIO_SUPPORT
11 default y
12
Simon Glass77d2f7f2016-09-12 23:18:41 -060013config SPL_LIBCOMMON_SUPPORT
14 default y
15
Simon Glass1646eba2016-09-12 23:18:42 -060016config SPL_LIBDISK_SUPPORT
17 default y
18
Simon Glasscc4288e2016-09-12 23:18:43 -060019config SPL_LIBGENERIC_SUPPORT
20 default y
21
Simon Glass1fdf7c62016-09-12 23:18:44 -060022config SPL_MMC_SUPPORT
Alexandru Gagniuc0dcf18c2017-04-04 10:02:58 -070023 depends on SPL && GENERIC_MMC
Simon Glass1fdf7c62016-09-12 23:18:44 -060024 default y
25
Simon Glass22537972016-09-12 23:18:54 -060026config SPL_POWER_SUPPORT
27 default y
28
Simon Glasse00f76c2016-09-12 23:18:56 -060029config SPL_SERIAL_SUPPORT
30 default y
31
Andre Przywarabc613d82017-02-16 01:20:23 +000032config SUNXI_HIGH_SRAM
33 bool
34 default n
35 ---help---
36 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
37 with the first SRAM region being located at address 0.
38 Some newer SoCs map the boot ROM at address 0 instead and move the
39 SRAM to 64KB, just behind the mask ROM.
40 Chips using the latter setup are supposed to select this option to
41 adjust the addresses accordingly.
42
Hans de Goede44d8ae52015-04-06 20:33:34 +020043# Note only one of these may be selected at a time! But hidden choices are
44# not supported by Kconfig
45config SUNXI_GEN_SUN4I
46 bool
47 ---help---
48 Select this for sunxi SoCs which have resets and clocks set up
49 as the original A10 (mach-sun4i).
50
51config SUNXI_GEN_SUN6I
52 bool
53 ---help---
54 Select this for sunxi SoCs which have sun6i like periphery, like
55 separate ahb reset control registers, custom pmic bus, new style
56 watchdog, etc.
57
58
Andre Przywara7b82a222017-02-16 01:20:27 +000059config MACH_SUNXI_H3_H5
60 bool
Jernej Skrabec1ae5def2017-03-27 19:22:31 +020061 select SUNXI_DE2
Andre Przywara7b82a222017-02-16 01:20:27 +000062 select SUNXI_GEN_SUN6I
63 select SUPPORT_SPL
64
Ian Campbell2c7e3b92014-10-24 21:20:44 +010065choice
66 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +020067 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +010068
Ian Campbellc3be2792014-10-24 21:20:45 +010069config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010070 bool "sun4i (Allwinner A10)"
71 select CPU_V7
Andre Przywara85db5832017-02-16 01:20:21 +000072 select ARM_CORTEX_CPU_IS_UP
Hans de Goede44d8ae52015-04-06 20:33:34 +020073 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010074 select SUPPORT_SPL
75
Ian Campbellc3be2792014-10-24 21:20:45 +010076config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010077 bool "sun5i (Allwinner A13)"
78 select CPU_V7
Andre Przywara85db5832017-02-16 01:20:21 +000079 select ARM_CORTEX_CPU_IS_UP
Hans de Goede44d8ae52015-04-06 20:33:34 +020080 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010081 select SUPPORT_SPL
82
Ian Campbellc3be2792014-10-24 21:20:45 +010083config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010084 bool "sun6i (Allwinner A31)"
85 select CPU_V7
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080086 select CPU_V7_HAS_NONSEC
87 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090088 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020089 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +020090 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +080091 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +010092
Ian Campbellc3be2792014-10-24 21:20:45 +010093config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +010094 bool "sun7i (Allwinner A20)"
95 select CPU_V7
Hans de Goedeea624e12014-11-14 09:34:30 +010096 select CPU_V7_HAS_NONSEC
97 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +090098 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +020099 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100100 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +0200101 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100102
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200103config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100104 bool "sun8i (Allwinner A23)"
105 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800106 select CPU_V7_HAS_NONSEC
107 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900108 select ARCH_SUPPORT_PSCI
Hans de Goede44d8ae52015-04-06 20:33:34 +0200109 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +0100110 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800111 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100112
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530113config MACH_SUN8I_A33
114 bool "sun8i (Allwinner A33)"
115 select CPU_V7
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800116 select CPU_V7_HAS_NONSEC
117 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900118 select ARCH_SUPPORT_PSCI
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530119 select SUNXI_GEN_SUN6I
120 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800121 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530122
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800123config MACH_SUN8I_A83T
124 bool "sun8i (Allwinner A83T)"
125 select CPU_V7
126 select SUNXI_GEN_SUN6I
127 select SUPPORT_SPL
128
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100129config MACH_SUN8I_H3
130 bool "sun8i (Allwinner H3)"
131 select CPU_V7
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800132 select CPU_V7_HAS_NONSEC
133 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900134 select ARCH_SUPPORT_PSCI
Andre Przywara7b82a222017-02-16 01:20:27 +0000135 select MACH_SUNXI_H3_H5
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800136 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100137
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800138config MACH_SUN8I_R40
139 bool "sun8i (Allwinner R40)"
140 select CPU_V7
Chen-Yu Tsai09186482017-03-01 11:03:15 +0800141 select CPU_V7_HAS_NONSEC
142 select CPU_V7_HAS_VIRT
143 select ARCH_SUPPORT_PSCI
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800144 select SUNXI_GEN_SUN6I
Chen-Yu Tsai50ae7ae2016-12-02 16:09:49 +0800145 select SUPPORT_SPL
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800146
Hans de Goede1871a8c2015-01-13 19:25:06 +0100147config MACH_SUN9I
148 bool "sun9i (Allwinner A80)"
149 select CPU_V7
Andre Przywarabc613d82017-02-16 01:20:23 +0000150 select SUNXI_HIGH_SRAM
Hans de Goede1871a8c2015-01-13 19:25:06 +0100151 select SUNXI_GEN_SUN6I
Philipp Tomsicha98c2962016-10-28 18:21:32 +0800152 select SUPPORT_SPL
Hans de Goede1871a8c2015-01-13 19:25:06 +0100153
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800154config MACH_SUN50I
155 bool "sun50i (Allwinner A64)"
156 select ARM64
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200157 select SUNXI_DE2
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800158 select SUNXI_GEN_SUN6I
Andre Przywarabc613d82017-02-16 01:20:23 +0000159 select SUNXI_HIGH_SRAM
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000160 select SUPPORT_SPL
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800161
Andre Przywara997bde62017-02-16 01:20:28 +0000162config MACH_SUN50I_H5
163 bool "sun50i (Allwinner H5)"
164 select ARM64
165 select MACH_SUNXI_H3_H5
166 select SUNXI_HIGH_SRAM
167
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100168endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800169
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200170# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
171config MACH_SUN8I
172 bool
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800173 default y if MACH_SUN8I_A23
174 default y if MACH_SUN8I_A33
175 default y if MACH_SUN8I_A83T
176 default y if MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800177 default y if MACH_SUN8I_R40
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200178
Andre Przywarab5402d12017-01-02 11:48:35 +0000179config RESERVE_ALLWINNER_BOOT0_HEADER
180 bool "reserve space for Allwinner boot0 header"
181 select ENABLE_ARM_SOC_BOOT0_HOOK
182 ---help---
183 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
184 filled with magic values post build. The Allwinner provided boot0
185 blob relies on this information to load and execute U-Boot.
186 Only needed on 64-bit Allwinner boards so far when using boot0.
187
Andre Przywara83843c92017-01-02 11:48:36 +0000188config ARM_BOOT_HOOK_RMR
189 bool
190 depends on ARM64
191 default y
192 select ENABLE_ARM_SOC_BOOT0_HOOK
193 ---help---
194 Insert some ARM32 code at the very beginning of the U-Boot binary
195 which uses an RMR register write to bring the core into AArch64 mode.
196 The very first instruction acts as a switch, since it's carefully
197 chosen to be a NOP in one mode and a branch in the other, so the
198 code would only be executed if not already in AArch64.
199 This allows both the SPL and the U-Boot proper to be entered in
200 either mode and switch to AArch64 if needed.
201
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800202config DRAM_TYPE
203 int "sunxi dram type"
204 depends on MACH_SUN8I_A83T
205 default 3
206 ---help---
207 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200208
Hans de Goede37781a12014-11-15 19:46:39 +0100209config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100210 int "sunxi dram clock speed"
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800211 default 792 if MACH_SUN9I
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800212 default 648 if MACH_SUN8I_R40
Hans de Goede8ffc4872015-01-17 14:24:55 +0100213 default 312 if MACH_SUN6I || MACH_SUN8I
214 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
Andre Przywara52e31822017-01-02 11:48:37 +0000215 default 672 if MACH_SUN50I
Hans de Goede37781a12014-11-15 19:46:39 +0100216 ---help---
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800217 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
218 must be a multiple of 24. For the sun9i (A80), the tested values
219 (for DDR3-1600) are 312 to 792.
Hans de Goede37781a12014-11-15 19:46:39 +0100220
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200221if MACH_SUN5I || MACH_SUN7I
222config DRAM_MBUS_CLK
223 int "sunxi mbus clock speed"
224 default 300
225 ---help---
226 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
227
228endif
229
Hans de Goede37781a12014-11-15 19:46:39 +0100230config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100231 int "sunxi dram zq value"
232 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
233 default 127 if MACH_SUN7I
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800234 default 3881979 if MACH_SUN8I_R40
Chen-Yu Tsai58b628e2016-10-28 18:21:36 +0800235 default 4145117 if MACH_SUN9I
Andre Przywara52e31822017-01-02 11:48:37 +0000236 default 3881915 if MACH_SUN50I
Hans de Goede37781a12014-11-15 19:46:39 +0100237 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100238 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100239
Hans de Goede8975cdf2015-05-13 15:00:46 +0200240config DRAM_ODT_EN
241 bool "sunxi dram odt enable"
242 default n if !MACH_SUN8I_A23
243 default y if MACH_SUN8I_A23
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800244 default y if MACH_SUN8I_R40
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000245 default y if MACH_SUN50I
Hans de Goede8975cdf2015-05-13 15:00:46 +0200246 ---help---
247 Select this to enable dram odt (on die termination).
248
Hans de Goede8ffc4872015-01-17 14:24:55 +0100249if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
250config DRAM_EMR1
251 int "sunxi dram emr1 value"
252 default 0 if MACH_SUN4I
253 default 4 if MACH_SUN5I || MACH_SUN7I
254 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100255 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200256
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200257config DRAM_TPR3
258 hex "sunxi dram tpr3 value"
259 default 0
260 ---help---
261 Set the dram controller tpr3 parameter. This parameter configures
262 the delay on the command lane and also phase shifts, which are
263 applied for sampling incoming read data. The default value 0
264 means that no phase/delay adjustments are necessary. Properly
265 configuring this parameter increases reliability at high DRAM
266 clock speeds.
267
268config DRAM_DQS_GATING_DELAY
269 hex "sunxi dram dqs_gating_delay value"
270 default 0
271 ---help---
272 Set the dram controller dqs_gating_delay parmeter. Each byte
273 encodes the DQS gating delay for each byte lane. The delay
274 granularity is 1/4 cycle. For example, the value 0x05060606
275 means that the delay is 5 quarter-cycles for one lane (1.25
276 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
277 The default value 0 means autodetection. The results of hardware
278 autodetection are not very reliable and depend on the chip
279 temperature (sometimes producing different results on cold start
280 and warm reboot). But the accuracy of hardware autodetection
281 is usually good enough, unless running at really high DRAM
282 clocks speeds (up to 600MHz). If unsure, keep as 0.
283
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200284choice
285 prompt "sunxi dram timings"
286 default DRAM_TIMINGS_VENDOR_MAGIC
287 ---help---
288 Select the timings of the DDR3 chips.
289
290config DRAM_TIMINGS_VENDOR_MAGIC
291 bool "Magic vendor timings from Android"
292 ---help---
293 The same DRAM timings as in the Allwinner boot0 bootloader.
294
295config DRAM_TIMINGS_DDR3_1066F_1333H
296 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
297 ---help---
298 Use the timings of the standard JEDEC DDR3-1066F speed bin for
299 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
300 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
301 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
302 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
303 that down binning to DDR3-1066F is supported (because DDR3-1066F
304 uses a bit faster timings than DDR3-1333H).
305
306config DRAM_TIMINGS_DDR3_800E_1066G_1333J
307 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
308 ---help---
309 Use the timings of the slowest possible JEDEC speed bin for the
310 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
311 DDR3-800E, DDR3-1066G or DDR3-1333J.
312
313endchoice
314
Hans de Goede37781a12014-11-15 19:46:39 +0100315endif
316
Hans de Goede8975cdf2015-05-13 15:00:46 +0200317if MACH_SUN8I_A23
318config DRAM_ODT_CORRECTION
319 int "sunxi dram odt correction value"
320 default 0
321 ---help---
322 Set the dram odt correction value (range -255 - 255). In allwinner
323 fex files, this option is found in bits 8-15 of the u32 odt_en variable
324 in the [dram] section. When bit 31 of the odt_en variable is set
325 then the correction is negative. Usually the value for this is 0.
326endif
327
Iain Patone71b4222015-03-28 10:26:38 +0000328config SYS_CLK_FREQ
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800329 default 1008000000 if MACH_SUN4I
330 default 1008000000 if MACH_SUN5I
331 default 1008000000 if MACH_SUN6I
Iain Patone71b4222015-03-28 10:26:38 +0000332 default 912000000 if MACH_SUN7I
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800333 default 1008000000 if MACH_SUN8I
334 default 1008000000 if MACH_SUN9I
335 default 816000000 if MACH_SUN50I
Iain Patone71b4222015-03-28 10:26:38 +0000336
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800337config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100338 default "sun4i" if MACH_SUN4I
339 default "sun5i" if MACH_SUN5I
340 default "sun6i" if MACH_SUN6I
341 default "sun7i" if MACH_SUN7I
342 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100343 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200344 default "sun50i" if MACH_SUN50I
Hans de Goede6ae66f22014-08-01 09:28:24 +0200345
Masahiro Yamadadd840582014-07-30 14:08:14 +0900346config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900347 default "sunxi"
348
349config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900350 default "sunxi"
351
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200352config UART0_PORT_F
353 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200354 default n
355 ---help---
356 Repurpose the SD card slot for getting access to the UART0 serial
357 console. Primarily useful only for low level u-boot debugging on
358 tablets, where normal UART0 is difficult to access and requires
359 device disassembly and/or soldering. As the SD card can't be used
360 at the same time, the system can be only booted in the FEL mode.
361 Only enable this if you really know what you are doing.
362
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200363config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900364 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200365 default n
366 ---help---
367 Set this to enable various workarounds for old kernels, this results in
368 sub-optimal settings for newer kernels, only enable if needed.
369
Mylène Josserandf5fd7882017-04-02 12:59:10 +0200370config MACPWR
371 string "MAC power pin"
372 default ""
373 help
374 Set the pin used to power the MAC. This takes a string in the format
375 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
376
Hans de Goedecd821132014-10-02 20:29:26 +0200377config MMC0_CD_PIN
378 string "Card detect pin for mmc0"
Andre Przywara7b82a222017-02-16 01:20:27 +0000379 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200380 default ""
381 ---help---
382 Set the card detect pin for mmc0, leave empty to not use cd. This
383 takes a string in the format understood by sunxi_name_to_gpio, e.g.
384 PH1 for pin 1 of port H.
385
386config MMC1_CD_PIN
387 string "Card detect pin for mmc1"
388 default ""
389 ---help---
390 See MMC0_CD_PIN help text.
391
392config MMC2_CD_PIN
393 string "Card detect pin for mmc2"
394 default ""
395 ---help---
396 See MMC0_CD_PIN help text.
397
398config MMC3_CD_PIN
399 string "Card detect pin for mmc3"
400 default ""
401 ---help---
402 See MMC0_CD_PIN help text.
403
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100404config MMC1_PINS
405 string "Pins for mmc1"
406 default ""
407 ---help---
408 Set the pins used for mmc1, when applicable. This takes a string in the
409 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
410
411config MMC2_PINS
412 string "Pins for mmc2"
413 default ""
414 ---help---
415 See MMC1_PINS help text.
416
417config MMC3_PINS
418 string "Pins for mmc3"
419 default ""
420 ---help---
421 See MMC1_PINS help text.
422
Hans de Goede2ccfac02014-10-02 20:43:50 +0200423config MMC_SUNXI_SLOT_EXTRA
424 int "mmc extra slot number"
425 default -1
426 ---help---
427 sunxi builds always enable mmc0, some boards also have a second sdcard
428 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
429 support for this.
430
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200431config INITIAL_USB_SCAN_DELAY
432 int "delay initial usb scan by x ms to allow builtin devices to init"
433 default 0
434 ---help---
435 Some boards have on board usb devices which need longer than the
436 USB spec's 1 second to connect from board powerup. Set this config
437 option to a non 0 value to add an extra delay before the first usb
438 bus scan.
439
Hans de Goede4458b7a2015-01-07 15:26:06 +0100440config USB0_VBUS_PIN
441 string "Vbus enable pin for usb0 (otg)"
442 default ""
443 ---help---
444 Set the Vbus enable pin for usb0 (otg). This takes a string in the
445 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
446
Hans de Goede52defe82015-02-16 22:13:43 +0100447config USB0_VBUS_DET
448 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100449 default ""
450 ---help---
451 Set the Vbus detect pin for usb0 (otg). This takes a string in the
452 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
453
Hans de Goede48c06c92015-06-14 17:29:53 +0200454config USB0_ID_DET
455 string "ID detect pin for usb0 (otg)"
456 default ""
457 ---help---
458 Set the ID detect pin for usb0 (otg). This takes a string in the
459 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
460
Hans de Goede115200c2014-11-07 16:09:00 +0100461config USB1_VBUS_PIN
462 string "Vbus enable pin for usb1 (ehci0)"
463 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100464 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100465 ---help---
466 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
467 a string in the format understood by sunxi_name_to_gpio, e.g.
468 PH1 for pin 1 of port H.
469
470config USB2_VBUS_PIN
471 string "Vbus enable pin for usb2 (ehci1)"
472 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100473 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100474 ---help---
475 See USB1_VBUS_PIN help text.
476
Hans de Goede60fa6302016-03-18 08:42:01 +0100477config USB3_VBUS_PIN
478 string "Vbus enable pin for usb3 (ehci2)"
479 default ""
480 ---help---
481 See USB1_VBUS_PIN help text.
482
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200483config I2C0_ENABLE
484 bool "Enable I2C/TWI controller 0"
Chen-Yu Tsai409677e2016-11-30 15:30:30 +0800485 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200486 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200487 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200488 ---help---
489 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
490 its clock and setting up the bus. This is especially useful on devices
491 with slaves connected to the bus or with pins exposed through e.g. an
492 expansion port/header.
493
494config I2C1_ENABLE
495 bool "Enable I2C/TWI controller 1"
496 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200497 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200498 ---help---
499 See I2C0_ENABLE help text.
500
501config I2C2_ENABLE
502 bool "Enable I2C/TWI controller 2"
503 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200504 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200505 ---help---
506 See I2C0_ENABLE help text.
507
508if MACH_SUN6I || MACH_SUN7I
509config I2C3_ENABLE
510 bool "Enable I2C/TWI controller 3"
511 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200512 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200513 ---help---
514 See I2C0_ENABLE help text.
515endif
516
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100517if SUNXI_GEN_SUN6I
Jelle van der Waa9d082682016-01-14 14:06:26 +0100518config R_I2C_ENABLE
519 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100520 # This is used for the pmic on H3
521 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200522 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100523 ---help---
524 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100525endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100526
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200527if MACH_SUN7I
528config I2C4_ENABLE
529 bool "Enable I2C/TWI controller 4"
530 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200531 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200532 ---help---
533 See I2C0_ENABLE help text.
534endif
535
Hans de Goede2fcf0332015-04-25 17:25:14 +0200536config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900537 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200538 default n
539 ---help---
540 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
541
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200542config VIDEO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900543 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800544 depends on !MACH_SUN8I_A83T
545 depends on !MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800546 depends on !MACH_SUN8I_R40
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800547 depends on !MACH_SUN9I
548 depends on !MACH_SUN50I
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200549 default y
550 ---help---
Hans de Goede2dae8002014-12-21 16:28:32 +0100551 Say Y here to add support for using a cfb console on the HDMI, LCD
552 or VGA output found on most sunxi devices. See doc/README.video for
553 info on how to select the video output and mode.
554
Hans de Goede2fbf0912014-12-23 23:04:35 +0100555config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900556 bool "HDMI output support"
Hans de Goede2fbf0912014-12-23 23:04:35 +0100557 depends on VIDEO && !MACH_SUN8I
558 default y
559 ---help---
560 Say Y here to add support for outputting video over HDMI.
561
Hans de Goeded9786d22014-12-25 13:58:06 +0100562config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900563 bool "VGA output support"
Hans de Goeded9786d22014-12-25 13:58:06 +0100564 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
565 default n
566 ---help---
567 Say Y here to add support for outputting video over VGA.
568
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100569config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900570 bool "VGA via LCD controller support"
Chen-Yu Tsai2583d5b2015-01-12 18:02:10 +0800571 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100572 default n
573 ---help---
574 Say Y here to add support for external DACs connected to the parallel
575 LCD interface driving a VGA connector, such as found on the
576 Olimex A13 boards.
577
Hans de Goedefb75d972015-01-25 15:33:07 +0100578config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900579 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100580 depends on VIDEO_VGA_VIA_LCD
581 default n
582 ---help---
583 Say Y here if you've a board which uses opendrain drivers for the vga
584 hsync and vsync signals. Opendrain drivers cannot generate steep enough
585 positive edges for a stable video output, so on boards with opendrain
586 drivers the sync signals must always be active high.
587
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800588config VIDEO_VGA_EXTERNAL_DAC_EN
589 string "LCD panel power enable pin"
590 depends on VIDEO_VGA_VIA_LCD
591 default ""
592 ---help---
593 Set the enable pin for the external VGA DAC. This takes a string in the
594 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
595
Hans de Goede39920c82015-08-03 19:20:26 +0200596config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900597 bool "Composite video output support"
Hans de Goede39920c82015-08-03 19:20:26 +0200598 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
599 default n
600 ---help---
601 Say Y here to add support for outputting composite video.
602
Hans de Goede2dae8002014-12-21 16:28:32 +0100603config VIDEO_LCD_MODE
604 string "LCD panel timing details"
605 depends on VIDEO
606 default ""
607 ---help---
608 LCD panel timing details string, leave empty if there is no LCD panel.
609 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
610 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200611 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100612
Hans de Goede65150322015-01-13 13:21:46 +0100613config VIDEO_LCD_DCLK_PHASE
614 int "LCD panel display clock phase"
615 depends on VIDEO
616 default 1
617 ---help---
618 Select LCD panel display clock phase shift, range 0-3.
619
Hans de Goede2dae8002014-12-21 16:28:32 +0100620config VIDEO_LCD_POWER
621 string "LCD panel power enable pin"
622 depends on VIDEO
623 default ""
624 ---help---
625 Set the power enable pin for the LCD panel. This takes a string in the
626 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
627
Hans de Goede242e3d82015-02-16 17:26:41 +0100628config VIDEO_LCD_RESET
629 string "LCD panel reset pin"
630 depends on VIDEO
631 default ""
632 ---help---
633 Set the reset pin for the LCD panel. This takes a string in the format
634 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
635
Hans de Goede2dae8002014-12-21 16:28:32 +0100636config VIDEO_LCD_BL_EN
637 string "LCD panel backlight enable pin"
638 depends on VIDEO
639 default ""
640 ---help---
641 Set the backlight enable pin for the LCD panel. This takes a string in the
642 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
643 port H.
644
645config VIDEO_LCD_BL_PWM
646 string "LCD panel backlight pwm pin"
647 depends on VIDEO
648 default ""
649 ---help---
650 Set the backlight pwm pin for the LCD panel. This takes a string in the
651 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200652
Hans de Goedea7403ae2015-01-22 21:02:42 +0100653config VIDEO_LCD_BL_PWM_ACTIVE_LOW
654 bool "LCD panel backlight pwm is inverted"
655 depends on VIDEO
656 default y
657 ---help---
658 Set this if the backlight pwm output is active low.
659
Hans de Goede55410082015-02-16 17:23:25 +0100660config VIDEO_LCD_PANEL_I2C
661 bool "LCD panel needs to be configured via i2c"
662 depends on VIDEO
Hans de Goede1fc42012015-03-07 12:00:02 +0100663 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200664 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100665 ---help---
666 Say y here if the LCD panel needs to be configured via i2c. This
667 will add a bitbang i2c controller using gpios to talk to the LCD.
668
669config VIDEO_LCD_PANEL_I2C_SDA
670 string "LCD panel i2c interface SDA pin"
671 depends on VIDEO_LCD_PANEL_I2C
672 default "PG12"
673 ---help---
674 Set the SDA pin for the LCD i2c interface. This takes a string in the
675 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
676
677config VIDEO_LCD_PANEL_I2C_SCL
678 string "LCD panel i2c interface SCL pin"
679 depends on VIDEO_LCD_PANEL_I2C
680 default "PG10"
681 ---help---
682 Set the SCL pin for the LCD i2c interface. This takes a string in the
683 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
684
Hans de Goede213480e2015-01-01 22:04:34 +0100685
686# Note only one of these may be selected at a time! But hidden choices are
687# not supported by Kconfig
688config VIDEO_LCD_IF_PARALLEL
689 bool
690
691config VIDEO_LCD_IF_LVDS
692 bool
693
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200694config SUNXI_DE2
695 bool
696 default n
697
Hans de Goede213480e2015-01-01 22:04:34 +0100698
699choice
700 prompt "LCD panel support"
701 depends on VIDEO
702 ---help---
703 Select which type of LCD panel to support.
704
705config VIDEO_LCD_PANEL_PARALLEL
706 bool "Generic parallel interface LCD panel"
707 select VIDEO_LCD_IF_PARALLEL
708
709config VIDEO_LCD_PANEL_LVDS
710 bool "Generic lvds interface LCD panel"
711 select VIDEO_LCD_IF_LVDS
712
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200713config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
714 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
715 select VIDEO_LCD_SSD2828
716 select VIDEO_LCD_IF_PARALLEL
717 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +0200718 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
719
720config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
721 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
722 select VIDEO_LCD_ANX9804
723 select VIDEO_LCD_IF_PARALLEL
724 select VIDEO_LCD_PANEL_I2C
725 ---help---
726 Select this for eDP LCD panels with 4 lanes running at 1.62G,
727 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200728
Hans de Goede27515b22015-01-20 09:23:36 +0100729config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
730 bool "Hitachi tx18d42vm LCD panel"
731 select VIDEO_LCD_HITACHI_TX18D42VM
732 select VIDEO_LCD_IF_LVDS
733 ---help---
734 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
735
Hans de Goedeaad2ac22015-02-16 17:49:47 +0100736config VIDEO_LCD_TL059WV5C0
737 bool "tl059wv5c0 LCD panel"
738 select VIDEO_LCD_PANEL_I2C
739 select VIDEO_LCD_IF_PARALLEL
740 ---help---
741 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
742 Aigo M60/M608/M606 tablets.
743
Hans de Goede213480e2015-01-01 22:04:34 +0100744endchoice
745
Mylène Josserandd7b560e2017-04-02 12:59:09 +0200746config SATAPWR
747 string "SATA power pin"
748 default ""
749 help
750 Set the pins used to power the SATA. This takes a string in the
751 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
752 port H.
Hans de Goede213480e2015-01-01 22:04:34 +0100753
Hans de Goedec13f60d2015-01-25 12:10:48 +0100754config GMAC_TX_DELAY
755 int "GMAC Transmit Clock Delay Chain"
756 default 0
757 ---help---
758 Set the GMAC Transmit Clock Delay Chain value.
759
Hans de Goedeff42d102015-09-13 13:02:48 +0200760config SPL_STACK_R_ADDR
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800761 default 0x4fe00000 if MACH_SUN4I
762 default 0x4fe00000 if MACH_SUN5I
763 default 0x4fe00000 if MACH_SUN6I
764 default 0x4fe00000 if MACH_SUN7I
765 default 0x4fe00000 if MACH_SUN8I
Hans de Goedeff42d102015-09-13 13:02:48 +0200766 default 0x2fe00000 if MACH_SUN9I
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800767 default 0x4fe00000 if MACH_SUN50I
Hans de Goedeff42d102015-09-13 13:02:48 +0200768
Masahiro Yamadadd840582014-07-30 14:08:14 +0900769endif