blob: d5976318d1ccfb4b787284b91d9a3bc1df09cc54 [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01008
Simon Glass2e7d35d2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070014
Simon Glass00606d72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010017 ethernet0 = "/eth@10002000";
18 ethernet2 = &swp_0;
19 ethernet3 = &eth_3;
20 ethernet4 = &dsa_eth0;
21 ethernet5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060022 gpio1 = &gpio_a;
23 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010024 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070025 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060026 mmc0 = "/mmc0";
27 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070028 pci0 = &pci0;
29 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070030 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020031 remoteproc0 = &rproc_1;
32 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060033 rtc0 = &rtc_0;
34 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060035 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020036 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070037 testbus3 = "/some-bus";
38 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070039 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070040 testfdt3 = "/b-test";
41 testfdt5 = "/some-bus/c-test@5";
42 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070043 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020044 fdt-dummy0 = "/translation-test@8000/dev@0,0";
45 fdt-dummy1 = "/translation-test@8000/dev@1,100";
46 fdt-dummy2 = "/translation-test@8000/dev@2,200";
47 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060048 usb0 = &usb_0;
49 usb1 = &usb_1;
50 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020051 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020052 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060053 };
54
Rasmus Villemoes8c728422021-04-21 11:06:55 +020055 config {
56 environment {
57 from_fdt = "yes";
58 fdt_env_path = "";
59 };
60 };
61
Nandor Hanf9db2f12021-06-10 16:56:44 +030062 reboot-mode0 {
63 compatible = "reboot-mode-gpio";
64 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
65 u-boot,env-variable = "bootstatus";
66 mode-test = <0x01>;
67 mode-download = <0x03>;
68 };
69
Nandor Hanc74675b2021-06-10 16:56:45 +030070 reboot_mode1: reboot-mode@14 {
71 compatible = "reboot-mode-rtc";
72 rtc = <&rtc_0>;
73 reg = <0x30 4>;
74 u-boot,env-variable = "bootstatus";
75 big-endian;
76 mode-test = <0x21969147>;
77 mode-download = <0x51939147>;
78 };
79
Simon Glassce6d99a2018-12-10 10:37:33 -070080 audio: audio-codec {
81 compatible = "sandbox,audio-codec";
82 #sound-dai-cells = <1>;
83 };
84
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020085 buttons {
86 compatible = "gpio-keys";
87
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020088 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020089 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020090 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020091 };
92
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020093 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020094 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020095 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020096 };
97 };
98
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010099 buttons2 {
100 compatible = "adc-keys";
101 io-channels = <&adc 3>;
102 keyup-threshold-microvolt = <3000000>;
103
104 button-up {
105 label = "button3";
106 linux,code = <KEY_F3>;
107 press-threshold-microvolt = <1500000>;
108 };
109
110 button-down {
111 label = "button4";
112 linux,code = <KEY_F4>;
113 press-threshold-microvolt = <1000000>;
114 };
115
116 button-enter {
117 label = "button5";
118 linux,code = <KEY_F5>;
119 press-threshold-microvolt = <500000>;
120 };
121 };
122
Simon Glasse96fa6c2018-12-10 10:37:34 -0700123 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600124 reg = <0 0>;
125 compatible = "google,cros-ec-sandbox";
126
127 /*
128 * This describes the flash memory within the EC. Note
129 * that the STM32L flash erases to 0, not 0xff.
130 */
131 flash {
132 image-pos = <0x08000000>;
133 size = <0x20000>;
134 erase-value = <0>;
135
136 /* Information for sandbox */
137 ro {
138 image-pos = <0>;
139 size = <0xf000>;
140 };
141 wp-ro {
142 image-pos = <0xf000>;
143 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700144 used = <0x884>;
145 compress = "lz4";
146 uncomp-size = <0xcf8>;
147 hash {
148 algo = "sha256";
149 value = [00 01 02 03 04 05 06 07
150 08 09 0a 0b 0c 0d 0e 0f
151 10 11 12 13 14 15 16 17
152 18 19 1a 1b 1c 1d 1e 1f];
153 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600154 };
155 rw {
156 image-pos = <0x10000>;
157 size = <0x10000>;
158 };
159 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300160
161 cros_ec_pwm: cros-ec-pwm {
162 compatible = "google,cros-ec-pwm";
163 #pwm-cells = <1>;
164 };
165
Simon Glasse6c5c942018-10-01 12:22:08 -0600166 };
167
Yannick Fertré23f965a2019-10-07 15:29:05 +0200168 dsi_host: dsi_host {
169 compatible = "sandbox,dsi-host";
170 };
171
Simon Glass2e7d35d2014-02-26 15:59:21 -0700172 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600173 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700174 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600175 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700176 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600177 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100178 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
179 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700180 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100181 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
182 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
183 <&gpio_b 7 GPIO_IN 3 2 1>,
184 <&gpio_b 8 GPIO_OUT 3 2 1>,
185 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100186 test3-gpios =
187 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
188 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
189 <&gpio_c 2 GPIO_OUT>,
190 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
191 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200192 <&gpio_c 5 GPIO_IN>,
193 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
194 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530195 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
196 test5-gpios = <&gpio_a 19>;
197
Simon Glassa1b17e42018-12-10 10:37:37 -0700198 int-value = <1234>;
199 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200200 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200201 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600202 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700203 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600204 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200205 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530206
207 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
208 <&muxcontroller0 2>, <&muxcontroller0 3>,
209 <&muxcontroller1>;
210 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
211 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100212 display-timings {
213 timing0: 240x320 {
214 clock-frequency = <6500000>;
215 hactive = <240>;
216 vactive = <320>;
217 hfront-porch = <6>;
218 hback-porch = <7>;
219 hsync-len = <1>;
220 vback-porch = <5>;
221 vfront-porch = <8>;
222 vsync-len = <2>;
223 hsync-active = <1>;
224 vsync-active = <0>;
225 de-active = <1>;
226 pixelclk-active = <1>;
227 interlaced;
228 doublescan;
229 doubleclk;
230 };
231 timing1: 480x800 {
232 clock-frequency = <9000000>;
233 hactive = <480>;
234 vactive = <800>;
235 hfront-porch = <10>;
236 hback-porch = <59>;
237 hsync-len = <12>;
238 vback-porch = <15>;
239 vfront-porch = <17>;
240 vsync-len = <16>;
241 hsync-active = <0>;
242 vsync-active = <1>;
243 de-active = <0>;
244 pixelclk-active = <0>;
245 };
246 timing2: 800x480 {
247 clock-frequency = <33500000>;
248 hactive = <800>;
249 vactive = <480>;
250 hback-porch = <89>;
251 hfront-porch = <164>;
252 vback-porch = <23>;
253 vfront-porch = <10>;
254 hsync-len = <11>;
255 vsync-len = <13>;
256 };
257 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700258 };
259
260 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600261 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700262 compatible = "not,compatible";
263 };
264
265 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600266 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700267 };
268
Simon Glass5d9a88f2018-10-01 12:22:40 -0600269 backlight: backlight {
270 compatible = "pwm-backlight";
271 enable-gpios = <&gpio_a 1>;
272 power-supply = <&ldo_1>;
273 pwms = <&pwm 0 1000>;
274 default-brightness-level = <5>;
275 brightness-levels = <0 16 32 64 128 170 202 234 255>;
276 };
277
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200278 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200279 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200280 bind-test-child1 {
281 compatible = "sandbox,phy";
282 #phy-cells = <1>;
283 };
284
285 bind-test-child2 {
286 compatible = "simple-bus";
287 };
288 };
289
Simon Glass2e7d35d2014-02-26 15:59:21 -0700290 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600291 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700292 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600293 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700294 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530295
296 mux-controls = <&muxcontroller0 0>;
297 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700298 };
299
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200300 phy_provider0: gen_phy@0 {
301 compatible = "sandbox,phy";
302 #phy-cells = <1>;
303 };
304
305 phy_provider1: gen_phy@1 {
306 compatible = "sandbox,phy";
307 #phy-cells = <0>;
308 broken;
309 };
310
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200311 phy_provider2: gen_phy@2 {
312 compatible = "sandbox,phy";
313 #phy-cells = <0>;
314 };
315
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200316 gen_phy_user: gen_phy_user {
317 compatible = "simple-bus";
318 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
319 phy-names = "phy1", "phy2", "phy3";
320 };
321
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200322 gen_phy_user1: gen_phy_user1 {
323 compatible = "simple-bus";
324 phys = <&phy_provider0 0>, <&phy_provider2>;
325 phy-names = "phy1", "phy2";
326 };
327
Simon Glass2e7d35d2014-02-26 15:59:21 -0700328 some-bus {
329 #address-cells = <1>;
330 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600331 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600332 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600333 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700334 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600335 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700336 compatible = "denx,u-boot-fdt-test";
337 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600338 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700339 ping-add = <5>;
340 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600341 c-test@0 {
342 compatible = "denx,u-boot-fdt-test";
343 reg = <0>;
344 ping-expect = <6>;
345 ping-add = <6>;
346 };
347 c-test@1 {
348 compatible = "denx,u-boot-fdt-test";
349 reg = <1>;
350 ping-expect = <7>;
351 ping-add = <7>;
352 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700353 };
354
355 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600356 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600357 ping-expect = <6>;
358 ping-add = <6>;
359 compatible = "google,another-fdt-test";
360 };
361
362 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600363 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600364 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700365 ping-add = <6>;
366 compatible = "google,another-fdt-test";
367 };
368
Simon Glass9cc36a22015-01-25 08:27:05 -0700369 f-test {
370 compatible = "denx,u-boot-fdt-test";
371 };
372
373 g-test {
374 compatible = "denx,u-boot-fdt-test";
375 };
376
Bin Meng2786cd72018-10-10 22:07:01 -0700377 h-test {
378 compatible = "denx,u-boot-fdt-test1";
379 };
380
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200381 i-test {
382 compatible = "mediatek,u-boot-fdt-test";
383 #address-cells = <1>;
384 #size-cells = <0>;
385
386 subnode@0 {
387 reg = <0>;
388 };
389
390 subnode@1 {
391 reg = <1>;
392 };
393
394 subnode@2 {
395 reg = <2>;
396 };
397 };
398
Simon Glassdc12ebb2019-12-29 21:19:25 -0700399 devres-test {
400 compatible = "denx,u-boot-devres-test";
401 };
402
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530403 another-test {
404 reg = <0 2>;
405 compatible = "denx,u-boot-fdt-test";
406 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
407 test5-gpios = <&gpio_a 19>;
408 };
409
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100410 mmio-bus@0 {
411 #address-cells = <1>;
412 #size-cells = <1>;
413 compatible = "denx,u-boot-test-bus";
414 dma-ranges = <0x10000000 0x00000000 0x00040000>;
415
416 subnode@0 {
417 compatible = "denx,u-boot-fdt-test";
418 };
419 };
420
421 mmio-bus@1 {
422 #address-cells = <1>;
423 #size-cells = <1>;
424 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100425
426 subnode@0 {
427 compatible = "denx,u-boot-fdt-test";
428 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100429 };
430
Simon Glass0f7b1112020-07-07 13:12:06 -0600431 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600432 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600433 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600434 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600435 child {
436 compatible = "denx,u-boot-acpi-test";
437 };
Simon Glassf50cc952020-04-08 16:57:34 -0600438 };
439
Simon Glass0f7b1112020-07-07 13:12:06 -0600440 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600441 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600442 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600443 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600444 };
445
Patrice Chotardee87a092017-09-04 14:55:57 +0200446 clocks {
447 clk_fixed: clk-fixed {
448 compatible = "fixed-clock";
449 #clock-cells = <0>;
450 clock-frequency = <1234>;
451 };
Anup Patelb630d572019-02-25 08:14:55 +0000452
453 clk_fixed_factor: clk-fixed-factor {
454 compatible = "fixed-factor-clock";
455 #clock-cells = <0>;
456 clock-div = <3>;
457 clock-mult = <2>;
458 clocks = <&clk_fixed>;
459 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200460
461 osc {
462 compatible = "fixed-clock";
463 #clock-cells = <0>;
464 clock-frequency = <20000000>;
465 };
Stephen Warren135aa952016-06-17 09:44:00 -0600466 };
467
468 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600469 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600470 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200471 assigned-clocks = <&clk_sandbox 3>;
472 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600473 };
474
475 clk-test {
476 compatible = "sandbox,clk-test";
477 clocks = <&clk_fixed>,
478 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200479 <&clk_sandbox 0>,
480 <&clk_sandbox 3>,
481 <&clk_sandbox 2>;
482 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600483 };
484
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200485 ccf: clk-ccf {
486 compatible = "sandbox,clk-ccf";
487 };
488
Simon Glass171e9912015-05-22 15:42:15 -0600489 eth@10002000 {
490 compatible = "sandbox,eth";
491 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500492 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600493 };
494
495 eth_5: eth@10003000 {
496 compatible = "sandbox,eth";
497 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500498 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600499 };
500
Bin Meng71d79712015-08-27 22:25:53 -0700501 eth_3: sbe5 {
502 compatible = "sandbox,eth";
503 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500504 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700505 };
506
Simon Glass171e9912015-05-22 15:42:15 -0600507 eth@10004000 {
508 compatible = "sandbox,eth";
509 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500510 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600511 };
512
Claudiu Manoilff98da02021-03-14 20:14:57 +0800513 dsa_eth0: dsa-test-eth {
514 compatible = "sandbox,eth";
515 reg = <0x10006000 0x1000>;
516 fake-host-hwaddr = [00 00 66 44 22 66];
517 };
518
519 dsa-test {
520 compatible = "sandbox,dsa";
521
522 ports {
523 #address-cells = <1>;
524 #size-cells = <0>;
525 swp_0: port@0 {
526 reg = <0>;
527 label = "lan0";
528 phy-mode = "rgmii-rxid";
529
530 fixed-link {
531 speed = <100>;
532 full-duplex;
533 };
534 };
535
536 swp_1: port@1 {
537 reg = <1>;
538 label = "lan1";
539 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800540 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800541 };
542
543 port@2 {
544 reg = <2>;
545 ethernet = <&dsa_eth0>;
546
547 fixed-link {
548 speed = <1000>;
549 full-duplex;
550 };
551 };
552 };
553 };
554
Rajan Vaja31b82172018-09-19 03:43:46 -0700555 firmware {
556 sandbox_firmware: sandbox-firmware {
557 compatible = "sandbox,firmware";
558 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200559
560 sandbox-scmi-agent@0 {
561 compatible = "sandbox,scmi-agent";
562 #address-cells = <1>;
563 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200564
565 clk_scmi0: protocol@14 {
566 reg = <0x14>;
567 #clock-cells = <1>;
568 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200569
570 reset_scmi0: protocol@16 {
571 reg = <0x16>;
572 #reset-cells = <1>;
573 };
Etienne Carriere01242182021-03-08 22:38:07 +0100574
575 protocol@17 {
576 reg = <0x17>;
577
578 regulators {
579 #address-cells = <1>;
580 #size-cells = <0>;
581
582 regul0_scmi0: reg@0 {
583 reg = <0>;
584 regulator-name = "sandbox-voltd0";
585 regulator-min-microvolt = <1100000>;
586 regulator-max-microvolt = <3300000>;
587 };
588 regul1_scmi0: reg@1 {
589 reg = <0x1>;
590 regulator-name = "sandbox-voltd1";
591 regulator-min-microvolt = <1800000>;
592 };
593 };
594 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200595 };
596
597 sandbox-scmi-agent@1 {
598 compatible = "sandbox,scmi-agent";
599 #address-cells = <1>;
600 #size-cells = <0>;
601
Etienne Carriere87d4f272020-09-09 18:44:05 +0200602 clk_scmi1: protocol@14 {
603 reg = <0x14>;
604 #clock-cells = <1>;
605 };
606
Etienne Carriere358599e2020-09-09 18:44:00 +0200607 protocol@10 {
608 reg = <0x10>;
609 };
610 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700611 };
612
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100613 pinctrl-gpio {
614 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700615
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100616 gpio_a: base-gpios {
617 compatible = "sandbox,gpio";
618 gpio-controller;
619 #gpio-cells = <1>;
620 gpio-bank-name = "a";
621 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200622 hog_input_active_low {
623 gpio-hog;
624 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200625 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200626 };
627 hog_input_active_high {
628 gpio-hog;
629 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200630 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200631 };
632 hog_output_low {
633 gpio-hog;
634 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200635 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200636 };
637 hog_output_high {
638 gpio-hog;
639 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200640 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200641 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100642 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600643
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100644 gpio_b: extra-gpios {
645 compatible = "sandbox,gpio";
646 gpio-controller;
647 #gpio-cells = <5>;
648 gpio-bank-name = "b";
649 sandbox,gpio-count = <10>;
650 };
651
652 gpio_c: pinmux-gpios {
653 compatible = "sandbox,gpio";
654 gpio-controller;
655 #gpio-cells = <2>;
656 gpio-bank-name = "c";
657 sandbox,gpio-count = <10>;
658 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100659 };
660
Simon Glassecc2ed52014-12-10 08:55:55 -0700661 i2c@0 {
662 #address-cells = <1>;
663 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600664 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700665 compatible = "sandbox,i2c";
666 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200667 pinctrl-names = "default";
668 pinctrl-0 = <&pinmux_i2c0_pins>;
669
Simon Glassecc2ed52014-12-10 08:55:55 -0700670 eeprom@2c {
671 reg = <0x2c>;
672 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700673 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200674 partitions {
675 compatible = "fixed-partitions";
676 #address-cells = <1>;
677 #size-cells = <1>;
678 bootcount_i2c: bootcount@10 {
679 reg = <10 2>;
680 };
681 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700682 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200683
Simon Glass52d3bc52015-05-22 15:42:17 -0600684 rtc_0: rtc@43 {
685 reg = <0x43>;
686 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700687 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600688 };
689
690 rtc_1: rtc@61 {
691 reg = <0x61>;
692 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700693 sandbox,emul = <&emul1>;
694 };
695
696 i2c_emul: emul {
697 reg = <0xff>;
698 compatible = "sandbox,i2c-emul-parent";
699 emul_eeprom: emul-eeprom {
700 compatible = "sandbox,i2c-eeprom";
701 sandbox,filename = "i2c.bin";
702 sandbox,size = <256>;
703 };
704 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700705 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700706 };
707 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700708 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600709 };
710 };
711
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200712 sandbox_pmic: sandbox_pmic {
713 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700714 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200715 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200716
717 mc34708: pmic@41 {
718 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700719 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200720 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700721 };
722
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100723 bootcount@0 {
724 compatible = "u-boot,bootcount-rtc";
725 rtc = <&rtc_1>;
726 offset = <0x13>;
727 };
728
Michal Simekf692b472020-05-28 11:48:55 +0200729 bootcount {
730 compatible = "u-boot,bootcount-i2c-eeprom";
731 i2c-eeprom = <&bootcount_i2c>;
732 };
733
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100734 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100735 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100736 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100737 vdd-supply = <&buck2>;
738 vss-microvolts = <0>;
739 };
740
Simon Glass02554352020-02-06 09:55:00 -0700741 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700742 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700743 interrupt-controller;
744 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700745 };
746
Simon Glass3c97c4f2016-01-18 19:52:26 -0700747 lcd {
748 u-boot,dm-pre-reloc;
749 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200750 pinctrl-names = "default";
751 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700752 xres = <1366>;
753 yres = <768>;
754 };
755
Simon Glass3c43fba2015-07-06 12:54:34 -0600756 leds {
757 compatible = "gpio-leds";
758
759 iracibble {
760 gpios = <&gpio_a 1 0>;
761 label = "sandbox:red";
762 };
763
764 martinet {
765 gpios = <&gpio_a 2 0>;
766 label = "sandbox:green";
767 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200768
769 default_on {
770 gpios = <&gpio_a 5 0>;
771 label = "sandbox:default_on";
772 default-state = "on";
773 };
774
775 default_off {
776 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400777 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200778 default-state = "off";
779 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600780 };
781
Stephen Warren8961b522016-05-16 17:41:37 -0600782 mbox: mbox {
783 compatible = "sandbox,mbox";
784 #mbox-cells = <1>;
785 };
786
787 mbox-test {
788 compatible = "sandbox,mbox-test";
789 mboxes = <&mbox 100>, <&mbox 1>;
790 mbox-names = "other", "test";
791 };
792
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900793 cpus {
Sean Anderson7616e362020-09-28 10:52:23 -0400794 timebase-frequency = <2000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900795 cpu-test1 {
Sean Anderson7616e362020-09-28 10:52:23 -0400796 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900797 compatible = "sandbox,cpu_sandbox";
798 u-boot,dm-pre-reloc;
799 };
Mario Sixfa44b532018-08-06 10:23:44 +0200800
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900801 cpu-test2 {
802 compatible = "sandbox,cpu_sandbox";
803 u-boot,dm-pre-reloc;
804 };
Mario Sixfa44b532018-08-06 10:23:44 +0200805
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900806 cpu-test3 {
807 compatible = "sandbox,cpu_sandbox";
808 u-boot,dm-pre-reloc;
809 };
Mario Sixfa44b532018-08-06 10:23:44 +0200810 };
811
Dave Gerlach21e3c212020-07-15 23:39:58 -0500812 chipid: chipid {
813 compatible = "sandbox,soc";
814 };
815
Simon Glasse96fa6c2018-12-10 10:37:34 -0700816 i2s: i2s {
817 compatible = "sandbox,i2s";
818 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700819 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700820 };
821
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200822 nop-test_0 {
823 compatible = "sandbox,nop_sandbox1";
824 nop-test_1 {
825 compatible = "sandbox,nop_sandbox2";
826 bind = "True";
827 };
828 nop-test_2 {
829 compatible = "sandbox,nop_sandbox2";
830 bind = "False";
831 };
832 };
833
Mario Six004e67c2018-07-31 14:24:14 +0200834 misc-test {
835 compatible = "sandbox,misc_sandbox";
836 };
837
Simon Glasse48eeb92017-04-23 20:02:07 -0600838 mmc2 {
839 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -0600840 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -0600841 };
842
843 mmc1 {
844 compatible = "sandbox,mmc";
845 };
846
847 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600848 compatible = "sandbox,mmc";
849 };
850
Simon Glassb45c8332019-02-16 20:24:50 -0700851 pch {
852 compatible = "sandbox,pch";
853 };
854
Tom Rini42c64d12020-02-11 12:41:23 -0500855 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700856 compatible = "sandbox,pci";
857 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500858 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700859 #address-cells = <3>;
860 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600861 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700862 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700863 pci@0,0 {
864 compatible = "pci-generic";
865 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600866 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700867 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300868 pci@1,0 {
869 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600870 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
871 reg = <0x02000814 0 0 0 0
872 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600873 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300874 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700875 p2sb-pci@2,0 {
876 compatible = "sandbox,p2sb";
877 reg = <0x02001010 0 0 0 0>;
878 sandbox,emul = <&p2sb_emul>;
879
880 adder {
881 intel,p2sb-port-id = <3>;
882 compatible = "sandbox,adder";
883 };
884 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700885 pci@1e,0 {
886 compatible = "sandbox,pmc";
887 reg = <0xf000 0 0 0 0>;
888 sandbox,emul = <&pmc_emul1e>;
889 acpi-base = <0x400>;
890 gpe0-dwx-mask = <0xf>;
891 gpe0-dwx-shift-base = <4>;
892 gpe0-dw = <6 7 9>;
893 gpe0-sts = <0x20>;
894 gpe0-en = <0x30>;
895 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700896 pci@1f,0 {
897 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600898 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
899 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600900 sandbox,emul = <&swap_case_emul0_1f>;
901 };
902 };
903
904 pci-emul0 {
905 compatible = "sandbox,pci-emul-parent";
906 swap_case_emul0_0: emul0@0,0 {
907 compatible = "sandbox,swap-case";
908 };
909 swap_case_emul0_1: emul0@1,0 {
910 compatible = "sandbox,swap-case";
911 use-ea;
912 };
913 swap_case_emul0_1f: emul0@1f,0 {
914 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700915 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700916 p2sb_emul: emul@2,0 {
917 compatible = "sandbox,p2sb-emul";
918 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700919 pmc_emul1e: emul@1e,0 {
920 compatible = "sandbox,pmc-emul";
921 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700922 };
923
Tom Rini42c64d12020-02-11 12:41:23 -0500924 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700925 compatible = "sandbox,pci";
926 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500927 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700928 #address-cells = <3>;
929 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700930 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
931 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
932 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700933 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200934 0x0c 0x00 0x1234 0x5678
935 0x10 0x00 0x1234 0x5678>;
936 pci@10,0 {
937 reg = <0x8000 0 0 0 0>;
938 };
Bin Mengdee4d752018-08-03 01:14:41 -0700939 };
940
Tom Rini42c64d12020-02-11 12:41:23 -0500941 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700942 compatible = "sandbox,pci";
943 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500944 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700945 #address-cells = <3>;
946 #size-cells = <2>;
947 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
948 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
949 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
950 pci@1f,0 {
951 compatible = "pci-generic";
952 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600953 sandbox,emul = <&swap_case_emul2_1f>;
954 };
955 };
956
957 pci-emul2 {
958 compatible = "sandbox,pci-emul-parent";
959 swap_case_emul2_1f: emul2@1f,0 {
960 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700961 };
962 };
963
Ramon Friedbb413332019-04-27 11:15:23 +0300964 pci_ep: pci_ep {
965 compatible = "sandbox,pci_ep";
966 };
967
Simon Glass98561572017-04-23 20:10:44 -0600968 probing {
969 compatible = "simple-bus";
970 test1 {
971 compatible = "denx,u-boot-probe-test";
972 };
973
974 test2 {
975 compatible = "denx,u-boot-probe-test";
976 };
977
978 test3 {
979 compatible = "denx,u-boot-probe-test";
980 };
981
982 test4 {
983 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100984 first-syscon = <&syscon0>;
985 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100986 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600987 };
988 };
989
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600990 pwrdom: power-domain {
991 compatible = "sandbox,power-domain";
992 #power-domain-cells = <1>;
993 };
994
995 power-domain-test {
996 compatible = "sandbox,power-domain-test";
997 power-domains = <&pwrdom 2>;
998 };
999
Simon Glass5d9a88f2018-10-01 12:22:40 -06001000 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001001 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001002 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001003 pinctrl-names = "default";
1004 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001005 };
1006
1007 pwm2 {
1008 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001009 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001010 };
1011
Simon Glass64ce0ca2015-07-06 12:54:31 -06001012 ram {
1013 compatible = "sandbox,ram";
1014 };
1015
Simon Glass5010d982015-07-06 12:54:29 -06001016 reset@0 {
1017 compatible = "sandbox,warm-reset";
1018 };
1019
1020 reset@1 {
1021 compatible = "sandbox,reset";
1022 };
1023
Stephen Warren4581b712016-06-17 09:43:59 -06001024 resetc: reset-ctl {
1025 compatible = "sandbox,reset-ctl";
1026 #reset-cells = <1>;
1027 };
1028
1029 reset-ctl-test {
1030 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001031 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1032 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001033 };
1034
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301035 rng {
1036 compatible = "sandbox,sandbox-rng";
1037 };
1038
Nishanth Menon52159402015-09-17 15:42:41 -05001039 rproc_1: rproc@1 {
1040 compatible = "sandbox,test-processor";
1041 remoteproc-name = "remoteproc-test-dev1";
1042 };
1043
1044 rproc_2: rproc@2 {
1045 compatible = "sandbox,test-processor";
1046 internal-memory-mapped;
1047 remoteproc-name = "remoteproc-test-dev2";
1048 };
1049
Simon Glass5d9a88f2018-10-01 12:22:40 -06001050 panel {
1051 compatible = "simple-panel";
1052 backlight = <&backlight 0 100>;
1053 };
1054
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001055 smem@0 {
1056 compatible = "sandbox,smem";
1057 };
1058
Simon Glassd4901892018-12-10 10:37:36 -07001059 sound {
1060 compatible = "sandbox,sound";
1061 cpu {
1062 sound-dai = <&i2s 0>;
1063 };
1064
1065 codec {
1066 sound-dai = <&audio 0>;
1067 };
1068 };
1069
Simon Glass0ae0cb72014-10-13 23:42:11 -06001070 spi@0 {
1071 #address-cells = <1>;
1072 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001073 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001074 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001075 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001076 pinctrl-names = "default";
1077 pinctrl-0 = <&pinmux_spi0_pins>;
1078
Simon Glass0ae0cb72014-10-13 23:42:11 -06001079 spi.bin@0 {
1080 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001081 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001082 spi-max-frequency = <40000000>;
1083 sandbox,filename = "spi.bin";
1084 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001085 spi.bin@1 {
1086 reg = <1>;
1087 compatible = "spansion,m25p16", "jedec,spi-nor";
1088 spi-max-frequency = <50000000>;
1089 sandbox,filename = "spi.bin";
1090 spi-cpol;
1091 spi-cpha;
1092 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001093 };
1094
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001095 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001096 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001097 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001098 };
1099
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001100 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001101 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001102 reg = <0x20 5
1103 0x28 6
1104 0x30 7
1105 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001106 };
1107
Patrick Delaunaya442e612019-03-07 09:57:13 +01001108 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001109 compatible = "simple-mfd", "syscon";
1110 reg = <0x40 5
1111 0x48 6
1112 0x50 7
1113 0x58 8>;
1114 };
1115
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301116 syscon3: syscon@3 {
1117 compatible = "simple-mfd", "syscon";
1118 reg = <0x000100 0x10>;
1119
1120 muxcontroller0: a-mux-controller {
1121 compatible = "mmio-mux";
1122 #mux-control-cells = <1>;
1123
1124 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1125 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1126 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1127 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1128 u-boot,mux-autoprobe;
1129 };
1130 };
1131
1132 muxcontroller1: emul-mux-controller {
1133 compatible = "mux-emul";
1134 #mux-control-cells = <0>;
1135 u-boot,mux-autoprobe;
1136 idle-state = <0xabcd>;
1137 };
1138
Simon Glass93f44e82020-12-16 21:20:27 -07001139 testfdtm0 {
1140 compatible = "denx,u-boot-fdtm-test";
1141 };
1142
1143 testfdtm1: testfdtm1 {
1144 compatible = "denx,u-boot-fdtm-test";
1145 };
1146
1147 testfdtm2 {
1148 compatible = "denx,u-boot-fdtm-test";
1149 };
1150
Sean Anderson7616e362020-09-28 10:52:23 -04001151 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001152 compatible = "sandbox,timer";
1153 clock-frequency = <1000000>;
1154 };
1155
Sean Anderson7616e362020-09-28 10:52:23 -04001156 timer@1 {
1157 compatible = "sandbox,timer";
1158 sandbox,timebase-frequency-fallback;
1159 };
1160
Miquel Raynalb91ad162018-05-15 11:57:27 +02001161 tpm2 {
1162 compatible = "sandbox,tpm2";
1163 };
1164
Simon Glass171e9912015-05-22 15:42:15 -06001165 uart0: serial {
1166 compatible = "sandbox,serial";
1167 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001168 pinctrl-names = "default";
1169 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001170 };
1171
Simon Glasse00cb222015-03-25 12:23:05 -06001172 usb_0: usb@0 {
1173 compatible = "sandbox,usb";
1174 status = "disabled";
1175 hub {
1176 compatible = "sandbox,usb-hub";
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1179 flash-stick {
1180 reg = <0>;
1181 compatible = "sandbox,usb-flash";
1182 };
1183 };
1184 };
1185
1186 usb_1: usb@1 {
1187 compatible = "sandbox,usb";
1188 hub {
1189 compatible = "usb-hub";
1190 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001191 #address-cells = <1>;
1192 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001193 hub-emul {
1194 compatible = "sandbox,usb-hub";
1195 #address-cells = <1>;
1196 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001197 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001198 reg = <0>;
1199 compatible = "sandbox,usb-flash";
1200 sandbox,filepath = "testflash.bin";
1201 };
1202
Simon Glass431cbd62015-11-08 23:48:01 -07001203 flash-stick@1 {
1204 reg = <1>;
1205 compatible = "sandbox,usb-flash";
1206 sandbox,filepath = "testflash1.bin";
1207 };
1208
1209 flash-stick@2 {
1210 reg = <2>;
1211 compatible = "sandbox,usb-flash";
1212 sandbox,filepath = "testflash2.bin";
1213 };
1214
Simon Glassbff1a712015-11-08 23:48:08 -07001215 keyb@3 {
1216 reg = <3>;
1217 compatible = "sandbox,usb-keyb";
1218 };
1219
Simon Glasse00cb222015-03-25 12:23:05 -06001220 };
Michael Wallec03b7612020-06-02 01:47:07 +02001221
1222 usbstor@1 {
1223 reg = <1>;
1224 };
1225 usbstor@3 {
1226 reg = <3>;
1227 };
Simon Glasse00cb222015-03-25 12:23:05 -06001228 };
1229 };
1230
1231 usb_2: usb@2 {
1232 compatible = "sandbox,usb";
1233 status = "disabled";
1234 };
1235
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001236 spmi: spmi@0 {
1237 compatible = "sandbox,spmi";
1238 #address-cells = <0x1>;
1239 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001240 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001241 pm8916@0 {
1242 compatible = "qcom,spmi-pmic";
1243 reg = <0x0 0x1>;
1244 #address-cells = <0x1>;
1245 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001246 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001247
1248 spmi_gpios: gpios@c000 {
1249 compatible = "qcom,pm8916-gpio";
1250 reg = <0xc000 0x400>;
1251 gpio-controller;
1252 gpio-count = <4>;
1253 #gpio-cells = <2>;
1254 gpio-bank-name="spmi";
1255 };
1256 };
1257 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001258
1259 wdt0: wdt@0 {
1260 compatible = "sandbox,wdt";
1261 };
Rob Clarkf2006802018-01-10 11:33:30 +01001262
Mario Six957983e2018-08-09 14:51:19 +02001263 axi: axi@0 {
1264 compatible = "sandbox,axi";
1265 #address-cells = <0x1>;
1266 #size-cells = <0x1>;
1267 store@0 {
1268 compatible = "sandbox,sandbox_store";
1269 reg = <0x0 0x400>;
1270 };
1271 };
1272
Rob Clarkf2006802018-01-10 11:33:30 +01001273 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001274 #address-cells = <1>;
1275 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001276 setting = "sunrise ohoka";
1277 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001278 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001279 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001280 chosen-test {
1281 compatible = "denx,u-boot-fdt-test";
1282 reg = <9 1>;
1283 };
1284 };
Mario Sixe8d52912018-03-12 14:53:33 +01001285
1286 translation-test@8000 {
1287 compatible = "simple-bus";
1288 reg = <0x8000 0x4000>;
1289
1290 #address-cells = <0x2>;
1291 #size-cells = <0x1>;
1292
1293 ranges = <0 0x0 0x8000 0x1000
1294 1 0x100 0x9000 0x1000
1295 2 0x200 0xA000 0x1000
1296 3 0x300 0xB000 0x1000
1297 >;
1298
Fabien Dessenne641067f2019-05-31 15:11:30 +02001299 dma-ranges = <0 0x000 0x10000000 0x1000
1300 1 0x100 0x20000000 0x1000
1301 >;
1302
Mario Sixe8d52912018-03-12 14:53:33 +01001303 dev@0,0 {
1304 compatible = "denx,u-boot-fdt-dummy";
1305 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001306 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001307 };
1308
1309 dev@1,100 {
1310 compatible = "denx,u-boot-fdt-dummy";
1311 reg = <1 0x100 0x1000>;
1312
1313 };
1314
1315 dev@2,200 {
1316 compatible = "denx,u-boot-fdt-dummy";
1317 reg = <2 0x200 0x1000>;
1318 };
1319
1320
1321 noxlatebus@3,300 {
1322 compatible = "simple-bus";
1323 reg = <3 0x300 0x1000>;
1324
1325 #address-cells = <0x1>;
1326 #size-cells = <0x0>;
1327
1328 dev@42 {
1329 compatible = "denx,u-boot-fdt-dummy";
1330 reg = <0x42>;
1331 };
1332 };
1333 };
Mario Six4eea5312018-09-27 09:19:31 +02001334
1335 osd {
1336 compatible = "sandbox,sandbox_osd";
1337 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001338
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001339 sandbox_tee {
1340 compatible = "sandbox,tee";
1341 };
Bin Meng4f89d492018-10-15 02:21:26 -07001342
1343 sandbox_virtio1 {
1344 compatible = "sandbox,virtio1";
1345 };
1346
1347 sandbox_virtio2 {
1348 compatible = "sandbox,virtio2";
1349 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001350
Etienne Carriere87d4f272020-09-09 18:44:05 +02001351 sandbox_scmi {
1352 compatible = "sandbox,scmi-devices";
1353 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001354 resets = <&reset_scmi0 3>;
Etienne Carriere01242182021-03-08 22:38:07 +01001355 regul0-supply = <&regul0_scmi0>;
1356 regul1-supply = <&regul1_scmi0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001357 };
1358
Patrice Chotardf41a8242018-10-24 14:10:23 +02001359 pinctrl {
1360 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001361
Sean Anderson7f0f1802020-09-14 11:01:57 -04001362 pinctrl-names = "default", "alternate";
1363 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1364 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001365
Sean Anderson7f0f1802020-09-14 11:01:57 -04001366 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001367 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001368 pins = "P5";
1369 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001370 bias-pull-up;
1371 input-disable;
1372 };
1373 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001374 pins = "P6";
1375 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001376 output-high;
1377 drive-open-drain;
1378 };
1379 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001380 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001381 bias-pull-down;
1382 input-enable;
1383 };
1384 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001385 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001386 bias-disable;
1387 };
1388 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001389
1390 pinctrl_i2c: i2c {
1391 groups {
1392 groups = "I2C_UART";
1393 function = "I2C";
1394 };
1395
1396 pins {
1397 pins = "P0", "P1";
1398 drive-open-drain;
1399 };
1400 };
1401
1402 pinctrl_i2s: i2s {
1403 groups = "SPI_I2S";
1404 function = "I2S";
1405 };
1406
1407 pinctrl_spi: spi {
1408 groups = "SPI_I2S";
1409 function = "SPI";
1410
1411 cs {
1412 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1413 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1414 };
1415 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001416 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001417
Dario Binacchi55322622021-04-11 09:39:50 +02001418 pinctrl-single-no-width {
1419 compatible = "pinctrl-single";
1420 reg = <0x0000 0x238>;
1421 #pinctrl-cells = <1>;
1422 pinctrl-single,function-mask = <0x7f>;
1423 };
1424
1425 pinctrl-single-pins {
1426 compatible = "pinctrl-single";
1427 reg = <0x0000 0x238>;
1428 #pinctrl-cells = <1>;
1429 pinctrl-single,register-width = <32>;
1430 pinctrl-single,function-mask = <0x7f>;
1431
1432 pinmux_pwm_pins: pinmux_pwm_pins {
1433 pinctrl-single,pins = < 0x48 0x06 >;
1434 };
1435
1436 pinmux_spi0_pins: pinmux_spi0_pins {
1437 pinctrl-single,pins = <
1438 0x190 0x0c
1439 0x194 0x0c
1440 0x198 0x23
1441 0x19c 0x0c
1442 >;
1443 };
1444
1445 pinmux_uart0_pins: pinmux_uart0_pins {
1446 pinctrl-single,pins = <
1447 0x70 0x30
1448 0x74 0x00
1449 >;
1450 };
1451 };
1452
1453 pinctrl-single-bits {
1454 compatible = "pinctrl-single";
1455 reg = <0x0000 0x50>;
1456 #pinctrl-cells = <2>;
1457 pinctrl-single,bit-per-mux;
1458 pinctrl-single,register-width = <32>;
1459 pinctrl-single,function-mask = <0xf>;
1460
1461 pinmux_i2c0_pins: pinmux_i2c0_pins {
1462 pinctrl-single,bits = <
1463 0x10 0x00002200 0x0000ff00
1464 >;
1465 };
1466
1467 pinmux_lcd_pins: pinmux_lcd_pins {
1468 pinctrl-single,bits = <
1469 0x40 0x22222200 0xffffff00
1470 0x44 0x22222222 0xffffffff
1471 0x48 0x00000022 0x000000ff
1472 0x48 0x02000000 0x0f000000
1473 0x4c 0x02000022 0x0f0000ff
1474 >;
1475 };
1476 };
1477
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001478 hwspinlock@0 {
1479 compatible = "sandbox,hwspinlock";
1480 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001481
1482 dma: dma {
1483 compatible = "sandbox,dma";
1484 #dma-cells = <1>;
1485
1486 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1487 dma-names = "m2m", "tx0", "rx0";
1488 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001489
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001490 /*
1491 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1492 * end of the test. If parent mdio is removed first, clean-up of the
1493 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1494 * active at the end of the test. That it turn doesn't allow the mdio
1495 * class to be destroyed, triggering an error.
1496 */
1497 mdio-mux-test {
1498 compatible = "sandbox,mdio-mux";
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1501 mdio-parent-bus = <&mdio>;
1502
1503 mdio-ch-test@0 {
1504 reg = <0>;
1505 };
1506 mdio-ch-test@1 {
1507 reg = <1>;
1508 };
1509 };
1510
1511 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001512 compatible = "sandbox,mdio";
1513 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001514
1515 pm-bus-test {
1516 compatible = "simple-pm-bus";
1517 clocks = <&clk_sandbox 4>;
1518 power-domains = <&pwrdom 1>;
1519 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001520
1521 resetc2: syscon-reset {
1522 compatible = "syscon-reset";
1523 #reset-cells = <1>;
1524 regmap = <&syscon0>;
1525 offset = <1>;
1526 mask = <0x27FFFFFF>;
1527 assert-high = <0>;
1528 };
1529
1530 syscon-reset-test {
1531 compatible = "sandbox,misc_sandbox";
1532 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1533 reset-names = "valid", "no_mask", "out_of_range";
1534 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301535
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001536 sysinfo {
1537 compatible = "sandbox,sysinfo-sandbox";
1538 };
1539
Sean Anderson1cbfed82021-04-20 10:50:58 -04001540 sysinfo-gpio {
1541 compatible = "gpio-sysinfo";
1542 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1543 revisions = <19>, <5>;
1544 names = "rev_a", "foo";
1545 };
1546
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301547 some_regmapped-bus {
1548 #address-cells = <0x1>;
1549 #size-cells = <0x1>;
1550
1551 ranges = <0x0 0x0 0x10>;
1552 compatible = "simple-bus";
1553
1554 regmap-test_0 {
1555 reg = <0 0x10>;
1556 compatible = "sandbox,regmap_test";
1557 };
1558 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001559};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001560
1561#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001562#include "cros-ec-keyboard.dtsi"