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Simon Glass2e7d35d2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +01008
Simon Glass2e7d35d2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070014
Simon Glass00606d72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Simon Glass171e9912015-05-22 15:42:15 -060017 eth0 = "/eth@10002000";
Claudiu Manoilff98da02021-03-14 20:14:57 +080018 eth2 = &swp_0;
Bin Meng71d79712015-08-27 22:25:53 -070019 eth3 = &eth_3;
Claudiu Manoilff98da02021-03-14 20:14:57 +080020 eth4 = &dsa_eth0;
Simon Glass171e9912015-05-22 15:42:15 -060021 eth5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060022 gpio1 = &gpio_a;
23 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010024 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070025 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060026 mmc0 = "/mmc0";
27 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070028 pci0 = &pci0;
29 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070030 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020031 remoteproc0 = &rproc_1;
32 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060033 rtc0 = &rtc_0;
34 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060035 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020036 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070037 testbus3 = "/some-bus";
38 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070039 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070040 testfdt3 = "/b-test";
41 testfdt5 = "/some-bus/c-test@5";
42 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070043 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020044 fdt-dummy0 = "/translation-test@8000/dev@0,0";
45 fdt-dummy1 = "/translation-test@8000/dev@1,100";
46 fdt-dummy2 = "/translation-test@8000/dev@2,200";
47 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchid64b9cd2020-12-30 00:16:21 +010048 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glasse00cb222015-03-25 12:23:05 -060049 usb0 = &usb_0;
50 usb1 = &usb_1;
51 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020052 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020053 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060054 };
55
Simon Glassce6d99a2018-12-10 10:37:33 -070056 audio: audio-codec {
57 compatible = "sandbox,audio-codec";
58 #sound-dai-cells = <1>;
59 };
60
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020061 buttons {
62 compatible = "gpio-keys";
63
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020064 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020065 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020066 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020067 };
68
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020069 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020070 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +020071 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020072 };
73 };
74
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010075 buttons2 {
76 compatible = "adc-keys";
77 io-channels = <&adc 3>;
78 keyup-threshold-microvolt = <3000000>;
79
80 button-up {
81 label = "button3";
82 linux,code = <KEY_F3>;
83 press-threshold-microvolt = <1500000>;
84 };
85
86 button-down {
87 label = "button4";
88 linux,code = <KEY_F4>;
89 press-threshold-microvolt = <1000000>;
90 };
91
92 button-enter {
93 label = "button5";
94 linux,code = <KEY_F5>;
95 press-threshold-microvolt = <500000>;
96 };
97 };
98
Simon Glasse96fa6c2018-12-10 10:37:34 -070099 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600100 reg = <0 0>;
101 compatible = "google,cros-ec-sandbox";
102
103 /*
104 * This describes the flash memory within the EC. Note
105 * that the STM32L flash erases to 0, not 0xff.
106 */
107 flash {
108 image-pos = <0x08000000>;
109 size = <0x20000>;
110 erase-value = <0>;
111
112 /* Information for sandbox */
113 ro {
114 image-pos = <0>;
115 size = <0xf000>;
116 };
117 wp-ro {
118 image-pos = <0xf000>;
119 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700120 used = <0x884>;
121 compress = "lz4";
122 uncomp-size = <0xcf8>;
123 hash {
124 algo = "sha256";
125 value = [00 01 02 03 04 05 06 07
126 08 09 0a 0b 0c 0d 0e 0f
127 10 11 12 13 14 15 16 17
128 18 19 1a 1b 1c 1d 1e 1f];
129 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600130 };
131 rw {
132 image-pos = <0x10000>;
133 size = <0x10000>;
134 };
135 };
136 };
137
Yannick Fertré23f965a2019-10-07 15:29:05 +0200138 dsi_host: dsi_host {
139 compatible = "sandbox,dsi-host";
140 };
141
Simon Glass2e7d35d2014-02-26 15:59:21 -0700142 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600143 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700144 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600145 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700146 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600147 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100148 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
149 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700150 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100151 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
152 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
153 <&gpio_b 7 GPIO_IN 3 2 1>,
154 <&gpio_b 8 GPIO_OUT 3 2 1>,
155 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100156 test3-gpios =
157 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
158 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
159 <&gpio_c 2 GPIO_OUT>,
160 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
161 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200162 <&gpio_c 5 GPIO_IN>,
163 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
164 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530165 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
166 test5-gpios = <&gpio_a 19>;
167
Simon Glassa1b17e42018-12-10 10:37:37 -0700168 int-value = <1234>;
169 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200170 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200171 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600172 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700173 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600174 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200175 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530176
177 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
178 <&muxcontroller0 2>, <&muxcontroller0 3>,
179 <&muxcontroller1>;
180 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
181 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100182 display-timings {
183 timing0: 240x320 {
184 clock-frequency = <6500000>;
185 hactive = <240>;
186 vactive = <320>;
187 hfront-porch = <6>;
188 hback-porch = <7>;
189 hsync-len = <1>;
190 vback-porch = <5>;
191 vfront-porch = <8>;
192 vsync-len = <2>;
193 hsync-active = <1>;
194 vsync-active = <0>;
195 de-active = <1>;
196 pixelclk-active = <1>;
197 interlaced;
198 doublescan;
199 doubleclk;
200 };
201 timing1: 480x800 {
202 clock-frequency = <9000000>;
203 hactive = <480>;
204 vactive = <800>;
205 hfront-porch = <10>;
206 hback-porch = <59>;
207 hsync-len = <12>;
208 vback-porch = <15>;
209 vfront-porch = <17>;
210 vsync-len = <16>;
211 hsync-active = <0>;
212 vsync-active = <1>;
213 de-active = <0>;
214 pixelclk-active = <0>;
215 };
216 timing2: 800x480 {
217 clock-frequency = <33500000>;
218 hactive = <800>;
219 vactive = <480>;
220 hback-porch = <89>;
221 hfront-porch = <164>;
222 vback-porch = <23>;
223 vfront-porch = <10>;
224 hsync-len = <11>;
225 vsync-len = <13>;
226 };
227 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700228 };
229
230 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600231 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700232 compatible = "not,compatible";
233 };
234
235 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600236 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700237 };
238
Simon Glass5d9a88f2018-10-01 12:22:40 -0600239 backlight: backlight {
240 compatible = "pwm-backlight";
241 enable-gpios = <&gpio_a 1>;
242 power-supply = <&ldo_1>;
243 pwms = <&pwm 0 1000>;
244 default-brightness-level = <5>;
245 brightness-levels = <0 16 32 64 128 170 202 234 255>;
246 };
247
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200248 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200249 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200250 bind-test-child1 {
251 compatible = "sandbox,phy";
252 #phy-cells = <1>;
253 };
254
255 bind-test-child2 {
256 compatible = "simple-bus";
257 };
258 };
259
Simon Glass2e7d35d2014-02-26 15:59:21 -0700260 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600261 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700262 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600263 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700264 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530265
266 mux-controls = <&muxcontroller0 0>;
267 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700268 };
269
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200270 phy_provider0: gen_phy@0 {
271 compatible = "sandbox,phy";
272 #phy-cells = <1>;
273 };
274
275 phy_provider1: gen_phy@1 {
276 compatible = "sandbox,phy";
277 #phy-cells = <0>;
278 broken;
279 };
280
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200281 phy_provider2: gen_phy@2 {
282 compatible = "sandbox,phy";
283 #phy-cells = <0>;
284 };
285
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200286 gen_phy_user: gen_phy_user {
287 compatible = "simple-bus";
288 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
289 phy-names = "phy1", "phy2", "phy3";
290 };
291
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200292 gen_phy_user1: gen_phy_user1 {
293 compatible = "simple-bus";
294 phys = <&phy_provider0 0>, <&phy_provider2>;
295 phy-names = "phy1", "phy2";
296 };
297
Simon Glass2e7d35d2014-02-26 15:59:21 -0700298 some-bus {
299 #address-cells = <1>;
300 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600301 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600302 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600303 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700304 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600305 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700306 compatible = "denx,u-boot-fdt-test";
307 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600308 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700309 ping-add = <5>;
310 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600311 c-test@0 {
312 compatible = "denx,u-boot-fdt-test";
313 reg = <0>;
314 ping-expect = <6>;
315 ping-add = <6>;
316 };
317 c-test@1 {
318 compatible = "denx,u-boot-fdt-test";
319 reg = <1>;
320 ping-expect = <7>;
321 ping-add = <7>;
322 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700323 };
324
325 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600326 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600327 ping-expect = <6>;
328 ping-add = <6>;
329 compatible = "google,another-fdt-test";
330 };
331
332 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600333 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600334 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700335 ping-add = <6>;
336 compatible = "google,another-fdt-test";
337 };
338
Simon Glass9cc36a22015-01-25 08:27:05 -0700339 f-test {
340 compatible = "denx,u-boot-fdt-test";
341 };
342
343 g-test {
344 compatible = "denx,u-boot-fdt-test";
345 };
346
Bin Meng2786cd72018-10-10 22:07:01 -0700347 h-test {
348 compatible = "denx,u-boot-fdt-test1";
349 };
350
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200351 i-test {
352 compatible = "mediatek,u-boot-fdt-test";
353 #address-cells = <1>;
354 #size-cells = <0>;
355
356 subnode@0 {
357 reg = <0>;
358 };
359
360 subnode@1 {
361 reg = <1>;
362 };
363
364 subnode@2 {
365 reg = <2>;
366 };
367 };
368
Simon Glassdc12ebb2019-12-29 21:19:25 -0700369 devres-test {
370 compatible = "denx,u-boot-devres-test";
371 };
372
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530373 another-test {
374 reg = <0 2>;
375 compatible = "denx,u-boot-fdt-test";
376 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
377 test5-gpios = <&gpio_a 19>;
378 };
379
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100380 mmio-bus@0 {
381 #address-cells = <1>;
382 #size-cells = <1>;
383 compatible = "denx,u-boot-test-bus";
384 dma-ranges = <0x10000000 0x00000000 0x00040000>;
385
386 subnode@0 {
387 compatible = "denx,u-boot-fdt-test";
388 };
389 };
390
391 mmio-bus@1 {
392 #address-cells = <1>;
393 #size-cells = <1>;
394 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100395
396 subnode@0 {
397 compatible = "denx,u-boot-fdt-test";
398 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100399 };
400
Simon Glass0f7b1112020-07-07 13:12:06 -0600401 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600402 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600403 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600404 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600405 child {
406 compatible = "denx,u-boot-acpi-test";
407 };
Simon Glassf50cc952020-04-08 16:57:34 -0600408 };
409
Simon Glass0f7b1112020-07-07 13:12:06 -0600410 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600411 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600412 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600413 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600414 };
415
Patrice Chotardee87a092017-09-04 14:55:57 +0200416 clocks {
417 clk_fixed: clk-fixed {
418 compatible = "fixed-clock";
419 #clock-cells = <0>;
420 clock-frequency = <1234>;
421 };
Anup Patelb630d572019-02-25 08:14:55 +0000422
423 clk_fixed_factor: clk-fixed-factor {
424 compatible = "fixed-factor-clock";
425 #clock-cells = <0>;
426 clock-div = <3>;
427 clock-mult = <2>;
428 clocks = <&clk_fixed>;
429 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200430
431 osc {
432 compatible = "fixed-clock";
433 #clock-cells = <0>;
434 clock-frequency = <20000000>;
435 };
Stephen Warren135aa952016-06-17 09:44:00 -0600436 };
437
438 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600439 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600440 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200441 assigned-clocks = <&clk_sandbox 3>;
442 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600443 };
444
445 clk-test {
446 compatible = "sandbox,clk-test";
447 clocks = <&clk_fixed>,
448 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200449 <&clk_sandbox 0>,
450 <&clk_sandbox 3>,
451 <&clk_sandbox 2>;
452 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600453 };
454
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200455 ccf: clk-ccf {
456 compatible = "sandbox,clk-ccf";
457 };
458
Simon Glass171e9912015-05-22 15:42:15 -0600459 eth@10002000 {
460 compatible = "sandbox,eth";
461 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500462 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600463 };
464
465 eth_5: eth@10003000 {
466 compatible = "sandbox,eth";
467 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500468 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600469 };
470
Bin Meng71d79712015-08-27 22:25:53 -0700471 eth_3: sbe5 {
472 compatible = "sandbox,eth";
473 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500474 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700475 };
476
Simon Glass171e9912015-05-22 15:42:15 -0600477 eth@10004000 {
478 compatible = "sandbox,eth";
479 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500480 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600481 };
482
Claudiu Manoilff98da02021-03-14 20:14:57 +0800483 dsa_eth0: dsa-test-eth {
484 compatible = "sandbox,eth";
485 reg = <0x10006000 0x1000>;
486 fake-host-hwaddr = [00 00 66 44 22 66];
487 };
488
489 dsa-test {
490 compatible = "sandbox,dsa";
491
492 ports {
493 #address-cells = <1>;
494 #size-cells = <0>;
495 swp_0: port@0 {
496 reg = <0>;
497 label = "lan0";
498 phy-mode = "rgmii-rxid";
499
500 fixed-link {
501 speed = <100>;
502 full-duplex;
503 };
504 };
505
506 swp_1: port@1 {
507 reg = <1>;
508 label = "lan1";
509 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800510 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800511 };
512
513 port@2 {
514 reg = <2>;
515 ethernet = <&dsa_eth0>;
516
517 fixed-link {
518 speed = <1000>;
519 full-duplex;
520 };
521 };
522 };
523 };
524
Rajan Vaja31b82172018-09-19 03:43:46 -0700525 firmware {
526 sandbox_firmware: sandbox-firmware {
527 compatible = "sandbox,firmware";
528 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200529
530 sandbox-scmi-agent@0 {
531 compatible = "sandbox,scmi-agent";
532 #address-cells = <1>;
533 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200534
535 clk_scmi0: protocol@14 {
536 reg = <0x14>;
537 #clock-cells = <1>;
538 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200539
540 reset_scmi0: protocol@16 {
541 reg = <0x16>;
542 #reset-cells = <1>;
543 };
Etienne Carriere01242182021-03-08 22:38:07 +0100544
545 protocol@17 {
546 reg = <0x17>;
547
548 regulators {
549 #address-cells = <1>;
550 #size-cells = <0>;
551
552 regul0_scmi0: reg@0 {
553 reg = <0>;
554 regulator-name = "sandbox-voltd0";
555 regulator-min-microvolt = <1100000>;
556 regulator-max-microvolt = <3300000>;
557 };
558 regul1_scmi0: reg@1 {
559 reg = <0x1>;
560 regulator-name = "sandbox-voltd1";
561 regulator-min-microvolt = <1800000>;
562 };
563 };
564 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200565 };
566
567 sandbox-scmi-agent@1 {
568 compatible = "sandbox,scmi-agent";
569 #address-cells = <1>;
570 #size-cells = <0>;
571
Etienne Carriere87d4f272020-09-09 18:44:05 +0200572 clk_scmi1: protocol@14 {
573 reg = <0x14>;
574 #clock-cells = <1>;
575 };
576
Etienne Carriere358599e2020-09-09 18:44:00 +0200577 protocol@10 {
578 reg = <0x10>;
579 };
580 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700581 };
582
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100583 pinctrl-gpio {
584 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700585
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100586 gpio_a: base-gpios {
587 compatible = "sandbox,gpio";
588 gpio-controller;
589 #gpio-cells = <1>;
590 gpio-bank-name = "a";
591 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200592 hog_input_active_low {
593 gpio-hog;
594 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200595 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200596 };
597 hog_input_active_high {
598 gpio-hog;
599 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200600 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200601 };
602 hog_output_low {
603 gpio-hog;
604 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200605 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200606 };
607 hog_output_high {
608 gpio-hog;
609 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200610 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200611 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100612 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600613
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100614 gpio_b: extra-gpios {
615 compatible = "sandbox,gpio";
616 gpio-controller;
617 #gpio-cells = <5>;
618 gpio-bank-name = "b";
619 sandbox,gpio-count = <10>;
620 };
621
622 gpio_c: pinmux-gpios {
623 compatible = "sandbox,gpio";
624 gpio-controller;
625 #gpio-cells = <2>;
626 gpio-bank-name = "c";
627 sandbox,gpio-count = <10>;
628 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100629 };
630
Simon Glassecc2ed52014-12-10 08:55:55 -0700631 i2c@0 {
632 #address-cells = <1>;
633 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600634 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700635 compatible = "sandbox,i2c";
636 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200637 pinctrl-names = "default";
638 pinctrl-0 = <&pinmux_i2c0_pins>;
639
Simon Glassecc2ed52014-12-10 08:55:55 -0700640 eeprom@2c {
641 reg = <0x2c>;
642 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700643 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200644 partitions {
645 compatible = "fixed-partitions";
646 #address-cells = <1>;
647 #size-cells = <1>;
648 bootcount_i2c: bootcount@10 {
649 reg = <10 2>;
650 };
651 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700652 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200653
Simon Glass52d3bc52015-05-22 15:42:17 -0600654 rtc_0: rtc@43 {
655 reg = <0x43>;
656 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700657 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600658 };
659
660 rtc_1: rtc@61 {
661 reg = <0x61>;
662 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700663 sandbox,emul = <&emul1>;
664 };
665
666 i2c_emul: emul {
667 reg = <0xff>;
668 compatible = "sandbox,i2c-emul-parent";
669 emul_eeprom: emul-eeprom {
670 compatible = "sandbox,i2c-eeprom";
671 sandbox,filename = "i2c.bin";
672 sandbox,size = <256>;
673 };
674 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700675 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700676 };
677 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700678 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600679 };
680 };
681
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200682 sandbox_pmic: sandbox_pmic {
683 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700684 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200685 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200686
687 mc34708: pmic@41 {
688 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700689 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200690 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700691 };
692
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100693 bootcount@0 {
694 compatible = "u-boot,bootcount-rtc";
695 rtc = <&rtc_1>;
696 offset = <0x13>;
697 };
698
Michal Simekf692b472020-05-28 11:48:55 +0200699 bootcount {
700 compatible = "u-boot,bootcount-i2c-eeprom";
701 i2c-eeprom = <&bootcount_i2c>;
702 };
703
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100704 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100705 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100706 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100707 vdd-supply = <&buck2>;
708 vss-microvolts = <0>;
709 };
710
Simon Glass02554352020-02-06 09:55:00 -0700711 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700712 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700713 interrupt-controller;
714 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700715 };
716
Simon Glass3c97c4f2016-01-18 19:52:26 -0700717 lcd {
718 u-boot,dm-pre-reloc;
719 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200720 pinctrl-names = "default";
721 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700722 xres = <1366>;
723 yres = <768>;
724 };
725
Simon Glass3c43fba2015-07-06 12:54:34 -0600726 leds {
727 compatible = "gpio-leds";
728
729 iracibble {
730 gpios = <&gpio_a 1 0>;
731 label = "sandbox:red";
732 };
733
734 martinet {
735 gpios = <&gpio_a 2 0>;
736 label = "sandbox:green";
737 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200738
739 default_on {
740 gpios = <&gpio_a 5 0>;
741 label = "sandbox:default_on";
742 default-state = "on";
743 };
744
745 default_off {
746 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400747 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200748 default-state = "off";
749 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600750 };
751
Stephen Warren8961b522016-05-16 17:41:37 -0600752 mbox: mbox {
753 compatible = "sandbox,mbox";
754 #mbox-cells = <1>;
755 };
756
757 mbox-test {
758 compatible = "sandbox,mbox-test";
759 mboxes = <&mbox 100>, <&mbox 1>;
760 mbox-names = "other", "test";
761 };
762
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900763 cpus {
Sean Anderson7616e362020-09-28 10:52:23 -0400764 timebase-frequency = <2000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900765 cpu-test1 {
Sean Anderson7616e362020-09-28 10:52:23 -0400766 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900767 compatible = "sandbox,cpu_sandbox";
768 u-boot,dm-pre-reloc;
769 };
Mario Sixfa44b532018-08-06 10:23:44 +0200770
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900771 cpu-test2 {
772 compatible = "sandbox,cpu_sandbox";
773 u-boot,dm-pre-reloc;
774 };
Mario Sixfa44b532018-08-06 10:23:44 +0200775
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900776 cpu-test3 {
777 compatible = "sandbox,cpu_sandbox";
778 u-boot,dm-pre-reloc;
779 };
Mario Sixfa44b532018-08-06 10:23:44 +0200780 };
781
Dave Gerlach21e3c212020-07-15 23:39:58 -0500782 chipid: chipid {
783 compatible = "sandbox,soc";
784 };
785
Simon Glasse96fa6c2018-12-10 10:37:34 -0700786 i2s: i2s {
787 compatible = "sandbox,i2s";
788 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700789 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700790 };
791
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200792 nop-test_0 {
793 compatible = "sandbox,nop_sandbox1";
794 nop-test_1 {
795 compatible = "sandbox,nop_sandbox2";
796 bind = "True";
797 };
798 nop-test_2 {
799 compatible = "sandbox,nop_sandbox2";
800 bind = "False";
801 };
802 };
803
Mario Six004e67c2018-07-31 14:24:14 +0200804 misc-test {
805 compatible = "sandbox,misc_sandbox";
806 };
807
Simon Glasse48eeb92017-04-23 20:02:07 -0600808 mmc2 {
809 compatible = "sandbox,mmc";
810 };
811
812 mmc1 {
813 compatible = "sandbox,mmc";
814 };
815
816 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600817 compatible = "sandbox,mmc";
818 };
819
Simon Glassb45c8332019-02-16 20:24:50 -0700820 pch {
821 compatible = "sandbox,pch";
822 };
823
Tom Rini42c64d12020-02-11 12:41:23 -0500824 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700825 compatible = "sandbox,pci";
826 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500827 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700828 #address-cells = <3>;
829 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600830 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700831 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700832 pci@0,0 {
833 compatible = "pci-generic";
834 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600835 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700836 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300837 pci@1,0 {
838 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600839 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
840 reg = <0x02000814 0 0 0 0
841 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600842 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300843 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700844 p2sb-pci@2,0 {
845 compatible = "sandbox,p2sb";
846 reg = <0x02001010 0 0 0 0>;
847 sandbox,emul = <&p2sb_emul>;
848
849 adder {
850 intel,p2sb-port-id = <3>;
851 compatible = "sandbox,adder";
852 };
853 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700854 pci@1e,0 {
855 compatible = "sandbox,pmc";
856 reg = <0xf000 0 0 0 0>;
857 sandbox,emul = <&pmc_emul1e>;
858 acpi-base = <0x400>;
859 gpe0-dwx-mask = <0xf>;
860 gpe0-dwx-shift-base = <4>;
861 gpe0-dw = <6 7 9>;
862 gpe0-sts = <0x20>;
863 gpe0-en = <0x30>;
864 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700865 pci@1f,0 {
866 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600867 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
868 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600869 sandbox,emul = <&swap_case_emul0_1f>;
870 };
871 };
872
873 pci-emul0 {
874 compatible = "sandbox,pci-emul-parent";
875 swap_case_emul0_0: emul0@0,0 {
876 compatible = "sandbox,swap-case";
877 };
878 swap_case_emul0_1: emul0@1,0 {
879 compatible = "sandbox,swap-case";
880 use-ea;
881 };
882 swap_case_emul0_1f: emul0@1f,0 {
883 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700884 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700885 p2sb_emul: emul@2,0 {
886 compatible = "sandbox,p2sb-emul";
887 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700888 pmc_emul1e: emul@1e,0 {
889 compatible = "sandbox,pmc-emul";
890 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700891 };
892
Tom Rini42c64d12020-02-11 12:41:23 -0500893 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700894 compatible = "sandbox,pci";
895 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500896 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700897 #address-cells = <3>;
898 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700899 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
900 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
901 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700902 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200903 0x0c 0x00 0x1234 0x5678
904 0x10 0x00 0x1234 0x5678>;
905 pci@10,0 {
906 reg = <0x8000 0 0 0 0>;
907 };
Bin Mengdee4d752018-08-03 01:14:41 -0700908 };
909
Tom Rini42c64d12020-02-11 12:41:23 -0500910 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700911 compatible = "sandbox,pci";
912 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500913 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700914 #address-cells = <3>;
915 #size-cells = <2>;
916 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
917 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
918 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
919 pci@1f,0 {
920 compatible = "pci-generic";
921 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600922 sandbox,emul = <&swap_case_emul2_1f>;
923 };
924 };
925
926 pci-emul2 {
927 compatible = "sandbox,pci-emul-parent";
928 swap_case_emul2_1f: emul2@1f,0 {
929 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -0700930 };
931 };
932
Ramon Friedbb413332019-04-27 11:15:23 +0300933 pci_ep: pci_ep {
934 compatible = "sandbox,pci_ep";
935 };
936
Simon Glass98561572017-04-23 20:10:44 -0600937 probing {
938 compatible = "simple-bus";
939 test1 {
940 compatible = "denx,u-boot-probe-test";
941 };
942
943 test2 {
944 compatible = "denx,u-boot-probe-test";
945 };
946
947 test3 {
948 compatible = "denx,u-boot-probe-test";
949 };
950
951 test4 {
952 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +0100953 first-syscon = <&syscon0>;
954 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +0100955 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -0600956 };
957 };
958
Stephen Warren61f5ddc2016-07-13 13:45:31 -0600959 pwrdom: power-domain {
960 compatible = "sandbox,power-domain";
961 #power-domain-cells = <1>;
962 };
963
964 power-domain-test {
965 compatible = "sandbox,power-domain-test";
966 power-domains = <&pwrdom 2>;
967 };
968
Simon Glass5d9a88f2018-10-01 12:22:40 -0600969 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -0600970 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600971 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +0200972 pinctrl-names = "default";
973 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -0600974 };
975
976 pwm2 {
977 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -0600978 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -0600979 };
980
Simon Glass64ce0ca2015-07-06 12:54:31 -0600981 ram {
982 compatible = "sandbox,ram";
983 };
984
Simon Glass5010d982015-07-06 12:54:29 -0600985 reset@0 {
986 compatible = "sandbox,warm-reset";
987 };
988
989 reset@1 {
990 compatible = "sandbox,reset";
991 };
992
Stephen Warren4581b712016-06-17 09:43:59 -0600993 resetc: reset-ctl {
994 compatible = "sandbox,reset-ctl";
995 #reset-cells = <1>;
996 };
997
998 reset-ctl-test {
999 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001000 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1001 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001002 };
1003
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301004 rng {
1005 compatible = "sandbox,sandbox-rng";
1006 };
1007
Nishanth Menon52159402015-09-17 15:42:41 -05001008 rproc_1: rproc@1 {
1009 compatible = "sandbox,test-processor";
1010 remoteproc-name = "remoteproc-test-dev1";
1011 };
1012
1013 rproc_2: rproc@2 {
1014 compatible = "sandbox,test-processor";
1015 internal-memory-mapped;
1016 remoteproc-name = "remoteproc-test-dev2";
1017 };
1018
Simon Glass5d9a88f2018-10-01 12:22:40 -06001019 panel {
1020 compatible = "simple-panel";
1021 backlight = <&backlight 0 100>;
1022 };
1023
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001024 smem@0 {
1025 compatible = "sandbox,smem";
1026 };
1027
Simon Glassd4901892018-12-10 10:37:36 -07001028 sound {
1029 compatible = "sandbox,sound";
1030 cpu {
1031 sound-dai = <&i2s 0>;
1032 };
1033
1034 codec {
1035 sound-dai = <&audio 0>;
1036 };
1037 };
1038
Simon Glass0ae0cb72014-10-13 23:42:11 -06001039 spi@0 {
1040 #address-cells = <1>;
1041 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001042 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001043 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001044 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001045 pinctrl-names = "default";
1046 pinctrl-0 = <&pinmux_spi0_pins>;
1047
Simon Glass0ae0cb72014-10-13 23:42:11 -06001048 spi.bin@0 {
1049 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001050 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001051 spi-max-frequency = <40000000>;
1052 sandbox,filename = "spi.bin";
1053 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001054 spi.bin@1 {
1055 reg = <1>;
1056 compatible = "spansion,m25p16", "jedec,spi-nor";
1057 spi-max-frequency = <50000000>;
1058 sandbox,filename = "spi.bin";
1059 spi-cpol;
1060 spi-cpha;
1061 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001062 };
1063
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001064 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001065 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001066 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001067 };
1068
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001069 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001070 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001071 reg = <0x20 5
1072 0x28 6
1073 0x30 7
1074 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001075 };
1076
Patrick Delaunaya442e612019-03-07 09:57:13 +01001077 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001078 compatible = "simple-mfd", "syscon";
1079 reg = <0x40 5
1080 0x48 6
1081 0x50 7
1082 0x58 8>;
1083 };
1084
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301085 syscon3: syscon@3 {
1086 compatible = "simple-mfd", "syscon";
1087 reg = <0x000100 0x10>;
1088
1089 muxcontroller0: a-mux-controller {
1090 compatible = "mmio-mux";
1091 #mux-control-cells = <1>;
1092
1093 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1094 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1095 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1096 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1097 u-boot,mux-autoprobe;
1098 };
1099 };
1100
1101 muxcontroller1: emul-mux-controller {
1102 compatible = "mux-emul";
1103 #mux-control-cells = <0>;
1104 u-boot,mux-autoprobe;
1105 idle-state = <0xabcd>;
1106 };
1107
Simon Glass93f44e82020-12-16 21:20:27 -07001108 testfdtm0 {
1109 compatible = "denx,u-boot-fdtm-test";
1110 };
1111
1112 testfdtm1: testfdtm1 {
1113 compatible = "denx,u-boot-fdtm-test";
1114 };
1115
1116 testfdtm2 {
1117 compatible = "denx,u-boot-fdtm-test";
1118 };
1119
Sean Anderson7616e362020-09-28 10:52:23 -04001120 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001121 compatible = "sandbox,timer";
1122 clock-frequency = <1000000>;
1123 };
1124
Sean Anderson7616e362020-09-28 10:52:23 -04001125 timer@1 {
1126 compatible = "sandbox,timer";
1127 sandbox,timebase-frequency-fallback;
1128 };
1129
Miquel Raynalb91ad162018-05-15 11:57:27 +02001130 tpm2 {
1131 compatible = "sandbox,tpm2";
1132 };
1133
Simon Glass171e9912015-05-22 15:42:15 -06001134 uart0: serial {
1135 compatible = "sandbox,serial";
1136 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001137 pinctrl-names = "default";
1138 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001139 };
1140
Simon Glasse00cb222015-03-25 12:23:05 -06001141 usb_0: usb@0 {
1142 compatible = "sandbox,usb";
1143 status = "disabled";
1144 hub {
1145 compatible = "sandbox,usb-hub";
1146 #address-cells = <1>;
1147 #size-cells = <0>;
1148 flash-stick {
1149 reg = <0>;
1150 compatible = "sandbox,usb-flash";
1151 };
1152 };
1153 };
1154
1155 usb_1: usb@1 {
1156 compatible = "sandbox,usb";
1157 hub {
1158 compatible = "usb-hub";
1159 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001160 #address-cells = <1>;
1161 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001162 hub-emul {
1163 compatible = "sandbox,usb-hub";
1164 #address-cells = <1>;
1165 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001166 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001167 reg = <0>;
1168 compatible = "sandbox,usb-flash";
1169 sandbox,filepath = "testflash.bin";
1170 };
1171
Simon Glass431cbd62015-11-08 23:48:01 -07001172 flash-stick@1 {
1173 reg = <1>;
1174 compatible = "sandbox,usb-flash";
1175 sandbox,filepath = "testflash1.bin";
1176 };
1177
1178 flash-stick@2 {
1179 reg = <2>;
1180 compatible = "sandbox,usb-flash";
1181 sandbox,filepath = "testflash2.bin";
1182 };
1183
Simon Glassbff1a712015-11-08 23:48:08 -07001184 keyb@3 {
1185 reg = <3>;
1186 compatible = "sandbox,usb-keyb";
1187 };
1188
Simon Glasse00cb222015-03-25 12:23:05 -06001189 };
Michael Wallec03b7612020-06-02 01:47:07 +02001190
1191 usbstor@1 {
1192 reg = <1>;
1193 };
1194 usbstor@3 {
1195 reg = <3>;
1196 };
Simon Glasse00cb222015-03-25 12:23:05 -06001197 };
1198 };
1199
1200 usb_2: usb@2 {
1201 compatible = "sandbox,usb";
1202 status = "disabled";
1203 };
1204
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001205 spmi: spmi@0 {
1206 compatible = "sandbox,spmi";
1207 #address-cells = <0x1>;
1208 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001209 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001210 pm8916@0 {
1211 compatible = "qcom,spmi-pmic";
1212 reg = <0x0 0x1>;
1213 #address-cells = <0x1>;
1214 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001215 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001216
1217 spmi_gpios: gpios@c000 {
1218 compatible = "qcom,pm8916-gpio";
1219 reg = <0xc000 0x400>;
1220 gpio-controller;
1221 gpio-count = <4>;
1222 #gpio-cells = <2>;
1223 gpio-bank-name="spmi";
1224 };
1225 };
1226 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001227
1228 wdt0: wdt@0 {
1229 compatible = "sandbox,wdt";
1230 };
Rob Clarkf2006802018-01-10 11:33:30 +01001231
Mario Six957983e2018-08-09 14:51:19 +02001232 axi: axi@0 {
1233 compatible = "sandbox,axi";
1234 #address-cells = <0x1>;
1235 #size-cells = <0x1>;
1236 store@0 {
1237 compatible = "sandbox,sandbox_store";
1238 reg = <0x0 0x400>;
1239 };
1240 };
1241
Rob Clarkf2006802018-01-10 11:33:30 +01001242 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001243 #address-cells = <1>;
1244 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001245 setting = "sunrise ohoka";
1246 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001247 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001248 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001249 chosen-test {
1250 compatible = "denx,u-boot-fdt-test";
1251 reg = <9 1>;
1252 };
1253 };
Mario Sixe8d52912018-03-12 14:53:33 +01001254
1255 translation-test@8000 {
1256 compatible = "simple-bus";
1257 reg = <0x8000 0x4000>;
1258
1259 #address-cells = <0x2>;
1260 #size-cells = <0x1>;
1261
1262 ranges = <0 0x0 0x8000 0x1000
1263 1 0x100 0x9000 0x1000
1264 2 0x200 0xA000 0x1000
1265 3 0x300 0xB000 0x1000
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001266 4 0x400 0xC000 0x1000
Mario Sixe8d52912018-03-12 14:53:33 +01001267 >;
1268
Fabien Dessenne641067f2019-05-31 15:11:30 +02001269 dma-ranges = <0 0x000 0x10000000 0x1000
1270 1 0x100 0x20000000 0x1000
1271 >;
1272
Mario Sixe8d52912018-03-12 14:53:33 +01001273 dev@0,0 {
1274 compatible = "denx,u-boot-fdt-dummy";
1275 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001276 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001277 };
1278
1279 dev@1,100 {
1280 compatible = "denx,u-boot-fdt-dummy";
1281 reg = <1 0x100 0x1000>;
1282
1283 };
1284
1285 dev@2,200 {
1286 compatible = "denx,u-boot-fdt-dummy";
1287 reg = <2 0x200 0x1000>;
1288 };
1289
1290
1291 noxlatebus@3,300 {
1292 compatible = "simple-bus";
1293 reg = <3 0x300 0x1000>;
1294
1295 #address-cells = <0x1>;
1296 #size-cells = <0x0>;
1297
1298 dev@42 {
1299 compatible = "denx,u-boot-fdt-dummy";
1300 reg = <0x42>;
1301 };
1302 };
Dario Binacchid64b9cd2020-12-30 00:16:21 +01001303
1304 xlatebus@4,400 {
1305 compatible = "sandbox,zero-size-cells-bus";
1306 reg = <4 0x400 0x1000>;
1307 #address-cells = <1>;
1308 #size-cells = <1>;
1309 ranges = <0 4 0x400 0x1000>;
1310
1311 devs {
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314
1315 dev@19 {
1316 compatible = "denx,u-boot-fdt-dummy";
1317 reg = <0x19>;
1318 };
1319 };
1320 };
1321
Mario Sixe8d52912018-03-12 14:53:33 +01001322 };
Mario Six4eea5312018-09-27 09:19:31 +02001323
1324 osd {
1325 compatible = "sandbox,sandbox_osd";
1326 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001327
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001328 sandbox_tee {
1329 compatible = "sandbox,tee";
1330 };
Bin Meng4f89d492018-10-15 02:21:26 -07001331
1332 sandbox_virtio1 {
1333 compatible = "sandbox,virtio1";
1334 };
1335
1336 sandbox_virtio2 {
1337 compatible = "sandbox,virtio2";
1338 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001339
Etienne Carriere87d4f272020-09-09 18:44:05 +02001340 sandbox_scmi {
1341 compatible = "sandbox,scmi-devices";
1342 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001343 resets = <&reset_scmi0 3>;
Etienne Carriere01242182021-03-08 22:38:07 +01001344 regul0-supply = <&regul0_scmi0>;
1345 regul1-supply = <&regul1_scmi0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001346 };
1347
Patrice Chotardf41a8242018-10-24 14:10:23 +02001348 pinctrl {
1349 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001350
Sean Anderson7f0f1802020-09-14 11:01:57 -04001351 pinctrl-names = "default", "alternate";
1352 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1353 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001354
Sean Anderson7f0f1802020-09-14 11:01:57 -04001355 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001356 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001357 pins = "P5";
1358 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001359 bias-pull-up;
1360 input-disable;
1361 };
1362 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001363 pins = "P6";
1364 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001365 output-high;
1366 drive-open-drain;
1367 };
1368 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001369 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001370 bias-pull-down;
1371 input-enable;
1372 };
1373 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001374 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001375 bias-disable;
1376 };
1377 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001378
1379 pinctrl_i2c: i2c {
1380 groups {
1381 groups = "I2C_UART";
1382 function = "I2C";
1383 };
1384
1385 pins {
1386 pins = "P0", "P1";
1387 drive-open-drain;
1388 };
1389 };
1390
1391 pinctrl_i2s: i2s {
1392 groups = "SPI_I2S";
1393 function = "I2S";
1394 };
1395
1396 pinctrl_spi: spi {
1397 groups = "SPI_I2S";
1398 function = "SPI";
1399
1400 cs {
1401 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1402 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1403 };
1404 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001405 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001406
Dario Binacchi55322622021-04-11 09:39:50 +02001407 pinctrl-single-no-width {
1408 compatible = "pinctrl-single";
1409 reg = <0x0000 0x238>;
1410 #pinctrl-cells = <1>;
1411 pinctrl-single,function-mask = <0x7f>;
1412 };
1413
1414 pinctrl-single-pins {
1415 compatible = "pinctrl-single";
1416 reg = <0x0000 0x238>;
1417 #pinctrl-cells = <1>;
1418 pinctrl-single,register-width = <32>;
1419 pinctrl-single,function-mask = <0x7f>;
1420
1421 pinmux_pwm_pins: pinmux_pwm_pins {
1422 pinctrl-single,pins = < 0x48 0x06 >;
1423 };
1424
1425 pinmux_spi0_pins: pinmux_spi0_pins {
1426 pinctrl-single,pins = <
1427 0x190 0x0c
1428 0x194 0x0c
1429 0x198 0x23
1430 0x19c 0x0c
1431 >;
1432 };
1433
1434 pinmux_uart0_pins: pinmux_uart0_pins {
1435 pinctrl-single,pins = <
1436 0x70 0x30
1437 0x74 0x00
1438 >;
1439 };
1440 };
1441
1442 pinctrl-single-bits {
1443 compatible = "pinctrl-single";
1444 reg = <0x0000 0x50>;
1445 #pinctrl-cells = <2>;
1446 pinctrl-single,bit-per-mux;
1447 pinctrl-single,register-width = <32>;
1448 pinctrl-single,function-mask = <0xf>;
1449
1450 pinmux_i2c0_pins: pinmux_i2c0_pins {
1451 pinctrl-single,bits = <
1452 0x10 0x00002200 0x0000ff00
1453 >;
1454 };
1455
1456 pinmux_lcd_pins: pinmux_lcd_pins {
1457 pinctrl-single,bits = <
1458 0x40 0x22222200 0xffffff00
1459 0x44 0x22222222 0xffffffff
1460 0x48 0x00000022 0x000000ff
1461 0x48 0x02000000 0x0f000000
1462 0x4c 0x02000022 0x0f0000ff
1463 >;
1464 };
1465 };
1466
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001467 hwspinlock@0 {
1468 compatible = "sandbox,hwspinlock";
1469 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001470
1471 dma: dma {
1472 compatible = "sandbox,dma";
1473 #dma-cells = <1>;
1474
1475 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1476 dma-names = "m2m", "tx0", "rx0";
1477 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001478
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001479 /*
1480 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1481 * end of the test. If parent mdio is removed first, clean-up of the
1482 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1483 * active at the end of the test. That it turn doesn't allow the mdio
1484 * class to be destroyed, triggering an error.
1485 */
1486 mdio-mux-test {
1487 compatible = "sandbox,mdio-mux";
1488 #address-cells = <1>;
1489 #size-cells = <0>;
1490 mdio-parent-bus = <&mdio>;
1491
1492 mdio-ch-test@0 {
1493 reg = <0>;
1494 };
1495 mdio-ch-test@1 {
1496 reg = <1>;
1497 };
1498 };
1499
1500 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001501 compatible = "sandbox,mdio";
1502 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001503
1504 pm-bus-test {
1505 compatible = "simple-pm-bus";
1506 clocks = <&clk_sandbox 4>;
1507 power-domains = <&pwrdom 1>;
1508 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001509
1510 resetc2: syscon-reset {
1511 compatible = "syscon-reset";
1512 #reset-cells = <1>;
1513 regmap = <&syscon0>;
1514 offset = <1>;
1515 mask = <0x27FFFFFF>;
1516 assert-high = <0>;
1517 };
1518
1519 syscon-reset-test {
1520 compatible = "sandbox,misc_sandbox";
1521 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1522 reset-names = "valid", "no_mask", "out_of_range";
1523 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301524
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001525 sysinfo {
1526 compatible = "sandbox,sysinfo-sandbox";
1527 };
1528
Sean Anderson1cbfed82021-04-20 10:50:58 -04001529 sysinfo-gpio {
1530 compatible = "gpio-sysinfo";
1531 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1532 revisions = <19>, <5>;
1533 names = "rev_a", "foo";
1534 };
1535
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301536 some_regmapped-bus {
1537 #address-cells = <0x1>;
1538 #size-cells = <0x1>;
1539
1540 ranges = <0x0 0x0 0x10>;
1541 compatible = "simple-bus";
1542
1543 regmap-test_0 {
1544 reg = <0 0x10>;
1545 compatible = "sandbox,regmap_test";
1546 };
1547 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001548};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001549
1550#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001551#include "cros-ec-keyboard.dtsi"