blob: 8e7aa8437dcf4d5b2f1660964767b0e2642cad4f [file] [log] [blame]
Ian Campbell2c7e3b92014-10-24 21:20:44 +01001if ARCH_SUNXI
2
Philipp Tomsichb5299932017-08-03 23:23:55 +02003config SPL_LDSCRIPT
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
5
Siva Durga Prasad Paladugua4d88922016-07-29 15:31:47 +05306config IDENT_STRING
7 default " Allwinner Technology"
8
Jagan Tekidd928bf2018-01-10 16:03:34 +05309config DRAM_SUN4I
10 bool
11 help
12 Select this dram controller driver for Sun4/5/7i platforms,
13 like A10/A13/A20.
14
Jagan Tekifdfa9342018-03-17 00:16:36 +053015config DRAM_SUN6I
16 bool
17 help
18 Select this dram controller driver for Sun6i platforms,
19 like A31/A31s.
20
Jagan Tekiaf303932018-01-10 16:15:14 +053021config DRAM_SUN8I_A23
22 bool
23 help
24 Select this dram controller driver for Sun8i platforms,
25 for A23 SOC.
26
Jagan Tekic335e992018-01-10 16:17:39 +053027config DRAM_SUN8I_A33
28 bool
29 help
30 Select this dram controller driver for Sun8i platforms,
31 for A33 SOC.
32
Jagan Teki0354f4b2018-01-10 16:20:26 +053033config DRAM_SUN8I_A83T
34 bool
35 help
36 Select this dram controller driver for Sun8i platforms,
37 for A83T SOC.
38
Jagan Teki7d0b1652018-03-17 00:18:01 +053039config DRAM_SUN9I
40 bool
41 help
42 Select this dram controller driver for Sun9i platforms,
43 like A80.
44
Icenowy Zhengda261652018-07-23 06:13:34 +080045config DRAM_SUN50I_H6
46 bool
47 help
48 Select this dram controller driver for some sun50i platforms,
49 like H6.
50
Jernej Skrabecf4317db2021-01-11 21:11:43 +010051config DRAM_SUN50I_H616
52 bool
53 help
54 Select this dram controller driver for some sun50i platforms,
55 like H616.
56
57if DRAM_SUN50I_H616
58config DRAM_SUN50I_H616_WRITE_LEVELING
59 bool "H616 DRAM write leveling"
60 ---help---
61 Select this when DRAM on your H616 board needs write leveling.
62
63config DRAM_SUN50I_H616_READ_CALIBRATION
64 bool "H616 DRAM read calibration"
65 ---help---
66 Select this when DRAM on your H616 board needs read calibration.
67
68config DRAM_SUN50I_H616_READ_TRAINING
69 bool "H616 DRAM read training"
70 ---help---
71 Select this when DRAM on your H616 board needs read training.
72
73config DRAM_SUN50I_H616_WRITE_TRAINING
74 bool "H616 DRAM write training"
75 ---help---
76 Select this when DRAM on your H616 board needs write training.
77
78config DRAM_SUN50I_H616_BIT_DELAY_COMPENSATION
79 bool "H616 DRAM bit delay compensation"
80 ---help---
81 Select this when DRAM on your H616 board needs bit delay
82 compensation.
83
84config DRAM_SUN50I_H616_UNKNOWN_FEATURE
85 bool "H616 DRAM unknown feature"
86 ---help---
87 Select this when DRAM on your H616 board needs this unknown
88 feature.
89endif
90
Jagan Teki71d9edf2018-01-11 13:21:58 +053091config SUN6I_P2WI
92 bool "Allwinner sun6i internal P2WI controller"
93 help
94 If you say yes to this option, support will be included for the
95 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
96 SOCs.
97 The P2WI looks like an SMBus controller (which supports only byte
98 accesses), except that it only supports one slave device.
99 This interface is used to connect to specific PMIC devices (like the
100 AXP221).
101
Jagan Teki2aa697a2018-01-11 13:21:15 +0530102config SUN6I_PRCM
103 bool
104 help
105 Support for the PRCM (Power/Reset/Clock Management) unit available
106 in A31 SoC.
107
Jagan Teki735fb252018-02-14 22:28:30 +0530108config AXP_PMIC_BUS
109 bool "Sunxi AXP PMIC bus access helpers"
110 help
111 Select this PMIC bus access helpers for Sunxi platform PRCM or other
112 AXP family PMIC devices.
113
Jagan Teki6f6f8832018-01-11 13:23:52 +0530114config SUN8I_RSB
115 bool "Allwinner sunXi Reduced Serial Bus Driver"
116 help
117 Say y here to enable support for Allwinner's Reduced Serial Bus
118 (RSB) support. This controller is responsible for communicating
119 with various RSB based devices, such as AXP223, AXP8XX PMICs,
120 and AC100/AC200 ICs.
121
Icenowy Zhengcadc7c22018-07-21 16:20:20 +0800122config SUNXI_SRAM_ADDRESS
123 hex
124 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
Jernej Skrabec44726092021-01-11 21:11:34 +0100125 default 0x20000 if SUN50I_GEN_H6
Icenowy Zhengcadc7c22018-07-21 16:20:20 +0800126 default 0x0
Andre Przywarabc613d82017-02-16 01:20:23 +0000127 ---help---
128 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
129 with the first SRAM region being located at address 0.
130 Some newer SoCs map the boot ROM at address 0 instead and move the
Icenowy Zhengcadc7c22018-07-21 16:20:20 +0800131 SRAM to a different address.
Andre Przywarabc613d82017-02-16 01:20:23 +0000132
Andre Przywarabe0d2172018-06-27 01:42:53 +0100133config SUNXI_A64_TIMER_ERRATUM
134 bool
135
Hans de Goede44d8ae52015-04-06 20:33:34 +0200136# Note only one of these may be selected at a time! But hidden choices are
137# not supported by Kconfig
138config SUNXI_GEN_SUN4I
139 bool
140 ---help---
141 Select this for sunxi SoCs which have resets and clocks set up
142 as the original A10 (mach-sun4i).
143
144config SUNXI_GEN_SUN6I
145 bool
146 ---help---
147 Select this for sunxi SoCs which have sun6i like periphery, like
148 separate ahb reset control registers, custom pmic bus, new style
149 watchdog, etc.
150
Jernej Skrabec44726092021-01-11 21:11:34 +0100151config SUN50I_GEN_H6
152 bool
153 select FIT
154 select SPL_LOAD_FIT
155 select SUPPORT_SPL
156 ---help---
157 Select this for sunxi SoCs which have H6 like peripherals, clocks
158 and memory map.
159
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800160config SUNXI_DRAM_DW
161 bool
162 ---help---
163 Select this for sunxi SoCs which uses a DRAM controller like the
164 DesignWare controller used in H3, mainly SoCs after H3, which do
165 not have official open-source DRAM initialization code, but can
166 use modified H3 DRAM initialization code.
Hans de Goede44d8ae52015-04-06 20:33:34 +0200167
Icenowy Zheng87098d72017-06-03 17:10:16 +0800168if SUNXI_DRAM_DW
169config SUNXI_DRAM_DW_16BIT
170 bool
171 ---help---
172 Select this for sunxi SoCs with DesignWare DRAM controller and
173 have only 16-bit memory buswidth.
174
175config SUNXI_DRAM_DW_32BIT
176 bool
177 ---help---
178 Select this for sunxi SoCs with DesignWare DRAM controller with
179 32-bit memory buswidth.
180endif
181
Andre Przywara7b82a222017-02-16 01:20:27 +0000182config MACH_SUNXI_H3_H5
183 bool
Jernej Skrabeca05a4542017-04-27 00:03:37 +0200184 select DM_I2C
Jagan Tekidd322812018-05-07 13:03:38 +0530185 select PHY_SUN4I_USB
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200186 select SUNXI_DE2
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800187 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800188 select SUNXI_DRAM_DW_32BIT
Andre Przywara7b82a222017-02-16 01:20:27 +0000189 select SUNXI_GEN_SUN6I
190 select SUPPORT_SPL
191
Icenowy Zhengf8aa3f82018-10-25 17:23:06 +0800192# TODO: try out A80's 8GiB DRAM space
193config SUNXI_DRAM_MAX_SIZE
194 hex
Andre Przywarab8747852021-04-28 21:29:55 +0100195 default 0x100000000 if MACH_SUN50I_H616
196 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
Icenowy Zhengf8aa3f82018-10-25 17:23:06 +0800197 default 0x80000000
198
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100199choice
200 prompt "Sunxi SoC Variant"
Hans de Goede3da95362016-06-12 11:57:07 +0200201 optional
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100202
Ian Campbellc3be2792014-10-24 21:20:45 +0100203config MACH_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100204 bool "sun4i (Allwinner A10)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530205 select CPU_V7A
Andre Przywara85db5832017-02-16 01:20:21 +0000206 select ARM_CORTEX_CPU_IS_UP
Jagan Tekidd322812018-05-07 13:03:38 +0530207 select PHY_SUN4I_USB
Jagan Tekidd928bf2018-01-10 16:03:34 +0530208 select DRAM_SUN4I
Hans de Goede44d8ae52015-04-06 20:33:34 +0200209 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100210 select SUPPORT_SPL
211
Ian Campbellc3be2792014-10-24 21:20:45 +0100212config MACH_SUN5I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100213 bool "sun5i (Allwinner A13)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530214 select CPU_V7A
Andre Przywara85db5832017-02-16 01:20:21 +0000215 select ARM_CORTEX_CPU_IS_UP
Jagan Tekidd928bf2018-01-10 16:03:34 +0530216 select DRAM_SUN4I
Jagan Tekidd322812018-05-07 13:03:38 +0530217 select PHY_SUN4I_USB
Hans de Goede44d8ae52015-04-06 20:33:34 +0200218 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100219 select SUPPORT_SPL
Tom Rini6f6b7cf2018-03-06 19:02:27 -0500220 imply CONS_INDEX_2 if !DM_SERIAL
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100221
Ian Campbellc3be2792014-10-24 21:20:45 +0100222config MACH_SUN6I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100223 bool "sun6i (Allwinner A31)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530224 select CPU_V7A
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +0800225 select CPU_V7_HAS_NONSEC
226 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900227 select ARCH_SUPPORT_PSCI
Jagan Tekifdfa9342018-03-17 00:16:36 +0530228 select DRAM_SUN6I
Jagan Tekidd322812018-05-07 13:03:38 +0530229 select PHY_SUN4I_USB
Jagan Teki71d9edf2018-01-11 13:21:58 +0530230 select SUN6I_P2WI
Jagan Teki2aa697a2018-01-11 13:21:15 +0530231 select SUN6I_PRCM
Hans de Goede44d8ae52015-04-06 20:33:34 +0200232 select SUNXI_GEN_SUN6I
Hans de Goede8c2c9cf2014-10-25 20:18:10 +0200233 select SUPPORT_SPL
Chen-Yu Tsaicc08ea42015-05-28 21:25:32 +0800234 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100235
Ian Campbellc3be2792014-10-24 21:20:45 +0100236config MACH_SUN7I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100237 bool "sun7i (Allwinner A20)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530238 select CPU_V7A
Hans de Goedeea624e12014-11-14 09:34:30 +0100239 select CPU_V7_HAS_NONSEC
240 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900241 select ARCH_SUPPORT_PSCI
Jagan Tekidd928bf2018-01-10 16:03:34 +0530242 select DRAM_SUN4I
Jagan Tekidd322812018-05-07 13:03:38 +0530243 select PHY_SUN4I_USB
Hans de Goede44d8ae52015-04-06 20:33:34 +0200244 select SUNXI_GEN_SUN4I
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100245 select SUPPORT_SPL
Hans de Goedeb366fb92014-10-24 20:12:04 +0200246 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100247
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200248config MACH_SUN8I_A23
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100249 bool "sun8i (Allwinner A23)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530250 select CPU_V7A
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800251 select CPU_V7_HAS_NONSEC
252 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900253 select ARCH_SUPPORT_PSCI
Jagan Tekiaf303932018-01-10 16:15:14 +0530254 select DRAM_SUN8I_A23
Jagan Tekidd322812018-05-07 13:03:38 +0530255 select PHY_SUN4I_USB
Hans de Goede44d8ae52015-04-06 20:33:34 +0200256 select SUNXI_GEN_SUN6I
Hans de Goede08fd1472014-12-07 14:34:27 +0100257 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800258 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Tom Rini6f6b7cf2018-03-06 19:02:27 -0500259 imply CONS_INDEX_5 if !DM_SERIAL
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100260
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530261config MACH_SUN8I_A33
262 bool "sun8i (Allwinner A33)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530263 select CPU_V7A
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800264 select CPU_V7_HAS_NONSEC
265 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900266 select ARCH_SUPPORT_PSCI
Jagan Tekic335e992018-01-10 16:17:39 +0530267 select DRAM_SUN8I_A33
Jagan Tekidd322812018-05-07 13:03:38 +0530268 select PHY_SUN4I_USB
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530269 select SUNXI_GEN_SUN6I
270 select SUPPORT_SPL
Chen-Yu Tsai014414f2015-05-28 21:25:34 +0800271 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Tom Rini6f6b7cf2018-03-06 19:02:27 -0500272 imply CONS_INDEX_5 if !DM_SERIAL
Vishnu Patekar8c3dacf2015-03-01 23:47:48 +0530273
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800274config MACH_SUN8I_A83T
275 bool "sun8i (Allwinner A83T)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530276 select CPU_V7A
Jagan Teki0354f4b2018-01-10 16:20:26 +0530277 select DRAM_SUN8I_A83T
Jagan Tekidd322812018-05-07 13:03:38 +0530278 select PHY_SUN4I_USB
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800279 select SUNXI_GEN_SUN6I
Maxime Ripard343ff162017-08-23 12:03:42 +0200280 select MMC_SUNXI_HAS_NEW_MODE
Vasily Khoruzhick2a8882e2018-11-09 20:41:44 -0800281 select MMC_SUNXI_HAS_MODE_SWITCH
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800282 select SUPPORT_SPL
283
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100284config MACH_SUN8I_H3
285 bool "sun8i (Allwinner H3)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530286 select CPU_V7A
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800287 select CPU_V7_HAS_NONSEC
288 select CPU_V7_HAS_VIRT
Masahiro Yamada217f92b2016-08-30 16:22:22 +0900289 select ARCH_SUPPORT_PSCI
Andre Przywara7b82a222017-02-16 01:20:27 +0000290 select MACH_SUNXI_H3_H5
Chen-Yu Tsai853f6d12016-01-06 15:13:09 +0800291 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
Jens Kuske1c27b7d2015-11-17 15:12:58 +0100292
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800293config MACH_SUN8I_R40
294 bool "sun8i (Allwinner R40)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530295 select CPU_V7A
Chen-Yu Tsai09186482017-03-01 11:03:15 +0800296 select CPU_V7_HAS_NONSEC
297 select CPU_V7_HAS_VIRT
298 select ARCH_SUPPORT_PSCI
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800299 select SUNXI_GEN_SUN6I
Chen-Yu Tsai50ae7ae2016-12-02 16:09:49 +0800300 select SUPPORT_SPL
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800301 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800302 select SUNXI_DRAM_DW_32BIT
Andre Przywaraa2f729f2020-01-01 23:44:48 +0000303 select PHY_SUN4I_USB
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800304
Icenowy Zhengc1994892017-04-08 15:30:12 +0800305config MACH_SUN8I_V3S
Icenowy Zhengef9025b2020-10-26 22:15:59 +0800306 bool "sun8i (Allwinner V3/V3s/S3/S3L)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530307 select CPU_V7A
Icenowy Zhengc1994892017-04-08 15:30:12 +0800308 select CPU_V7_HAS_NONSEC
309 select CPU_V7_HAS_VIRT
310 select ARCH_SUPPORT_PSCI
311 select SUNXI_GEN_SUN6I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800312 select SUNXI_DRAM_DW
313 select SUNXI_DRAM_DW_16BIT
314 select SUPPORT_SPL
Icenowy Zhengc1994892017-04-08 15:30:12 +0800315 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
316
Hans de Goede1871a8c2015-01-13 19:25:06 +0100317config MACH_SUN9I
318 bool "sun9i (Allwinner A80)"
Lokesh Vutlaacf15002018-04-26 18:21:26 +0530319 select CPU_V7A
Jagan Teki7d0b1652018-03-17 00:18:01 +0530320 select DRAM_SUN9I
Jagan Teki63928fa2018-01-11 13:23:02 +0530321 select SUN6I_PRCM
Hans de Goede1871a8c2015-01-13 19:25:06 +0100322 select SUNXI_GEN_SUN6I
Jagan Teki6f6f8832018-01-11 13:23:52 +0530323 select SUN8I_RSB
Philipp Tomsicha98c2962016-10-28 18:21:32 +0800324 select SUPPORT_SPL
Hans de Goede1871a8c2015-01-13 19:25:06 +0100325
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800326config MACH_SUN50I
327 bool "sun50i (Allwinner A64)"
328 select ARM64
Jagan Teki7945caf2019-10-16 18:08:26 +0530329 select SPI
Jernej Skrabeca05a4542017-04-27 00:03:37 +0200330 select DM_I2C
Jagan Teki7945caf2019-10-16 18:08:26 +0530331 select DM_SPI if SPI
332 select DM_SPI_FLASH
Jagan Tekidd322812018-05-07 13:03:38 +0530333 select PHY_SUN4I_USB
Vasily Khoruzhick31a4ac42018-11-05 20:24:30 -0800334 select SUN6I_PRCM
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200335 select SUNXI_DE2
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800336 select SUNXI_GEN_SUN6I
Vasily Khoruzhick0e21a2f2018-11-09 20:41:46 -0800337 select MMC_SUNXI_HAS_NEW_MODE
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000338 select SUPPORT_SPL
Icenowy Zheng9934aba2017-06-03 17:10:14 +0800339 select SUNXI_DRAM_DW
Icenowy Zheng87098d72017-06-03 17:10:16 +0800340 select SUNXI_DRAM_DW_32BIT
Andre Przywarad29adf82017-04-26 01:32:48 +0100341 select FIT
342 select SPL_LOAD_FIT
Andre Przywarabe0d2172018-06-27 01:42:53 +0100343 select SUNXI_A64_TIMER_ERRATUM
Chen-Yu Tsaia81b7992016-05-02 10:28:07 +0800344
Andre Przywara997bde62017-02-16 01:20:28 +0000345config MACH_SUN50I_H5
346 bool "sun50i (Allwinner H5)"
347 select ARM64
348 select MACH_SUNXI_H3_H5
Andre Przywarad29adf82017-04-26 01:32:48 +0100349 select FIT
350 select SPL_LOAD_FIT
Andre Przywara997bde62017-02-16 01:20:28 +0000351
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800352config MACH_SUN50I_H6
353 bool "sun50i (Allwinner H6)"
354 select ARM64
Andre Przywaraf96238e2019-06-23 15:09:50 +0100355 select PHY_SUN4I_USB
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800356 select DRAM_SUN50I_H6
Jernej Skrabec44726092021-01-11 21:11:34 +0100357 select SUN50I_GEN_H6
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800358
Jernej Skrabec8ec293e2021-01-11 21:11:46 +0100359config MACH_SUN50I_H616
360 bool "sun50i (Allwinner H616)"
361 select ARM64
362 select DRAM_SUN50I_H616
363 select SUN50I_GEN_H6
364
Ian Campbell2c7e3b92014-10-24 21:20:44 +0100365endchoice
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800366
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200367# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
368config MACH_SUN8I
369 bool
Jagan Teki6f6f8832018-01-11 13:23:52 +0530370 select SUN8I_RSB
Jagan Teki63928fa2018-01-11 13:23:02 +0530371 select SUN6I_PRCM
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800372 default y if MACH_SUN8I_A23
373 default y if MACH_SUN8I_A33
374 default y if MACH_SUN8I_A83T
375 default y if MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800376 default y if MACH_SUN8I_R40
Icenowy Zhengc1994892017-04-08 15:30:12 +0800377 default y if MACH_SUN8I_V3S
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200378
Andre Przywarab5402d12017-01-02 11:48:35 +0000379config RESERVE_ALLWINNER_BOOT0_HEADER
380 bool "reserve space for Allwinner boot0 header"
381 select ENABLE_ARM_SOC_BOOT0_HOOK
382 ---help---
383 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
384 filled with magic values post build. The Allwinner provided boot0
385 blob relies on this information to load and execute U-Boot.
386 Only needed on 64-bit Allwinner boards so far when using boot0.
387
Andre Przywara83843c92017-01-02 11:48:36 +0000388config ARM_BOOT_HOOK_RMR
389 bool
390 depends on ARM64
391 default y
392 select ENABLE_ARM_SOC_BOOT0_HOOK
393 ---help---
394 Insert some ARM32 code at the very beginning of the U-Boot binary
395 which uses an RMR register write to bring the core into AArch64 mode.
396 The very first instruction acts as a switch, since it's carefully
397 chosen to be a NOP in one mode and a branch in the other, so the
398 code would only be executed if not already in AArch64.
399 This allows both the SPL and the U-Boot proper to be entered in
400 either mode and switch to AArch64 if needed.
401
Andre Przywara770b85a2019-07-15 02:27:06 +0100402if SUNXI_DRAM_DW || DRAM_SUN50I_H6
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800403config SUNXI_DRAM_DDR3
404 bool
405
Icenowy Zheng67337e62017-06-03 17:10:20 +0800406config SUNXI_DRAM_DDR2
407 bool
408
Icenowy Zheng72cc9872017-06-03 17:10:23 +0800409config SUNXI_DRAM_LPDDR3
410 bool
411
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800412choice
413 prompt "DRAM Type and Timing"
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800414 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
415 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800416
417config SUNXI_DRAM_DDR3_1333
418 bool "DDR3 1333"
419 select SUNXI_DRAM_DDR3
420 ---help---
421 This option is the original only supported memory type, which suits
422 many H3/H5/A64 boards available now.
423
Icenowy Zhengec4670a2017-06-03 17:10:24 +0800424config SUNXI_DRAM_LPDDR3_STOCK
425 bool "LPDDR3 with Allwinner stock configuration"
426 select SUNXI_DRAM_LPDDR3
427 ---help---
428 This option is the LPDDR3 timing used by the stock boot0 by
429 Allwinner.
430
Andre Przywara770b85a2019-07-15 02:27:06 +0100431config SUNXI_DRAM_H6_LPDDR3
432 bool "LPDDR3 DRAM chips on the H6 DRAM controller"
433 select SUNXI_DRAM_LPDDR3
434 depends on DRAM_SUN50I_H6
435 ---help---
436 This option is the LPDDR3 timing used by the stock boot0 by
437 Allwinner.
438
Andre Przywara7656d392019-07-15 02:27:08 +0100439config SUNXI_DRAM_H6_DDR3_1333
440 bool "DDR3-1333 boot0 timings on the H6 DRAM controller"
441 select SUNXI_DRAM_DDR3
442 depends on DRAM_SUN50I_H6
443 ---help---
444 This option is the DDR3 timing used by the boot0 on H6 TV boxes
445 which use a DDR3-1333 timing.
446
Icenowy Zheng67337e62017-06-03 17:10:20 +0800447config SUNXI_DRAM_DDR2_V3S
448 bool "DDR2 found in V3s chip"
449 select SUNXI_DRAM_DDR2
Icenowy Zheng3ec06982017-06-03 17:10:21 +0800450 depends on MACH_SUN8I_V3S
Icenowy Zheng67337e62017-06-03 17:10:20 +0800451 ---help---
452 This option is only for the DDR2 memory chip which is co-packaged in
453 Allwinner V3s SoC.
454
Icenowy Zhengf6457ce2017-06-03 17:10:18 +0800455endchoice
456endif
457
Vishnu Patekarf5fd8ca2016-01-12 01:20:58 +0800458config DRAM_TYPE
459 int "sunxi dram type"
460 depends on MACH_SUN8I_A83T
461 default 3
462 ---help---
463 Set the dram type, 3: DDR3, 7: LPDDR3
Hans de Goede5e6bacd2015-04-06 20:55:39 +0200464
Hans de Goede37781a12014-11-15 19:46:39 +0100465config DRAM_CLK
Hans de Goede8ffc4872015-01-17 14:24:55 +0100466 int "sunxi dram clock speed"
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800467 default 792 if MACH_SUN9I
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800468 default 648 if MACH_SUN8I_R40
Hans de Goede8ffc4872015-01-17 14:24:55 +0100469 default 312 if MACH_SUN6I || MACH_SUN8I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800470 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
471 MACH_SUN8I_V3S
Andre Przywara52e31822017-01-02 11:48:37 +0000472 default 672 if MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800473 default 744 if MACH_SUN50I_H6
Jernej Skrabecf4317db2021-01-11 21:11:43 +0100474 default 720 if MACH_SUN50I_H616
Hans de Goede37781a12014-11-15 19:46:39 +0100475 ---help---
Philipp Tomsich297bb9e2016-10-28 18:21:28 +0800476 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
477 must be a multiple of 24. For the sun9i (A80), the tested values
478 (for DDR3-1600) are 312 to 792.
Hans de Goede37781a12014-11-15 19:46:39 +0100479
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200480if MACH_SUN5I || MACH_SUN7I
481config DRAM_MBUS_CLK
482 int "sunxi mbus clock speed"
483 default 300
484 ---help---
485 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
486
487endif
488
Hans de Goede37781a12014-11-15 19:46:39 +0100489config DRAM_ZQ
Hans de Goede8ffc4872015-01-17 14:24:55 +0100490 int "sunxi dram zq value"
Jernej Skrabecf4317db2021-01-11 21:11:43 +0100491 depends on !MACH_SUN50I_H616
Paul Kocialkowski9c2b0dd2019-03-14 11:36:14 +0100492 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || \
Paul Kocialkowski882b71e2019-03-14 11:36:15 +0100493 MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
Hans de Goede8ffc4872015-01-17 14:24:55 +0100494 default 127 if MACH_SUN7I
Icenowy Zheng7d06e592017-06-03 17:10:22 +0800495 default 14779 if MACH_SUN8I_V3S
Paul Kocialkowski882b71e2019-03-14 11:36:15 +0100496 default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
Chen-Yu Tsai58b628e2016-10-28 18:21:36 +0800497 default 4145117 if MACH_SUN9I
Andre Przywara52e31822017-01-02 11:48:37 +0000498 default 3881915 if MACH_SUN50I
Hans de Goede37781a12014-11-15 19:46:39 +0100499 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100500 Set the dram zq value.
Hans de Goede37781a12014-11-15 19:46:39 +0100501
Hans de Goede8975cdf2015-05-13 15:00:46 +0200502config DRAM_ODT_EN
503 bool "sunxi dram odt enable"
Hans de Goede8975cdf2015-05-13 15:00:46 +0200504 default y if MACH_SUN8I_A23
Paul Kocialkowski9d0f9e82019-03-14 11:36:16 +0100505 default y if MACH_SUNXI_H3_H5
Chen-Yu Tsaifab03e32016-11-30 16:58:35 +0800506 default y if MACH_SUN8I_R40
Andre Przywaraeb77f5c2017-01-02 11:48:45 +0000507 default y if MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800508 default y if MACH_SUN50I_H6
Jernej Skrabecf4317db2021-01-11 21:11:43 +0100509 default y if MACH_SUN50I_H616
Hans de Goede8975cdf2015-05-13 15:00:46 +0200510 ---help---
511 Select this to enable dram odt (on die termination).
512
Hans de Goede8ffc4872015-01-17 14:24:55 +0100513if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
514config DRAM_EMR1
515 int "sunxi dram emr1 value"
516 default 0 if MACH_SUN4I
517 default 4 if MACH_SUN5I || MACH_SUN7I
518 ---help---
Hans de Goedee1a08882015-01-25 11:29:27 +0100519 Set the dram controller emr1 value.
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200520
Siarhei Siamashka47e35012015-02-01 00:27:06 +0200521config DRAM_TPR3
522 hex "sunxi dram tpr3 value"
523 default 0
524 ---help---
525 Set the dram controller tpr3 parameter. This parameter configures
526 the delay on the command lane and also phase shifts, which are
527 applied for sampling incoming read data. The default value 0
528 means that no phase/delay adjustments are necessary. Properly
529 configuring this parameter increases reliability at high DRAM
530 clock speeds.
531
532config DRAM_DQS_GATING_DELAY
533 hex "sunxi dram dqs_gating_delay value"
534 default 0
535 ---help---
536 Set the dram controller dqs_gating_delay parmeter. Each byte
537 encodes the DQS gating delay for each byte lane. The delay
538 granularity is 1/4 cycle. For example, the value 0x05060606
539 means that the delay is 5 quarter-cycles for one lane (1.25
540 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
541 The default value 0 means autodetection. The results of hardware
542 autodetection are not very reliable and depend on the chip
543 temperature (sometimes producing different results on cold start
544 and warm reboot). But the accuracy of hardware autodetection
545 is usually good enough, unless running at really high DRAM
546 clocks speeds (up to 600MHz). If unsure, keep as 0.
547
Siarhei Siamashkad1336472015-02-01 00:27:05 +0200548choice
549 prompt "sunxi dram timings"
550 default DRAM_TIMINGS_VENDOR_MAGIC
551 ---help---
552 Select the timings of the DDR3 chips.
553
554config DRAM_TIMINGS_VENDOR_MAGIC
555 bool "Magic vendor timings from Android"
556 ---help---
557 The same DRAM timings as in the Allwinner boot0 bootloader.
558
559config DRAM_TIMINGS_DDR3_1066F_1333H
560 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
561 ---help---
562 Use the timings of the standard JEDEC DDR3-1066F speed bin for
563 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
564 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
565 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
566 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
567 that down binning to DDR3-1066F is supported (because DDR3-1066F
568 uses a bit faster timings than DDR3-1333H).
569
570config DRAM_TIMINGS_DDR3_800E_1066G_1333J
571 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
572 ---help---
573 Use the timings of the slowest possible JEDEC speed bin for the
574 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
575 DDR3-800E, DDR3-1066G or DDR3-1333J.
576
577endchoice
578
Hans de Goede37781a12014-11-15 19:46:39 +0100579endif
580
Hans de Goede8975cdf2015-05-13 15:00:46 +0200581if MACH_SUN8I_A23
582config DRAM_ODT_CORRECTION
583 int "sunxi dram odt correction value"
584 default 0
585 ---help---
586 Set the dram odt correction value (range -255 - 255). In allwinner
587 fex files, this option is found in bits 8-15 of the u32 odt_en variable
588 in the [dram] section. When bit 31 of the odt_en variable is set
589 then the correction is negative. Usually the value for this is 0.
590endif
591
Iain Patone71b4222015-03-28 10:26:38 +0000592config SYS_CLK_FREQ
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800593 default 1008000000 if MACH_SUN4I
594 default 1008000000 if MACH_SUN5I
595 default 1008000000 if MACH_SUN6I
Iain Patone71b4222015-03-28 10:26:38 +0000596 default 912000000 if MACH_SUN7I
Icenowy Zheng3cfecee2017-10-31 07:36:28 +0800597 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800598 default 1008000000 if MACH_SUN8I
599 default 1008000000 if MACH_SUN9I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800600 default 888000000 if MACH_SUN50I_H6
Jernej Skrabec8ec293e2021-01-11 21:11:46 +0100601 default 1008000000 if MACH_SUN50I_H616
Iain Patone71b4222015-03-28 10:26:38 +0000602
Maxime Ripard8a6564d2014-10-03 20:16:29 +0800603config SYS_CONFIG_NAME
Ian Campbellc3be2792014-10-24 21:20:45 +0100604 default "sun4i" if MACH_SUN4I
605 default "sun5i" if MACH_SUN5I
606 default "sun6i" if MACH_SUN6I
607 default "sun7i" if MACH_SUN7I
608 default "sun8i" if MACH_SUN8I
Hans de Goede1871a8c2015-01-13 19:25:06 +0100609 default "sun9i" if MACH_SUN9I
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200610 default "sun50i" if MACH_SUN50I
Icenowy Zheng6f796a92018-07-21 16:20:31 +0800611 default "sun50i" if MACH_SUN50I_H6
Jernej Skrabec8ec293e2021-01-11 21:11:46 +0100612 default "sun50i" if MACH_SUN50I_H616
Hans de Goede6ae66f22014-08-01 09:28:24 +0200613
Masahiro Yamadadd840582014-07-30 14:08:14 +0900614config SYS_BOARD
Masahiro Yamadadd840582014-07-30 14:08:14 +0900615 default "sunxi"
616
617config SYS_SOC
Masahiro Yamadadd840582014-07-30 14:08:14 +0900618 default "sunxi"
619
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200620config UART0_PORT_F
621 bool "UART0 on MicroSD breakout board"
Siarhei Siamashkaf0ce28e2014-12-25 02:34:47 +0200622 default n
623 ---help---
624 Repurpose the SD card slot for getting access to the UART0 serial
625 console. Primarily useful only for low level u-boot debugging on
626 tablets, where normal UART0 is difficult to access and requires
627 device disassembly and/or soldering. As the SD card can't be used
628 at the same time, the system can be only booted in the FEL mode.
629 Only enable this if you really know what you are doing.
630
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200631config OLD_SUNXI_KERNEL_COMPAT
Masahiro Yamadaab650062016-08-12 10:26:50 +0900632 bool "Enable workarounds for booting old kernels"
Hans de Goedeaccc9e42014-10-22 14:56:36 +0200633 default n
634 ---help---
635 Set this to enable various workarounds for old kernels, this results in
636 sub-optimal settings for newer kernels, only enable if needed.
637
Mylène Josserandf5fd7882017-04-02 12:59:10 +0200638config MACPWR
639 string "MAC power pin"
640 default ""
641 help
642 Set the pin used to power the MAC. This takes a string in the format
643 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
644
Hans de Goedecd821132014-10-02 20:29:26 +0200645config MMC0_CD_PIN
646 string "Card detect pin for mmc0"
Andre Przywara7b82a222017-02-16 01:20:27 +0000647 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
Hans de Goedecd821132014-10-02 20:29:26 +0200648 default ""
649 ---help---
650 Set the card detect pin for mmc0, leave empty to not use cd. This
651 takes a string in the format understood by sunxi_name_to_gpio, e.g.
652 PH1 for pin 1 of port H.
653
654config MMC1_CD_PIN
655 string "Card detect pin for mmc1"
656 default ""
657 ---help---
658 See MMC0_CD_PIN help text.
659
660config MMC2_CD_PIN
661 string "Card detect pin for mmc2"
662 default ""
663 ---help---
664 See MMC0_CD_PIN help text.
665
666config MMC3_CD_PIN
667 string "Card detect pin for mmc3"
668 default ""
669 ---help---
670 See MMC0_CD_PIN help text.
671
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100672config MMC1_PINS
673 string "Pins for mmc1"
674 default ""
675 ---help---
676 Set the pins used for mmc1, when applicable. This takes a string in the
677 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
678
679config MMC2_PINS
680 string "Pins for mmc2"
681 default ""
682 ---help---
683 See MMC1_PINS help text.
684
685config MMC3_PINS
686 string "Pins for mmc3"
687 default ""
688 ---help---
689 See MMC1_PINS help text.
690
Hans de Goede2ccfac02014-10-02 20:43:50 +0200691config MMC_SUNXI_SLOT_EXTRA
692 int "mmc extra slot number"
693 default -1
694 ---help---
695 sunxi builds always enable mmc0, some boards also have a second sdcard
696 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
697 support for this.
698
Hans de Goede2c3c3ec2016-04-01 22:39:26 +0200699config INITIAL_USB_SCAN_DELAY
700 int "delay initial usb scan by x ms to allow builtin devices to init"
701 default 0
702 ---help---
703 Some boards have on board usb devices which need longer than the
704 USB spec's 1 second to connect from board powerup. Set this config
705 option to a non 0 value to add an extra delay before the first usb
706 bus scan.
707
Hans de Goede4458b7a2015-01-07 15:26:06 +0100708config USB0_VBUS_PIN
709 string "Vbus enable pin for usb0 (otg)"
710 default ""
711 ---help---
712 Set the Vbus enable pin for usb0 (otg). This takes a string in the
713 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
714
Hans de Goede52defe82015-02-16 22:13:43 +0100715config USB0_VBUS_DET
716 string "Vbus detect pin for usb0 (otg)"
Hans de Goede52defe82015-02-16 22:13:43 +0100717 default ""
718 ---help---
719 Set the Vbus detect pin for usb0 (otg). This takes a string in the
720 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
721
Hans de Goede48c06c92015-06-14 17:29:53 +0200722config USB0_ID_DET
723 string "ID detect pin for usb0 (otg)"
724 default ""
725 ---help---
726 Set the ID detect pin for usb0 (otg). This takes a string in the
727 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
728
Hans de Goede115200c2014-11-07 16:09:00 +0100729config USB1_VBUS_PIN
730 string "Vbus enable pin for usb1 (ehci0)"
731 default "PH6" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100732 default "PH27" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100733 ---help---
734 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
735 a string in the format understood by sunxi_name_to_gpio, e.g.
736 PH1 for pin 1 of port H.
737
738config USB2_VBUS_PIN
739 string "Vbus enable pin for usb2 (ehci1)"
740 default "PH3" if MACH_SUN4I || MACH_SUN7I
Hans de Goede76946df2014-11-07 14:51:12 +0100741 default "PH24" if MACH_SUN6I
Hans de Goede115200c2014-11-07 16:09:00 +0100742 ---help---
743 See USB1_VBUS_PIN help text.
744
Hans de Goede60fa6302016-03-18 08:42:01 +0100745config USB3_VBUS_PIN
746 string "Vbus enable pin for usb3 (ehci2)"
747 default ""
748 ---help---
749 See USB1_VBUS_PIN help text.
750
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200751config I2C0_ENABLE
752 bool "Enable I2C/TWI controller 0"
Chen-Yu Tsai409677e2016-11-30 15:30:30 +0800753 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200754 default n if MACH_SUN6I || MACH_SUN8I
Hans de Goede0878a8a2016-05-15 13:51:58 +0200755 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200756 ---help---
757 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
758 its clock and setting up the bus. This is especially useful on devices
759 with slaves connected to the bus or with pins exposed through e.g. an
760 expansion port/header.
761
762config I2C1_ENABLE
763 bool "Enable I2C/TWI controller 1"
764 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200765 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200766 ---help---
767 See I2C0_ENABLE help text.
768
769config I2C2_ENABLE
770 bool "Enable I2C/TWI controller 2"
771 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200772 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200773 ---help---
774 See I2C0_ENABLE help text.
775
776if MACH_SUN6I || MACH_SUN7I
777config I2C3_ENABLE
778 bool "Enable I2C/TWI controller 3"
779 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200780 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200781 ---help---
782 See I2C0_ENABLE help text.
783endif
784
Jernej Skrabec57e76232021-01-11 21:11:38 +0100785if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
Jelle van der Waa9d082682016-01-14 14:06:26 +0100786config R_I2C_ENABLE
787 bool "Enable the PRCM I2C/TWI controller"
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100788 # This is used for the pmic on H3
789 default y if SY8106A_POWER
Hans de Goede0878a8a2016-05-15 13:51:58 +0200790 select CMD_I2C
Jelle van der Waa9d082682016-01-14 14:06:26 +0100791 ---help---
792 Set this to y to enable the I2C controller which is part of the PRCM.
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100793endif
Jelle van der Waa9d082682016-01-14 14:06:26 +0100794
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200795if MACH_SUN7I
796config I2C4_ENABLE
797 bool "Enable I2C/TWI controller 4"
798 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200799 select CMD_I2C
Paul Kocialkowski6c739c52015-04-10 23:09:52 +0200800 ---help---
801 See I2C0_ENABLE help text.
802endif
803
Hans de Goede2fcf0332015-04-25 17:25:14 +0200804config AXP_GPIO
Masahiro Yamadaab650062016-08-12 10:26:50 +0900805 bool "Enable support for gpio-s on axp PMICs"
Hans de Goede2fcf0332015-04-25 17:25:14 +0200806 default n
807 ---help---
808 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
809
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800810config VIDEO_SUNXI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900811 bool "Enable graphical uboot console on HDMI, LCD or VGA"
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800812 depends on !MACH_SUN8I_A83T
813 depends on !MACH_SUNXI_H3_H5
Chen-Yu Tsai379feba2016-11-30 14:57:32 +0800814 depends on !MACH_SUN8I_R40
Icenowy Zhengc1994892017-04-08 15:30:12 +0800815 depends on !MACH_SUN8I_V3S
Chen-Yu Tsai301791c2017-03-02 16:03:06 +0800816 depends on !MACH_SUN9I
817 depends on !MACH_SUN50I
Jernej Skrabec44726092021-01-11 21:11:34 +0100818 depends on !SUN50I_GEN_H6
Jagan Teki5d235322021-02-22 00:12:34 +0000819 select DM_VIDEO
820 select DISPLAY
Icenowy Zhengf6bdddc2017-10-26 11:14:46 +0800821 imply VIDEO_DT_SIMPLEFB
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200822 default y
823 ---help---
Jagan Teki5d235322021-02-22 00:12:34 +0000824 Say Y here to add support for using a graphical console on the HDMI,
825 LCD or VGA output found on older sunxi devices. This will also provide
826 a simple_framebuffer device for Linux.
Hans de Goede2dae8002014-12-21 16:28:32 +0100827
Hans de Goede2fbf0912014-12-23 23:04:35 +0100828config VIDEO_HDMI
Masahiro Yamadaab650062016-08-12 10:26:50 +0900829 bool "HDMI output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800830 depends on VIDEO_SUNXI && !MACH_SUN8I
Hans de Goede2fbf0912014-12-23 23:04:35 +0100831 default y
832 ---help---
833 Say Y here to add support for outputting video over HDMI.
834
Hans de Goeded9786d22014-12-25 13:58:06 +0100835config VIDEO_VGA
Masahiro Yamadaab650062016-08-12 10:26:50 +0900836 bool "VGA output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800837 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
Hans de Goeded9786d22014-12-25 13:58:06 +0100838 default n
839 ---help---
840 Say Y here to add support for outputting video over VGA.
841
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100842config VIDEO_VGA_VIA_LCD
Masahiro Yamadaab650062016-08-12 10:26:50 +0900843 bool "VGA via LCD controller support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800844 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
Hans de Goedee2bbdfb2014-12-24 12:17:07 +0100845 default n
846 ---help---
847 Say Y here to add support for external DACs connected to the parallel
848 LCD interface driving a VGA connector, such as found on the
849 Olimex A13 boards.
850
Hans de Goedefb75d972015-01-25 15:33:07 +0100851config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
Masahiro Yamadaab650062016-08-12 10:26:50 +0900852 bool "Force sync active high for VGA via LCD controller support"
Hans de Goedefb75d972015-01-25 15:33:07 +0100853 depends on VIDEO_VGA_VIA_LCD
854 default n
855 ---help---
856 Say Y here if you've a board which uses opendrain drivers for the vga
857 hsync and vsync signals. Opendrain drivers cannot generate steep enough
858 positive edges for a stable video output, so on boards with opendrain
859 drivers the sync signals must always be active high.
860
Chen-Yu Tsai507e27d2015-01-12 18:02:11 +0800861config VIDEO_VGA_EXTERNAL_DAC_EN
862 string "LCD panel power enable pin"
863 depends on VIDEO_VGA_VIA_LCD
864 default ""
865 ---help---
866 Set the enable pin for the external VGA DAC. This takes a string in the
867 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
868
Hans de Goede39920c82015-08-03 19:20:26 +0200869config VIDEO_COMPOSITE
Masahiro Yamadaab650062016-08-12 10:26:50 +0900870 bool "Composite video output support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800871 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
Hans de Goede39920c82015-08-03 19:20:26 +0200872 default n
873 ---help---
874 Say Y here to add support for outputting composite video.
875
Hans de Goede2dae8002014-12-21 16:28:32 +0100876config VIDEO_LCD_MODE
877 string "LCD panel timing details"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800878 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100879 default ""
880 ---help---
881 LCD panel timing details string, leave empty if there is no LCD panel.
882 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
883 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
Hans de Goede8addd3e2015-08-16 11:23:42 +0200884 Also see: http://linux-sunxi.org/LCD
Hans de Goede2dae8002014-12-21 16:28:32 +0100885
Hans de Goede65150322015-01-13 13:21:46 +0100886config VIDEO_LCD_DCLK_PHASE
887 int "LCD panel display clock phase"
Vasily Khoruzhick1d7eef32017-10-26 21:51:52 -0700888 depends on VIDEO_SUNXI || DM_VIDEO
Hans de Goede65150322015-01-13 13:21:46 +0100889 default 1
890 ---help---
891 Select LCD panel display clock phase shift, range 0-3.
892
Hans de Goede2dae8002014-12-21 16:28:32 +0100893config VIDEO_LCD_POWER
894 string "LCD panel power enable pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800895 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100896 default ""
897 ---help---
898 Set the power enable pin for the LCD panel. This takes a string in the
899 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
900
Hans de Goede242e3d82015-02-16 17:26:41 +0100901config VIDEO_LCD_RESET
902 string "LCD panel reset pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800903 depends on VIDEO_SUNXI
Hans de Goede242e3d82015-02-16 17:26:41 +0100904 default ""
905 ---help---
906 Set the reset pin for the LCD panel. This takes a string in the format
907 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
908
Hans de Goede2dae8002014-12-21 16:28:32 +0100909config VIDEO_LCD_BL_EN
910 string "LCD panel backlight enable pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800911 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100912 default ""
913 ---help---
914 Set the backlight enable pin for the LCD panel. This takes a string in the
915 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
916 port H.
917
918config VIDEO_LCD_BL_PWM
919 string "LCD panel backlight pwm pin"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800920 depends on VIDEO_SUNXI
Hans de Goede2dae8002014-12-21 16:28:32 +0100921 default ""
922 ---help---
923 Set the backlight pwm pin for the LCD panel. This takes a string in the
924 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
Luc Verhaegen7f2c5212014-08-13 07:55:06 +0200925
Hans de Goedea7403ae2015-01-22 21:02:42 +0100926config VIDEO_LCD_BL_PWM_ACTIVE_LOW
927 bool "LCD panel backlight pwm is inverted"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800928 depends on VIDEO_SUNXI
Hans de Goedea7403ae2015-01-22 21:02:42 +0100929 default y
930 ---help---
931 Set this if the backlight pwm output is active low.
932
Hans de Goede55410082015-02-16 17:23:25 +0100933config VIDEO_LCD_PANEL_I2C
934 bool "LCD panel needs to be configured via i2c"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800935 depends on VIDEO_SUNXI
Hans de Goede1fc42012015-03-07 12:00:02 +0100936 default n
Hans de Goede0878a8a2016-05-15 13:51:58 +0200937 select CMD_I2C
Hans de Goede55410082015-02-16 17:23:25 +0100938 ---help---
939 Say y here if the LCD panel needs to be configured via i2c. This
940 will add a bitbang i2c controller using gpios to talk to the LCD.
941
942config VIDEO_LCD_PANEL_I2C_SDA
943 string "LCD panel i2c interface SDA pin"
944 depends on VIDEO_LCD_PANEL_I2C
945 default "PG12"
946 ---help---
947 Set the SDA pin for the LCD i2c interface. This takes a string in the
948 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
949
950config VIDEO_LCD_PANEL_I2C_SCL
951 string "LCD panel i2c interface SCL pin"
952 depends on VIDEO_LCD_PANEL_I2C
953 default "PG10"
954 ---help---
955 Set the SCL pin for the LCD i2c interface. This takes a string in the
956 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
957
Hans de Goede213480e2015-01-01 22:04:34 +0100958
959# Note only one of these may be selected at a time! But hidden choices are
960# not supported by Kconfig
961config VIDEO_LCD_IF_PARALLEL
962 bool
963
964config VIDEO_LCD_IF_LVDS
965 bool
966
Jernej Skrabec1ae5def2017-03-27 19:22:31 +0200967config SUNXI_DE2
968 bool
969 default n
970
Jernej Skrabec56009452017-03-27 19:22:32 +0200971config VIDEO_DE2
972 bool "Display Engine 2 video driver"
973 depends on SUNXI_DE2
974 select DM_VIDEO
975 select DISPLAY
Jernej Skrabec599177e2021-03-06 20:54:19 +0100976 select VIDEO_DW_HDMI
Icenowy Zhengbe5b96f2017-10-26 11:14:47 +0800977 imply VIDEO_DT_SIMPLEFB
Jernej Skrabec56009452017-03-27 19:22:32 +0200978 default y
979 ---help---
980 Say y here if you want to build DE2 video driver which is present on
981 newer SoCs. Currently only HDMI output is supported.
982
Hans de Goede213480e2015-01-01 22:04:34 +0100983
984choice
985 prompt "LCD panel support"
Icenowy Zheng401a3ca2017-10-26 11:14:44 +0800986 depends on VIDEO_SUNXI
Hans de Goede213480e2015-01-01 22:04:34 +0100987 ---help---
988 Select which type of LCD panel to support.
989
990config VIDEO_LCD_PANEL_PARALLEL
991 bool "Generic parallel interface LCD panel"
992 select VIDEO_LCD_IF_PARALLEL
993
994config VIDEO_LCD_PANEL_LVDS
995 bool "Generic lvds interface LCD panel"
996 select VIDEO_LCD_IF_LVDS
997
Siarhei Siamashka97ece832015-01-19 05:23:33 +0200998config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
999 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
1000 select VIDEO_LCD_SSD2828
1001 select VIDEO_LCD_IF_PARALLEL
1002 ---help---
Hans de Goedec1cfd512015-08-08 16:13:53 +02001003 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
1004
1005config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
1006 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
1007 select VIDEO_LCD_ANX9804
1008 select VIDEO_LCD_IF_PARALLEL
1009 select VIDEO_LCD_PANEL_I2C
1010 ---help---
1011 Select this for eDP LCD panels with 4 lanes running at 1.62G,
1012 connected via an ANX9804 bridge chip.
Siarhei Siamashka97ece832015-01-19 05:23:33 +02001013
Hans de Goede27515b22015-01-20 09:23:36 +01001014config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
1015 bool "Hitachi tx18d42vm LCD panel"
1016 select VIDEO_LCD_HITACHI_TX18D42VM
1017 select VIDEO_LCD_IF_LVDS
1018 ---help---
1019 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
1020
Hans de Goedeaad2ac22015-02-16 17:49:47 +01001021config VIDEO_LCD_TL059WV5C0
1022 bool "tl059wv5c0 LCD panel"
1023 select VIDEO_LCD_PANEL_I2C
1024 select VIDEO_LCD_IF_PARALLEL
1025 ---help---
1026 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
1027 Aigo M60/M608/M606 tablets.
1028
Hans de Goede213480e2015-01-01 22:04:34 +01001029endchoice
1030
Mylène Josserandd7b560e2017-04-02 12:59:09 +02001031config SATAPWR
1032 string "SATA power pin"
1033 default ""
1034 help
1035 Set the pins used to power the SATA. This takes a string in the
1036 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
1037 port H.
Hans de Goede213480e2015-01-01 22:04:34 +01001038
Hans de Goedec13f60d2015-01-25 12:10:48 +01001039config GMAC_TX_DELAY
1040 int "GMAC Transmit Clock Delay Chain"
1041 default 0
1042 ---help---
1043 Set the GMAC Transmit Clock Delay Chain value.
1044
Hans de Goedeff42d102015-09-13 13:02:48 +02001045config SPL_STACK_R_ADDR
Chen-Yu Tsai301791c2017-03-02 16:03:06 +08001046 default 0x4fe00000 if MACH_SUN4I
1047 default 0x4fe00000 if MACH_SUN5I
1048 default 0x4fe00000 if MACH_SUN6I
1049 default 0x4fe00000 if MACH_SUN7I
1050 default 0x4fe00000 if MACH_SUN8I
Hans de Goedeff42d102015-09-13 13:02:48 +02001051 default 0x2fe00000 if MACH_SUN9I
Chen-Yu Tsai301791c2017-03-02 16:03:06 +08001052 default 0x4fe00000 if MACH_SUN50I
Jernej Skrabec44726092021-01-11 21:11:34 +01001053 default 0x4fe00000 if SUN50I_GEN_H6
Hans de Goedeff42d102015-09-13 13:02:48 +02001054
Jagan Tekic2a7a7e2018-02-06 22:42:56 +05301055config SPL_SPI_SUNXI
1056 bool "Support for SPI Flash on Allwinner SoCs in SPL"
Andre Przywarafd40ad02020-01-28 00:46:43 +00001057 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || MACH_SUN50I_H6
Jagan Tekic2a7a7e2018-02-06 22:42:56 +05301058 help
1059 Enable support for SPI Flash. This option allows SPL to read from
1060 sunxi SPI Flash. It uses the same method as the boot ROM, so does
1061 not need any extra configuration.
1062
Icenowy Zhengc6c2c852018-10-25 17:23:02 +08001063config PINE64_DT_SELECTION
1064 bool "Enable Pine64 device tree selection code"
1065 depends on MACH_SUN50I
1066 help
1067 The original Pine A64 and Pine A64+ are similar but different
1068 boards and can be differed by the DRAM size. Pine A64 has
1069 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
1070 option, the device tree selection code specific to Pine64 which
1071 utilizes the DRAM size will be enabled.
1072
Samuel Holland8a8b73b2020-10-24 10:21:52 -05001073config PINEPHONE_DT_SELECTION
1074 bool "Enable PinePhone device tree selection code"
1075 depends on MACH_SUN50I
1076 help
1077 Enable this option to automatically select the device tree for the
1078 correct PinePhone hardware revision during boot.
1079
Andre Heider9267ff82021-10-01 19:29:00 +01001080config BLUETOOTH_DT_DEVICE_FIXUP
1081 string "Fixup the Bluetooth controller address"
1082 default ""
1083 help
1084 This option specifies the DT compatible name of the Bluetooth
1085 controller for which to set the "local-bd-address" property.
1086 Set this option if your device ships with the Bluetooth controller
1087 default address.
1088 The used address is "bdaddr" if set, and "ethaddr" with the LSB
1089 flipped elsewise.
1090
Masahiro Yamadadd840582014-07-30 14:08:14 +09001091endif
Kory Maincent6c2c7e92021-05-04 19:31:27 +02001092
1093config CHIP_DIP_SCAN
1094 bool "Enable DIPs detection for CHIP board"
1095 select SUPPORT_EXTENSION_SCAN
1096 select W1
1097 select W1_GPIO
1098 select W1_EEPROM
1099 select W1_EEPROM_DS24XXX
1100 select CMD_EXTENSION