blob: e27d106466b4dfca0638be4f9fdb136c2f0dfaa1 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060062 };
63
Rasmus Villemoes8c728422021-04-21 11:06:55 +020064 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060065 testing-bool;
66 testing-int = <123>;
67 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020068 environment {
69 from_fdt = "yes";
70 fdt_env_path = "";
71 };
72 };
73
Nandor Hanf9db2f12021-06-10 16:56:44 +030074 reboot-mode0 {
75 compatible = "reboot-mode-gpio";
76 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
77 u-boot,env-variable = "bootstatus";
78 mode-test = <0x01>;
79 mode-download = <0x03>;
80 };
81
Nandor Hanc74675b2021-06-10 16:56:45 +030082 reboot_mode1: reboot-mode@14 {
83 compatible = "reboot-mode-rtc";
84 rtc = <&rtc_0>;
85 reg = <0x30 4>;
86 u-boot,env-variable = "bootstatus";
87 big-endian;
88 mode-test = <0x21969147>;
89 mode-download = <0x51939147>;
90 };
91
Simon Glassce6d99a2018-12-10 10:37:33 -070092 audio: audio-codec {
93 compatible = "sandbox,audio-codec";
94 #sound-dai-cells = <1>;
95 };
96
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +020097 buttons {
98 compatible = "gpio-keys";
99
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200100 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200101 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200102 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200103 };
104
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200105 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200106 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200107 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200108 };
109 };
110
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100111 buttons2 {
112 compatible = "adc-keys";
113 io-channels = <&adc 3>;
114 keyup-threshold-microvolt = <3000000>;
115
116 button-up {
117 label = "button3";
118 linux,code = <KEY_F3>;
119 press-threshold-microvolt = <1500000>;
120 };
121
122 button-down {
123 label = "button4";
124 linux,code = <KEY_F4>;
125 press-threshold-microvolt = <1000000>;
126 };
127
128 button-enter {
129 label = "button5";
130 linux,code = <KEY_F5>;
131 press-threshold-microvolt = <500000>;
132 };
133 };
134
Simon Glasse96fa6c2018-12-10 10:37:34 -0700135 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600136 reg = <0 0>;
137 compatible = "google,cros-ec-sandbox";
138
139 /*
140 * This describes the flash memory within the EC. Note
141 * that the STM32L flash erases to 0, not 0xff.
142 */
143 flash {
144 image-pos = <0x08000000>;
145 size = <0x20000>;
146 erase-value = <0>;
147
148 /* Information for sandbox */
149 ro {
150 image-pos = <0>;
151 size = <0xf000>;
152 };
153 wp-ro {
154 image-pos = <0xf000>;
155 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700156 used = <0x884>;
157 compress = "lz4";
158 uncomp-size = <0xcf8>;
159 hash {
160 algo = "sha256";
161 value = [00 01 02 03 04 05 06 07
162 08 09 0a 0b 0c 0d 0e 0f
163 10 11 12 13 14 15 16 17
164 18 19 1a 1b 1c 1d 1e 1f];
165 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600166 };
167 rw {
168 image-pos = <0x10000>;
169 size = <0x10000>;
170 };
171 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300172
173 cros_ec_pwm: cros-ec-pwm {
174 compatible = "google,cros-ec-pwm";
175 #pwm-cells = <1>;
176 };
177
Simon Glasse6c5c942018-10-01 12:22:08 -0600178 };
179
Yannick Fertré23f965a2019-10-07 15:29:05 +0200180 dsi_host: dsi_host {
181 compatible = "sandbox,dsi-host";
182 };
183
Simon Glass2e7d35d2014-02-26 15:59:21 -0700184 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600185 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700186 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600187 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700188 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600189 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100190 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
191 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700192 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100193 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
194 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
195 <&gpio_b 7 GPIO_IN 3 2 1>,
196 <&gpio_b 8 GPIO_OUT 3 2 1>,
197 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100198 test3-gpios =
199 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
200 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
201 <&gpio_c 2 GPIO_OUT>,
202 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
203 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200204 <&gpio_c 5 GPIO_IN>,
205 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
206 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530207 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
208 test5-gpios = <&gpio_a 19>;
209
Simon Glassa1b17e42018-12-10 10:37:37 -0700210 int-value = <1234>;
211 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200212 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200213 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600214 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700215 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600216 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200217 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530218
219 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
220 <&muxcontroller0 2>, <&muxcontroller0 3>,
221 <&muxcontroller1>;
222 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
223 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100224 display-timings {
225 timing0: 240x320 {
226 clock-frequency = <6500000>;
227 hactive = <240>;
228 vactive = <320>;
229 hfront-porch = <6>;
230 hback-porch = <7>;
231 hsync-len = <1>;
232 vback-porch = <5>;
233 vfront-porch = <8>;
234 vsync-len = <2>;
235 hsync-active = <1>;
236 vsync-active = <0>;
237 de-active = <1>;
238 pixelclk-active = <1>;
239 interlaced;
240 doublescan;
241 doubleclk;
242 };
243 timing1: 480x800 {
244 clock-frequency = <9000000>;
245 hactive = <480>;
246 vactive = <800>;
247 hfront-porch = <10>;
248 hback-porch = <59>;
249 hsync-len = <12>;
250 vback-porch = <15>;
251 vfront-porch = <17>;
252 vsync-len = <16>;
253 hsync-active = <0>;
254 vsync-active = <1>;
255 de-active = <0>;
256 pixelclk-active = <0>;
257 };
258 timing2: 800x480 {
259 clock-frequency = <33500000>;
260 hactive = <800>;
261 vactive = <480>;
262 hback-porch = <89>;
263 hfront-porch = <164>;
264 vback-porch = <23>;
265 vfront-porch = <10>;
266 hsync-len = <11>;
267 vsync-len = <13>;
268 };
269 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700270 };
271
272 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600273 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700274 compatible = "not,compatible";
275 };
276
277 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600278 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700279 };
280
Simon Glass5d9a88f2018-10-01 12:22:40 -0600281 backlight: backlight {
282 compatible = "pwm-backlight";
283 enable-gpios = <&gpio_a 1>;
284 power-supply = <&ldo_1>;
285 pwms = <&pwm 0 1000>;
286 default-brightness-level = <5>;
287 brightness-levels = <0 16 32 64 128 170 202 234 255>;
288 };
289
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200290 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200291 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200292 bind-test-child1 {
293 compatible = "sandbox,phy";
294 #phy-cells = <1>;
295 };
296
297 bind-test-child2 {
298 compatible = "simple-bus";
299 };
300 };
301
Simon Glass2e7d35d2014-02-26 15:59:21 -0700302 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600303 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700304 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600305 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700306 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530307
308 mux-controls = <&muxcontroller0 0>;
309 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700310 };
311
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200312 phy_provider0: gen_phy@0 {
313 compatible = "sandbox,phy";
314 #phy-cells = <1>;
315 };
316
317 phy_provider1: gen_phy@1 {
318 compatible = "sandbox,phy";
319 #phy-cells = <0>;
320 broken;
321 };
322
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200323 phy_provider2: gen_phy@2 {
324 compatible = "sandbox,phy";
325 #phy-cells = <0>;
326 };
327
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200328 gen_phy_user: gen_phy_user {
329 compatible = "simple-bus";
330 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
331 phy-names = "phy1", "phy2", "phy3";
332 };
333
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200334 gen_phy_user1: gen_phy_user1 {
335 compatible = "simple-bus";
336 phys = <&phy_provider0 0>, <&phy_provider2>;
337 phy-names = "phy1", "phy2";
338 };
339
Simon Glass2e7d35d2014-02-26 15:59:21 -0700340 some-bus {
341 #address-cells = <1>;
342 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600343 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600344 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600345 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700346 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600347 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700348 compatible = "denx,u-boot-fdt-test";
349 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600350 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700351 ping-add = <5>;
352 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600353 c-test@0 {
354 compatible = "denx,u-boot-fdt-test";
355 reg = <0>;
356 ping-expect = <6>;
357 ping-add = <6>;
358 };
359 c-test@1 {
360 compatible = "denx,u-boot-fdt-test";
361 reg = <1>;
362 ping-expect = <7>;
363 ping-add = <7>;
364 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700365 };
366
367 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600368 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600369 ping-expect = <6>;
370 ping-add = <6>;
371 compatible = "google,another-fdt-test";
372 };
373
374 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600375 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600376 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700377 ping-add = <6>;
378 compatible = "google,another-fdt-test";
379 };
380
Simon Glass9cc36a22015-01-25 08:27:05 -0700381 f-test {
382 compatible = "denx,u-boot-fdt-test";
383 };
384
385 g-test {
386 compatible = "denx,u-boot-fdt-test";
387 };
388
Bin Meng2786cd72018-10-10 22:07:01 -0700389 h-test {
390 compatible = "denx,u-boot-fdt-test1";
391 };
392
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200393 i-test {
394 compatible = "mediatek,u-boot-fdt-test";
395 #address-cells = <1>;
396 #size-cells = <0>;
397
398 subnode@0 {
399 reg = <0>;
400 };
401
402 subnode@1 {
403 reg = <1>;
404 };
405
406 subnode@2 {
407 reg = <2>;
408 };
409 };
410
Simon Glassdc12ebb2019-12-29 21:19:25 -0700411 devres-test {
412 compatible = "denx,u-boot-devres-test";
413 };
414
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530415 another-test {
416 reg = <0 2>;
417 compatible = "denx,u-boot-fdt-test";
418 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
419 test5-gpios = <&gpio_a 19>;
420 };
421
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100422 mmio-bus@0 {
423 #address-cells = <1>;
424 #size-cells = <1>;
425 compatible = "denx,u-boot-test-bus";
426 dma-ranges = <0x10000000 0x00000000 0x00040000>;
427
428 subnode@0 {
429 compatible = "denx,u-boot-fdt-test";
430 };
431 };
432
433 mmio-bus@1 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100437
438 subnode@0 {
439 compatible = "denx,u-boot-fdt-test";
440 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100441 };
442
Simon Glass0f7b1112020-07-07 13:12:06 -0600443 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600444 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600445 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600446 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600447 child {
448 compatible = "denx,u-boot-acpi-test";
449 };
Simon Glassf50cc952020-04-08 16:57:34 -0600450 };
451
Simon Glass0f7b1112020-07-07 13:12:06 -0600452 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600453 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600454 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600455 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600456 };
457
Patrice Chotardee87a092017-09-04 14:55:57 +0200458 clocks {
459 clk_fixed: clk-fixed {
460 compatible = "fixed-clock";
461 #clock-cells = <0>;
462 clock-frequency = <1234>;
463 };
Anup Patelb630d572019-02-25 08:14:55 +0000464
465 clk_fixed_factor: clk-fixed-factor {
466 compatible = "fixed-factor-clock";
467 #clock-cells = <0>;
468 clock-div = <3>;
469 clock-mult = <2>;
470 clocks = <&clk_fixed>;
471 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200472
473 osc {
474 compatible = "fixed-clock";
475 #clock-cells = <0>;
476 clock-frequency = <20000000>;
477 };
Stephen Warren135aa952016-06-17 09:44:00 -0600478 };
479
480 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600481 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600482 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200483 assigned-clocks = <&clk_sandbox 3>;
484 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600485 };
486
487 clk-test {
488 compatible = "sandbox,clk-test";
489 clocks = <&clk_fixed>,
490 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200491 <&clk_sandbox 0>,
492 <&clk_sandbox 3>,
493 <&clk_sandbox 2>;
494 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600495 };
496
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200497 ccf: clk-ccf {
498 compatible = "sandbox,clk-ccf";
499 };
500
Simon Glass171e9912015-05-22 15:42:15 -0600501 eth@10002000 {
502 compatible = "sandbox,eth";
503 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500504 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600505 };
506
507 eth_5: eth@10003000 {
508 compatible = "sandbox,eth";
509 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500510 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600511 };
512
Bin Meng71d79712015-08-27 22:25:53 -0700513 eth_3: sbe5 {
514 compatible = "sandbox,eth";
515 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500516 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700517 };
518
Simon Glass171e9912015-05-22 15:42:15 -0600519 eth@10004000 {
520 compatible = "sandbox,eth";
521 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500522 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600523 };
524
Claudiu Manoilff98da02021-03-14 20:14:57 +0800525 dsa_eth0: dsa-test-eth {
526 compatible = "sandbox,eth";
527 reg = <0x10006000 0x1000>;
528 fake-host-hwaddr = [00 00 66 44 22 66];
529 };
530
531 dsa-test {
532 compatible = "sandbox,dsa";
533
534 ports {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 swp_0: port@0 {
538 reg = <0>;
539 label = "lan0";
540 phy-mode = "rgmii-rxid";
541
542 fixed-link {
543 speed = <100>;
544 full-duplex;
545 };
546 };
547
548 swp_1: port@1 {
549 reg = <1>;
550 label = "lan1";
551 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800552 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800553 };
554
555 port@2 {
556 reg = <2>;
557 ethernet = <&dsa_eth0>;
558
559 fixed-link {
560 speed = <1000>;
561 full-duplex;
562 };
563 };
564 };
565 };
566
Rajan Vaja31b82172018-09-19 03:43:46 -0700567 firmware {
568 sandbox_firmware: sandbox-firmware {
569 compatible = "sandbox,firmware";
570 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200571
572 sandbox-scmi-agent@0 {
573 compatible = "sandbox,scmi-agent";
574 #address-cells = <1>;
575 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200576
577 clk_scmi0: protocol@14 {
578 reg = <0x14>;
579 #clock-cells = <1>;
580 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200581
582 reset_scmi0: protocol@16 {
583 reg = <0x16>;
584 #reset-cells = <1>;
585 };
Etienne Carriere01242182021-03-08 22:38:07 +0100586
587 protocol@17 {
588 reg = <0x17>;
589
590 regulators {
591 #address-cells = <1>;
592 #size-cells = <0>;
593
594 regul0_scmi0: reg@0 {
595 reg = <0>;
596 regulator-name = "sandbox-voltd0";
597 regulator-min-microvolt = <1100000>;
598 regulator-max-microvolt = <3300000>;
599 };
600 regul1_scmi0: reg@1 {
601 reg = <0x1>;
602 regulator-name = "sandbox-voltd1";
603 regulator-min-microvolt = <1800000>;
604 };
605 };
606 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200607 };
608
609 sandbox-scmi-agent@1 {
610 compatible = "sandbox,scmi-agent";
611 #address-cells = <1>;
612 #size-cells = <0>;
613
Etienne Carriere87d4f272020-09-09 18:44:05 +0200614 clk_scmi1: protocol@14 {
615 reg = <0x14>;
616 #clock-cells = <1>;
617 };
618
Etienne Carriere358599e2020-09-09 18:44:00 +0200619 protocol@10 {
620 reg = <0x10>;
621 };
622 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700623 };
624
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100625 pinctrl-gpio {
626 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700627
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100628 gpio_a: base-gpios {
629 compatible = "sandbox,gpio";
630 gpio-controller;
631 #gpio-cells = <1>;
632 gpio-bank-name = "a";
633 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200634 hog_input_active_low {
635 gpio-hog;
636 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200637 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200638 };
639 hog_input_active_high {
640 gpio-hog;
641 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200642 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200643 };
644 hog_output_low {
645 gpio-hog;
646 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200647 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200648 };
649 hog_output_high {
650 gpio-hog;
651 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200652 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200653 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100654 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600655
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100656 gpio_b: extra-gpios {
657 compatible = "sandbox,gpio";
658 gpio-controller;
659 #gpio-cells = <5>;
660 gpio-bank-name = "b";
661 sandbox,gpio-count = <10>;
662 };
663
664 gpio_c: pinmux-gpios {
665 compatible = "sandbox,gpio";
666 gpio-controller;
667 #gpio-cells = <2>;
668 gpio-bank-name = "c";
669 sandbox,gpio-count = <10>;
670 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100671 };
672
Simon Glassecc2ed52014-12-10 08:55:55 -0700673 i2c@0 {
674 #address-cells = <1>;
675 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600676 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700677 compatible = "sandbox,i2c";
678 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200679 pinctrl-names = "default";
680 pinctrl-0 = <&pinmux_i2c0_pins>;
681
Simon Glassecc2ed52014-12-10 08:55:55 -0700682 eeprom@2c {
683 reg = <0x2c>;
684 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700685 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200686 partitions {
687 compatible = "fixed-partitions";
688 #address-cells = <1>;
689 #size-cells = <1>;
690 bootcount_i2c: bootcount@10 {
691 reg = <10 2>;
692 };
693 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700694 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200695
Simon Glass52d3bc52015-05-22 15:42:17 -0600696 rtc_0: rtc@43 {
697 reg = <0x43>;
698 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700699 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600700 };
701
702 rtc_1: rtc@61 {
703 reg = <0x61>;
704 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700705 sandbox,emul = <&emul1>;
706 };
707
708 i2c_emul: emul {
709 reg = <0xff>;
710 compatible = "sandbox,i2c-emul-parent";
711 emul_eeprom: emul-eeprom {
712 compatible = "sandbox,i2c-eeprom";
713 sandbox,filename = "i2c.bin";
714 sandbox,size = <256>;
715 };
716 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700717 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700718 };
719 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700720 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600721 };
722 };
723
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200724 sandbox_pmic: sandbox_pmic {
725 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700726 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200727 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200728
729 mc34708: pmic@41 {
730 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700731 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200732 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700733 };
734
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100735 bootcount@0 {
736 compatible = "u-boot,bootcount-rtc";
737 rtc = <&rtc_1>;
738 offset = <0x13>;
739 };
740
Michal Simekf692b472020-05-28 11:48:55 +0200741 bootcount {
742 compatible = "u-boot,bootcount-i2c-eeprom";
743 i2c-eeprom = <&bootcount_i2c>;
744 };
745
Nandor Hanc50b21b2021-06-10 15:40:38 +0300746 bootcount_4@0 {
747 compatible = "u-boot,bootcount-syscon";
748 syscon = <&syscon0>;
749 reg = <0x0 0x04>, <0x0 0x04>;
750 reg-names = "syscon_reg", "offset";
751 };
752
753 bootcount_2@0 {
754 compatible = "u-boot,bootcount-syscon";
755 syscon = <&syscon0>;
756 reg = <0x0 0x04>, <0x0 0x02> ;
757 reg-names = "syscon_reg", "offset";
758 };
759
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100760 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100761 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100762 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100763 vdd-supply = <&buck2>;
764 vss-microvolts = <0>;
765 };
766
Simon Glass02554352020-02-06 09:55:00 -0700767 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700768 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700769 interrupt-controller;
770 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700771 };
772
Simon Glass3c97c4f2016-01-18 19:52:26 -0700773 lcd {
774 u-boot,dm-pre-reloc;
775 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200776 pinctrl-names = "default";
777 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700778 xres = <1366>;
779 yres = <768>;
780 };
781
Simon Glass3c43fba2015-07-06 12:54:34 -0600782 leds {
783 compatible = "gpio-leds";
784
785 iracibble {
786 gpios = <&gpio_a 1 0>;
787 label = "sandbox:red";
788 };
789
790 martinet {
791 gpios = <&gpio_a 2 0>;
792 label = "sandbox:green";
793 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200794
795 default_on {
796 gpios = <&gpio_a 5 0>;
797 label = "sandbox:default_on";
798 default-state = "on";
799 };
800
801 default_off {
802 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400803 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200804 default-state = "off";
805 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600806 };
807
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200808 gpio-wdt {
809 gpios = <&gpio_a 7 0>;
810 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200811 hw_margin_ms = <100>;
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200812 always-running;
813 };
814
Stephen Warren8961b522016-05-16 17:41:37 -0600815 mbox: mbox {
816 compatible = "sandbox,mbox";
817 #mbox-cells = <1>;
818 };
819
820 mbox-test {
821 compatible = "sandbox,mbox-test";
822 mboxes = <&mbox 100>, <&mbox 1>;
823 mbox-names = "other", "test";
824 };
825
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900826 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200827 #address-cells = <1>;
828 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400829 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200830 cpu1: cpu@1 {
831 device_type = "cpu";
832 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400833 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900834 compatible = "sandbox,cpu_sandbox";
835 u-boot,dm-pre-reloc;
836 };
Mario Sixfa44b532018-08-06 10:23:44 +0200837
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200838 cpu2: cpu@2 {
839 device_type = "cpu";
840 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900841 compatible = "sandbox,cpu_sandbox";
842 u-boot,dm-pre-reloc;
843 };
Mario Sixfa44b532018-08-06 10:23:44 +0200844
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200845 cpu3: cpu@3 {
846 device_type = "cpu";
847 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900848 compatible = "sandbox,cpu_sandbox";
849 u-boot,dm-pre-reloc;
850 };
Mario Sixfa44b532018-08-06 10:23:44 +0200851 };
852
Dave Gerlach21e3c212020-07-15 23:39:58 -0500853 chipid: chipid {
854 compatible = "sandbox,soc";
855 };
856
Simon Glasse96fa6c2018-12-10 10:37:34 -0700857 i2s: i2s {
858 compatible = "sandbox,i2s";
859 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700860 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700861 };
862
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200863 nop-test_0 {
864 compatible = "sandbox,nop_sandbox1";
865 nop-test_1 {
866 compatible = "sandbox,nop_sandbox2";
867 bind = "True";
868 };
869 nop-test_2 {
870 compatible = "sandbox,nop_sandbox2";
871 bind = "False";
872 };
873 };
874
Mario Six004e67c2018-07-31 14:24:14 +0200875 misc-test {
876 compatible = "sandbox,misc_sandbox";
877 };
878
Simon Glasse48eeb92017-04-23 20:02:07 -0600879 mmc2 {
880 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -0600881 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -0600882 };
883
884 mmc1 {
885 compatible = "sandbox,mmc";
886 };
887
888 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600889 compatible = "sandbox,mmc";
890 };
891
Simon Glassb45c8332019-02-16 20:24:50 -0700892 pch {
893 compatible = "sandbox,pch";
894 };
895
Tom Rini42c64d12020-02-11 12:41:23 -0500896 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700897 compatible = "sandbox,pci";
898 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500899 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700900 #address-cells = <3>;
901 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600902 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700903 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700904 pci@0,0 {
905 compatible = "pci-generic";
906 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600907 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700908 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300909 pci@1,0 {
910 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600911 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
912 reg = <0x02000814 0 0 0 0
913 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600914 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300915 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700916 p2sb-pci@2,0 {
917 compatible = "sandbox,p2sb";
918 reg = <0x02001010 0 0 0 0>;
919 sandbox,emul = <&p2sb_emul>;
920
921 adder {
922 intel,p2sb-port-id = <3>;
923 compatible = "sandbox,adder";
924 };
925 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700926 pci@1e,0 {
927 compatible = "sandbox,pmc";
928 reg = <0xf000 0 0 0 0>;
929 sandbox,emul = <&pmc_emul1e>;
930 acpi-base = <0x400>;
931 gpe0-dwx-mask = <0xf>;
932 gpe0-dwx-shift-base = <4>;
933 gpe0-dw = <6 7 9>;
934 gpe0-sts = <0x20>;
935 gpe0-en = <0x30>;
936 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700937 pci@1f,0 {
938 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600939 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
940 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600941 sandbox,emul = <&swap_case_emul0_1f>;
942 };
943 };
944
945 pci-emul0 {
946 compatible = "sandbox,pci-emul-parent";
947 swap_case_emul0_0: emul0@0,0 {
948 compatible = "sandbox,swap-case";
949 };
950 swap_case_emul0_1: emul0@1,0 {
951 compatible = "sandbox,swap-case";
952 use-ea;
953 };
954 swap_case_emul0_1f: emul0@1f,0 {
955 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700956 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700957 p2sb_emul: emul@2,0 {
958 compatible = "sandbox,p2sb-emul";
959 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700960 pmc_emul1e: emul@1e,0 {
961 compatible = "sandbox,pmc-emul";
962 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700963 };
964
Tom Rini42c64d12020-02-11 12:41:23 -0500965 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700966 compatible = "sandbox,pci";
967 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500968 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700969 #address-cells = <3>;
970 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700971 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
972 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
973 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700974 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200975 0x0c 0x00 0x1234 0x5678
976 0x10 0x00 0x1234 0x5678>;
977 pci@10,0 {
978 reg = <0x8000 0 0 0 0>;
979 };
Bin Mengdee4d752018-08-03 01:14:41 -0700980 };
981
Tom Rini42c64d12020-02-11 12:41:23 -0500982 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700983 compatible = "sandbox,pci";
984 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500985 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700986 #address-cells = <3>;
987 #size-cells = <2>;
988 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
989 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
990 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
991 pci@1f,0 {
992 compatible = "pci-generic";
993 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600994 sandbox,emul = <&swap_case_emul2_1f>;
995 };
996 };
997
998 pci-emul2 {
999 compatible = "sandbox,pci-emul-parent";
1000 swap_case_emul2_1f: emul2@1f,0 {
1001 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001002 };
1003 };
1004
Ramon Friedbb413332019-04-27 11:15:23 +03001005 pci_ep: pci_ep {
1006 compatible = "sandbox,pci_ep";
1007 };
1008
Simon Glass98561572017-04-23 20:10:44 -06001009 probing {
1010 compatible = "simple-bus";
1011 test1 {
1012 compatible = "denx,u-boot-probe-test";
1013 };
1014
1015 test2 {
1016 compatible = "denx,u-boot-probe-test";
1017 };
1018
1019 test3 {
1020 compatible = "denx,u-boot-probe-test";
1021 };
1022
1023 test4 {
1024 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001025 first-syscon = <&syscon0>;
1026 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001027 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001028 };
1029 };
1030
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001031 pwrdom: power-domain {
1032 compatible = "sandbox,power-domain";
1033 #power-domain-cells = <1>;
1034 };
1035
1036 power-domain-test {
1037 compatible = "sandbox,power-domain-test";
1038 power-domains = <&pwrdom 2>;
1039 };
1040
Simon Glass5d9a88f2018-10-01 12:22:40 -06001041 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001042 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001043 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001044 pinctrl-names = "default";
1045 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001046 };
1047
1048 pwm2 {
1049 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001050 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001051 };
1052
Simon Glass64ce0ca2015-07-06 12:54:31 -06001053 ram {
1054 compatible = "sandbox,ram";
1055 };
1056
Simon Glass5010d982015-07-06 12:54:29 -06001057 reset@0 {
1058 compatible = "sandbox,warm-reset";
1059 };
1060
1061 reset@1 {
1062 compatible = "sandbox,reset";
1063 };
1064
Stephen Warren4581b712016-06-17 09:43:59 -06001065 resetc: reset-ctl {
1066 compatible = "sandbox,reset-ctl";
1067 #reset-cells = <1>;
1068 };
1069
1070 reset-ctl-test {
1071 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001072 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1073 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001074 };
1075
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301076 rng {
1077 compatible = "sandbox,sandbox-rng";
1078 };
1079
Nishanth Menon52159402015-09-17 15:42:41 -05001080 rproc_1: rproc@1 {
1081 compatible = "sandbox,test-processor";
1082 remoteproc-name = "remoteproc-test-dev1";
1083 };
1084
1085 rproc_2: rproc@2 {
1086 compatible = "sandbox,test-processor";
1087 internal-memory-mapped;
1088 remoteproc-name = "remoteproc-test-dev2";
1089 };
1090
Simon Glass5d9a88f2018-10-01 12:22:40 -06001091 panel {
1092 compatible = "simple-panel";
1093 backlight = <&backlight 0 100>;
1094 };
1095
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001096 smem@0 {
1097 compatible = "sandbox,smem";
1098 };
1099
Simon Glassd4901892018-12-10 10:37:36 -07001100 sound {
1101 compatible = "sandbox,sound";
1102 cpu {
1103 sound-dai = <&i2s 0>;
1104 };
1105
1106 codec {
1107 sound-dai = <&audio 0>;
1108 };
1109 };
1110
Simon Glass0ae0cb72014-10-13 23:42:11 -06001111 spi@0 {
1112 #address-cells = <1>;
1113 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001114 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001115 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001116 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001117 pinctrl-names = "default";
1118 pinctrl-0 = <&pinmux_spi0_pins>;
1119
Simon Glass0ae0cb72014-10-13 23:42:11 -06001120 spi.bin@0 {
1121 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001122 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001123 spi-max-frequency = <40000000>;
1124 sandbox,filename = "spi.bin";
1125 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001126 spi.bin@1 {
1127 reg = <1>;
1128 compatible = "spansion,m25p16", "jedec,spi-nor";
1129 spi-max-frequency = <50000000>;
1130 sandbox,filename = "spi.bin";
1131 spi-cpol;
1132 spi-cpha;
1133 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001134 };
1135
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001136 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001137 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001138 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001139 };
1140
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001141 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001142 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001143 reg = <0x20 5
1144 0x28 6
1145 0x30 7
1146 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001147 };
1148
Patrick Delaunaya442e612019-03-07 09:57:13 +01001149 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001150 compatible = "simple-mfd", "syscon";
1151 reg = <0x40 5
1152 0x48 6
1153 0x50 7
1154 0x58 8>;
1155 };
1156
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301157 syscon3: syscon@3 {
1158 compatible = "simple-mfd", "syscon";
1159 reg = <0x000100 0x10>;
1160
1161 muxcontroller0: a-mux-controller {
1162 compatible = "mmio-mux";
1163 #mux-control-cells = <1>;
1164
1165 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1166 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1167 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1168 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1169 u-boot,mux-autoprobe;
1170 };
1171 };
1172
1173 muxcontroller1: emul-mux-controller {
1174 compatible = "mux-emul";
1175 #mux-control-cells = <0>;
1176 u-boot,mux-autoprobe;
1177 idle-state = <0xabcd>;
1178 };
1179
Simon Glass93f44e82020-12-16 21:20:27 -07001180 testfdtm0 {
1181 compatible = "denx,u-boot-fdtm-test";
1182 };
1183
1184 testfdtm1: testfdtm1 {
1185 compatible = "denx,u-boot-fdtm-test";
1186 };
1187
1188 testfdtm2 {
1189 compatible = "denx,u-boot-fdtm-test";
1190 };
1191
Sean Anderson7616e362020-09-28 10:52:23 -04001192 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001193 compatible = "sandbox,timer";
1194 clock-frequency = <1000000>;
1195 };
1196
Sean Anderson7616e362020-09-28 10:52:23 -04001197 timer@1 {
1198 compatible = "sandbox,timer";
1199 sandbox,timebase-frequency-fallback;
1200 };
1201
Miquel Raynalb91ad162018-05-15 11:57:27 +02001202 tpm2 {
1203 compatible = "sandbox,tpm2";
1204 };
1205
Simon Glass171e9912015-05-22 15:42:15 -06001206 uart0: serial {
1207 compatible = "sandbox,serial";
1208 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001209 pinctrl-names = "default";
1210 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001211 };
1212
Simon Glasse00cb222015-03-25 12:23:05 -06001213 usb_0: usb@0 {
1214 compatible = "sandbox,usb";
1215 status = "disabled";
1216 hub {
1217 compatible = "sandbox,usb-hub";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 flash-stick {
1221 reg = <0>;
1222 compatible = "sandbox,usb-flash";
1223 };
1224 };
1225 };
1226
1227 usb_1: usb@1 {
1228 compatible = "sandbox,usb";
1229 hub {
1230 compatible = "usb-hub";
1231 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001232 #address-cells = <1>;
1233 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001234 hub-emul {
1235 compatible = "sandbox,usb-hub";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001238 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001239 reg = <0>;
1240 compatible = "sandbox,usb-flash";
1241 sandbox,filepath = "testflash.bin";
1242 };
1243
Simon Glass431cbd62015-11-08 23:48:01 -07001244 flash-stick@1 {
1245 reg = <1>;
1246 compatible = "sandbox,usb-flash";
1247 sandbox,filepath = "testflash1.bin";
1248 };
1249
1250 flash-stick@2 {
1251 reg = <2>;
1252 compatible = "sandbox,usb-flash";
1253 sandbox,filepath = "testflash2.bin";
1254 };
1255
Simon Glassbff1a712015-11-08 23:48:08 -07001256 keyb@3 {
1257 reg = <3>;
1258 compatible = "sandbox,usb-keyb";
1259 };
1260
Simon Glasse00cb222015-03-25 12:23:05 -06001261 };
Michael Wallec03b7612020-06-02 01:47:07 +02001262
1263 usbstor@1 {
1264 reg = <1>;
1265 };
1266 usbstor@3 {
1267 reg = <3>;
1268 };
Simon Glasse00cb222015-03-25 12:23:05 -06001269 };
1270 };
1271
1272 usb_2: usb@2 {
1273 compatible = "sandbox,usb";
1274 status = "disabled";
1275 };
1276
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001277 spmi: spmi@0 {
1278 compatible = "sandbox,spmi";
1279 #address-cells = <0x1>;
1280 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001281 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001282 pm8916@0 {
1283 compatible = "qcom,spmi-pmic";
1284 reg = <0x0 0x1>;
1285 #address-cells = <0x1>;
1286 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001287 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001288
1289 spmi_gpios: gpios@c000 {
1290 compatible = "qcom,pm8916-gpio";
1291 reg = <0xc000 0x400>;
1292 gpio-controller;
1293 gpio-count = <4>;
1294 #gpio-cells = <2>;
1295 gpio-bank-name="spmi";
1296 };
1297 };
1298 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001299
1300 wdt0: wdt@0 {
1301 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001302 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001303 };
Rob Clarkf2006802018-01-10 11:33:30 +01001304
Mario Six957983e2018-08-09 14:51:19 +02001305 axi: axi@0 {
1306 compatible = "sandbox,axi";
1307 #address-cells = <0x1>;
1308 #size-cells = <0x1>;
1309 store@0 {
1310 compatible = "sandbox,sandbox_store";
1311 reg = <0x0 0x400>;
1312 };
1313 };
1314
Rob Clarkf2006802018-01-10 11:33:30 +01001315 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001316 #address-cells = <1>;
1317 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001318 setting = "sunrise ohoka";
1319 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001320 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001321 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001322 chosen-test {
1323 compatible = "denx,u-boot-fdt-test";
1324 reg = <9 1>;
1325 };
1326 };
Mario Sixe8d52912018-03-12 14:53:33 +01001327
1328 translation-test@8000 {
1329 compatible = "simple-bus";
1330 reg = <0x8000 0x4000>;
1331
1332 #address-cells = <0x2>;
1333 #size-cells = <0x1>;
1334
1335 ranges = <0 0x0 0x8000 0x1000
1336 1 0x100 0x9000 0x1000
1337 2 0x200 0xA000 0x1000
1338 3 0x300 0xB000 0x1000
1339 >;
1340
Fabien Dessenne641067f2019-05-31 15:11:30 +02001341 dma-ranges = <0 0x000 0x10000000 0x1000
1342 1 0x100 0x20000000 0x1000
1343 >;
1344
Mario Sixe8d52912018-03-12 14:53:33 +01001345 dev@0,0 {
1346 compatible = "denx,u-boot-fdt-dummy";
1347 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001348 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001349 };
1350
1351 dev@1,100 {
1352 compatible = "denx,u-boot-fdt-dummy";
1353 reg = <1 0x100 0x1000>;
1354
1355 };
1356
1357 dev@2,200 {
1358 compatible = "denx,u-boot-fdt-dummy";
1359 reg = <2 0x200 0x1000>;
1360 };
1361
1362
1363 noxlatebus@3,300 {
1364 compatible = "simple-bus";
1365 reg = <3 0x300 0x1000>;
1366
1367 #address-cells = <0x1>;
1368 #size-cells = <0x0>;
1369
1370 dev@42 {
1371 compatible = "denx,u-boot-fdt-dummy";
1372 reg = <0x42>;
1373 };
1374 };
1375 };
Mario Six4eea5312018-09-27 09:19:31 +02001376
1377 osd {
1378 compatible = "sandbox,sandbox_osd";
1379 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001380
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001381 sandbox_tee {
1382 compatible = "sandbox,tee";
1383 };
Bin Meng4f89d492018-10-15 02:21:26 -07001384
1385 sandbox_virtio1 {
1386 compatible = "sandbox,virtio1";
1387 };
1388
1389 sandbox_virtio2 {
1390 compatible = "sandbox,virtio2";
1391 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001392
Etienne Carriere87d4f272020-09-09 18:44:05 +02001393 sandbox_scmi {
1394 compatible = "sandbox,scmi-devices";
1395 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carrierec0dd1772020-09-09 18:44:07 +02001396 resets = <&reset_scmi0 3>;
Etienne Carriere01242182021-03-08 22:38:07 +01001397 regul0-supply = <&regul0_scmi0>;
1398 regul1-supply = <&regul1_scmi0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001399 };
1400
Patrice Chotardf41a8242018-10-24 14:10:23 +02001401 pinctrl {
1402 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001403
Sean Anderson7f0f1802020-09-14 11:01:57 -04001404 pinctrl-names = "default", "alternate";
1405 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1406 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001407
Sean Anderson7f0f1802020-09-14 11:01:57 -04001408 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001409 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001410 pins = "P5";
1411 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001412 bias-pull-up;
1413 input-disable;
1414 };
1415 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001416 pins = "P6";
1417 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001418 output-high;
1419 drive-open-drain;
1420 };
1421 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001422 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001423 bias-pull-down;
1424 input-enable;
1425 };
1426 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001427 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001428 bias-disable;
1429 };
1430 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001431
1432 pinctrl_i2c: i2c {
1433 groups {
1434 groups = "I2C_UART";
1435 function = "I2C";
1436 };
1437
1438 pins {
1439 pins = "P0", "P1";
1440 drive-open-drain;
1441 };
1442 };
1443
1444 pinctrl_i2s: i2s {
1445 groups = "SPI_I2S";
1446 function = "I2S";
1447 };
1448
1449 pinctrl_spi: spi {
1450 groups = "SPI_I2S";
1451 function = "SPI";
1452
1453 cs {
1454 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1455 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1456 };
1457 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001458 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001459
Dario Binacchi55322622021-04-11 09:39:50 +02001460 pinctrl-single-no-width {
1461 compatible = "pinctrl-single";
1462 reg = <0x0000 0x238>;
1463 #pinctrl-cells = <1>;
1464 pinctrl-single,function-mask = <0x7f>;
1465 };
1466
1467 pinctrl-single-pins {
1468 compatible = "pinctrl-single";
1469 reg = <0x0000 0x238>;
1470 #pinctrl-cells = <1>;
1471 pinctrl-single,register-width = <32>;
1472 pinctrl-single,function-mask = <0x7f>;
1473
1474 pinmux_pwm_pins: pinmux_pwm_pins {
1475 pinctrl-single,pins = < 0x48 0x06 >;
1476 };
1477
1478 pinmux_spi0_pins: pinmux_spi0_pins {
1479 pinctrl-single,pins = <
1480 0x190 0x0c
1481 0x194 0x0c
1482 0x198 0x23
1483 0x19c 0x0c
1484 >;
1485 };
1486
1487 pinmux_uart0_pins: pinmux_uart0_pins {
1488 pinctrl-single,pins = <
1489 0x70 0x30
1490 0x74 0x00
1491 >;
1492 };
1493 };
1494
1495 pinctrl-single-bits {
1496 compatible = "pinctrl-single";
1497 reg = <0x0000 0x50>;
1498 #pinctrl-cells = <2>;
1499 pinctrl-single,bit-per-mux;
1500 pinctrl-single,register-width = <32>;
1501 pinctrl-single,function-mask = <0xf>;
1502
1503 pinmux_i2c0_pins: pinmux_i2c0_pins {
1504 pinctrl-single,bits = <
1505 0x10 0x00002200 0x0000ff00
1506 >;
1507 };
1508
1509 pinmux_lcd_pins: pinmux_lcd_pins {
1510 pinctrl-single,bits = <
1511 0x40 0x22222200 0xffffff00
1512 0x44 0x22222222 0xffffffff
1513 0x48 0x00000022 0x000000ff
1514 0x48 0x02000000 0x0f000000
1515 0x4c 0x02000022 0x0f0000ff
1516 >;
1517 };
1518 };
1519
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001520 hwspinlock@0 {
1521 compatible = "sandbox,hwspinlock";
1522 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001523
1524 dma: dma {
1525 compatible = "sandbox,dma";
1526 #dma-cells = <1>;
1527
1528 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1529 dma-names = "m2m", "tx0", "rx0";
1530 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001531
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001532 /*
1533 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1534 * end of the test. If parent mdio is removed first, clean-up of the
1535 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1536 * active at the end of the test. That it turn doesn't allow the mdio
1537 * class to be destroyed, triggering an error.
1538 */
1539 mdio-mux-test {
1540 compatible = "sandbox,mdio-mux";
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543 mdio-parent-bus = <&mdio>;
1544
1545 mdio-ch-test@0 {
1546 reg = <0>;
1547 };
1548 mdio-ch-test@1 {
1549 reg = <1>;
1550 };
1551 };
1552
1553 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001554 compatible = "sandbox,mdio";
1555 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001556
1557 pm-bus-test {
1558 compatible = "simple-pm-bus";
1559 clocks = <&clk_sandbox 4>;
1560 power-domains = <&pwrdom 1>;
1561 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001562
1563 resetc2: syscon-reset {
1564 compatible = "syscon-reset";
1565 #reset-cells = <1>;
1566 regmap = <&syscon0>;
1567 offset = <1>;
1568 mask = <0x27FFFFFF>;
1569 assert-high = <0>;
1570 };
1571
1572 syscon-reset-test {
1573 compatible = "sandbox,misc_sandbox";
1574 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1575 reset-names = "valid", "no_mask", "out_of_range";
1576 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301577
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001578 sysinfo {
1579 compatible = "sandbox,sysinfo-sandbox";
1580 };
1581
Sean Anderson1cbfed82021-04-20 10:50:58 -04001582 sysinfo-gpio {
1583 compatible = "gpio-sysinfo";
1584 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1585 revisions = <19>, <5>;
1586 names = "rev_a", "foo";
1587 };
1588
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301589 some_regmapped-bus {
1590 #address-cells = <0x1>;
1591 #size-cells = <0x1>;
1592
1593 ranges = <0x0 0x0 0x10>;
1594 compatible = "simple-bus";
1595
1596 regmap-test_0 {
1597 reg = <0 0x10>;
1598 compatible = "sandbox,regmap_test";
1599 };
1600 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001601};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001602
1603#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001604#include "cros-ec-keyboard.dtsi"