blob: 05c1cd5e1a553228ac54a80d113e05267933bfe1 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060062 };
63
Philippe Reynes059df562022-03-28 22:56:53 +020064 binman {
65 };
66
Rasmus Villemoes8c728422021-04-21 11:06:55 +020067 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060068 testing-bool;
69 testing-int = <123>;
70 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020071 environment {
72 from_fdt = "yes";
73 fdt_env_path = "";
74 };
75 };
76
Nandor Hanf9db2f12021-06-10 16:56:44 +030077 reboot-mode0 {
78 compatible = "reboot-mode-gpio";
79 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
80 u-boot,env-variable = "bootstatus";
81 mode-test = <0x01>;
82 mode-download = <0x03>;
83 };
84
Nandor Hanc74675b2021-06-10 16:56:45 +030085 reboot_mode1: reboot-mode@14 {
86 compatible = "reboot-mode-rtc";
87 rtc = <&rtc_0>;
88 reg = <0x30 4>;
89 u-boot,env-variable = "bootstatus";
90 big-endian;
91 mode-test = <0x21969147>;
92 mode-download = <0x51939147>;
93 };
94
Simon Glassce6d99a2018-12-10 10:37:33 -070095 audio: audio-codec {
96 compatible = "sandbox,audio-codec";
97 #sound-dai-cells = <1>;
98 };
99
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200100 buttons {
101 compatible = "gpio-keys";
102
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200103 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200104 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200105 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200106 };
107
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200108 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200109 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200110 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200111 };
112 };
113
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100114 buttons2 {
115 compatible = "adc-keys";
116 io-channels = <&adc 3>;
117 keyup-threshold-microvolt = <3000000>;
118
119 button-up {
120 label = "button3";
121 linux,code = <KEY_F3>;
122 press-threshold-microvolt = <1500000>;
123 };
124
125 button-down {
126 label = "button4";
127 linux,code = <KEY_F4>;
128 press-threshold-microvolt = <1000000>;
129 };
130
131 button-enter {
132 label = "button5";
133 linux,code = <KEY_F5>;
134 press-threshold-microvolt = <500000>;
135 };
136 };
137
Simon Glasse96fa6c2018-12-10 10:37:34 -0700138 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600139 reg = <0 0>;
140 compatible = "google,cros-ec-sandbox";
141
142 /*
143 * This describes the flash memory within the EC. Note
144 * that the STM32L flash erases to 0, not 0xff.
145 */
146 flash {
147 image-pos = <0x08000000>;
148 size = <0x20000>;
149 erase-value = <0>;
150
151 /* Information for sandbox */
152 ro {
153 image-pos = <0>;
154 size = <0xf000>;
155 };
156 wp-ro {
157 image-pos = <0xf000>;
158 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700159 used = <0x884>;
160 compress = "lz4";
161 uncomp-size = <0xcf8>;
162 hash {
163 algo = "sha256";
164 value = [00 01 02 03 04 05 06 07
165 08 09 0a 0b 0c 0d 0e 0f
166 10 11 12 13 14 15 16 17
167 18 19 1a 1b 1c 1d 1e 1f];
168 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600169 };
170 rw {
171 image-pos = <0x10000>;
172 size = <0x10000>;
173 };
174 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300175
176 cros_ec_pwm: cros-ec-pwm {
177 compatible = "google,cros-ec-pwm";
178 #pwm-cells = <1>;
179 };
180
Simon Glasse6c5c942018-10-01 12:22:08 -0600181 };
182
Yannick Fertré23f965a2019-10-07 15:29:05 +0200183 dsi_host: dsi_host {
184 compatible = "sandbox,dsi-host";
185 };
186
Simon Glass2e7d35d2014-02-26 15:59:21 -0700187 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600188 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700189 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600190 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700191 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600192 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100193 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
194 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700195 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100196 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
197 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
198 <&gpio_b 7 GPIO_IN 3 2 1>,
199 <&gpio_b 8 GPIO_OUT 3 2 1>,
200 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100201 test3-gpios =
202 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
203 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
204 <&gpio_c 2 GPIO_OUT>,
205 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
206 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200207 <&gpio_c 5 GPIO_IN>,
208 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
209 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530210 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
211 test5-gpios = <&gpio_a 19>;
212
Simon Glassfb933d02021-10-23 17:26:04 -0600213 bool-value;
Simon Glassa1b17e42018-12-10 10:37:37 -0700214 int-value = <1234>;
215 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200216 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200217 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600218 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700219 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600220 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200221 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530222
223 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
224 <&muxcontroller0 2>, <&muxcontroller0 3>,
225 <&muxcontroller1>;
226 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
227 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100228 display-timings {
229 timing0: 240x320 {
230 clock-frequency = <6500000>;
231 hactive = <240>;
232 vactive = <320>;
233 hfront-porch = <6>;
234 hback-porch = <7>;
235 hsync-len = <1>;
236 vback-porch = <5>;
237 vfront-porch = <8>;
238 vsync-len = <2>;
239 hsync-active = <1>;
240 vsync-active = <0>;
241 de-active = <1>;
242 pixelclk-active = <1>;
243 interlaced;
244 doublescan;
245 doubleclk;
246 };
247 timing1: 480x800 {
248 clock-frequency = <9000000>;
249 hactive = <480>;
250 vactive = <800>;
251 hfront-porch = <10>;
252 hback-porch = <59>;
253 hsync-len = <12>;
254 vback-porch = <15>;
255 vfront-porch = <17>;
256 vsync-len = <16>;
257 hsync-active = <0>;
258 vsync-active = <1>;
259 de-active = <0>;
260 pixelclk-active = <0>;
261 };
262 timing2: 800x480 {
263 clock-frequency = <33500000>;
264 hactive = <800>;
265 vactive = <480>;
266 hback-porch = <89>;
267 hfront-porch = <164>;
268 vback-porch = <23>;
269 vfront-porch = <10>;
270 hsync-len = <11>;
271 vsync-len = <13>;
272 };
273 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700274 };
275
276 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600277 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700278 compatible = "not,compatible";
279 };
280
281 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600282 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700283 };
284
Simon Glass5d9a88f2018-10-01 12:22:40 -0600285 backlight: backlight {
286 compatible = "pwm-backlight";
287 enable-gpios = <&gpio_a 1>;
288 power-supply = <&ldo_1>;
289 pwms = <&pwm 0 1000>;
290 default-brightness-level = <5>;
291 brightness-levels = <0 16 32 64 128 170 202 234 255>;
292 };
293
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200294 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200295 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200296 bind-test-child1 {
297 compatible = "sandbox,phy";
298 #phy-cells = <1>;
299 };
300
301 bind-test-child2 {
302 compatible = "simple-bus";
303 };
304 };
305
Simon Glass2e7d35d2014-02-26 15:59:21 -0700306 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600307 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700308 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600309 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700310 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530311
312 mux-controls = <&muxcontroller0 0>;
313 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700314 };
315
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200316 phy_provider0: gen_phy@0 {
317 compatible = "sandbox,phy";
318 #phy-cells = <1>;
319 };
320
321 phy_provider1: gen_phy@1 {
322 compatible = "sandbox,phy";
323 #phy-cells = <0>;
324 broken;
325 };
326
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200327 phy_provider2: gen_phy@2 {
328 compatible = "sandbox,phy";
329 #phy-cells = <0>;
330 };
331
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200332 gen_phy_user: gen_phy_user {
333 compatible = "simple-bus";
334 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
335 phy-names = "phy1", "phy2", "phy3";
336 };
337
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200338 gen_phy_user1: gen_phy_user1 {
339 compatible = "simple-bus";
340 phys = <&phy_provider0 0>, <&phy_provider2>;
341 phy-names = "phy1", "phy2";
342 };
343
Simon Glass2e7d35d2014-02-26 15:59:21 -0700344 some-bus {
345 #address-cells = <1>;
346 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600347 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600348 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600349 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700350 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600351 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700352 compatible = "denx,u-boot-fdt-test";
353 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600354 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700355 ping-add = <5>;
356 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600357 c-test@0 {
358 compatible = "denx,u-boot-fdt-test";
359 reg = <0>;
360 ping-expect = <6>;
361 ping-add = <6>;
362 };
363 c-test@1 {
364 compatible = "denx,u-boot-fdt-test";
365 reg = <1>;
366 ping-expect = <7>;
367 ping-add = <7>;
368 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700369 };
370
371 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600372 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600373 ping-expect = <6>;
374 ping-add = <6>;
375 compatible = "google,another-fdt-test";
376 };
377
378 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600379 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600380 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700381 ping-add = <6>;
382 compatible = "google,another-fdt-test";
383 };
384
Simon Glass9cc36a22015-01-25 08:27:05 -0700385 f-test {
386 compatible = "denx,u-boot-fdt-test";
387 };
388
389 g-test {
390 compatible = "denx,u-boot-fdt-test";
391 };
392
Bin Meng2786cd72018-10-10 22:07:01 -0700393 h-test {
394 compatible = "denx,u-boot-fdt-test1";
395 };
396
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200397 i-test {
398 compatible = "mediatek,u-boot-fdt-test";
399 #address-cells = <1>;
400 #size-cells = <0>;
401
402 subnode@0 {
403 reg = <0>;
404 };
405
406 subnode@1 {
407 reg = <1>;
408 };
409
410 subnode@2 {
411 reg = <2>;
412 };
413 };
414
Simon Glassdc12ebb2019-12-29 21:19:25 -0700415 devres-test {
416 compatible = "denx,u-boot-devres-test";
417 };
418
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530419 another-test {
420 reg = <0 2>;
421 compatible = "denx,u-boot-fdt-test";
422 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
423 test5-gpios = <&gpio_a 19>;
424 };
425
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100426 mmio-bus@0 {
427 #address-cells = <1>;
428 #size-cells = <1>;
429 compatible = "denx,u-boot-test-bus";
430 dma-ranges = <0x10000000 0x00000000 0x00040000>;
431
432 subnode@0 {
433 compatible = "denx,u-boot-fdt-test";
434 };
435 };
436
437 mmio-bus@1 {
438 #address-cells = <1>;
439 #size-cells = <1>;
440 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100441
442 subnode@0 {
443 compatible = "denx,u-boot-fdt-test";
444 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100445 };
446
Simon Glass0f7b1112020-07-07 13:12:06 -0600447 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600448 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600449 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600450 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600451 child {
452 compatible = "denx,u-boot-acpi-test";
453 };
Simon Glassf50cc952020-04-08 16:57:34 -0600454 };
455
Simon Glass0f7b1112020-07-07 13:12:06 -0600456 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600457 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600458 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600459 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600460 };
461
Patrice Chotardee87a092017-09-04 14:55:57 +0200462 clocks {
463 clk_fixed: clk-fixed {
464 compatible = "fixed-clock";
465 #clock-cells = <0>;
466 clock-frequency = <1234>;
467 };
Anup Patelb630d572019-02-25 08:14:55 +0000468
469 clk_fixed_factor: clk-fixed-factor {
470 compatible = "fixed-factor-clock";
471 #clock-cells = <0>;
472 clock-div = <3>;
473 clock-mult = <2>;
474 clocks = <&clk_fixed>;
475 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200476
477 osc {
478 compatible = "fixed-clock";
479 #clock-cells = <0>;
480 clock-frequency = <20000000>;
481 };
Stephen Warren135aa952016-06-17 09:44:00 -0600482 };
483
484 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600485 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600486 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200487 assigned-clocks = <&clk_sandbox 3>;
488 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600489 };
490
491 clk-test {
492 compatible = "sandbox,clk-test";
493 clocks = <&clk_fixed>,
494 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200495 <&clk_sandbox 0>,
496 <&clk_sandbox 3>,
497 <&clk_sandbox 2>;
498 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600499 };
500
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200501 ccf: clk-ccf {
502 compatible = "sandbox,clk-ccf";
503 };
504
Simon Glass42b7f422021-12-04 08:56:31 -0700505 efi-media {
506 compatible = "sandbox,efi-media";
507 };
508
Simon Glass171e9912015-05-22 15:42:15 -0600509 eth@10002000 {
510 compatible = "sandbox,eth";
511 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500512 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600513 };
514
515 eth_5: eth@10003000 {
516 compatible = "sandbox,eth";
517 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500518 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600519 };
520
Bin Meng71d79712015-08-27 22:25:53 -0700521 eth_3: sbe5 {
522 compatible = "sandbox,eth";
523 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500524 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700525 };
526
Simon Glass171e9912015-05-22 15:42:15 -0600527 eth@10004000 {
528 compatible = "sandbox,eth";
529 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500530 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600531 };
532
Claudiu Manoilff98da02021-03-14 20:14:57 +0800533 dsa_eth0: dsa-test-eth {
534 compatible = "sandbox,eth";
535 reg = <0x10006000 0x1000>;
536 fake-host-hwaddr = [00 00 66 44 22 66];
537 };
538
539 dsa-test {
540 compatible = "sandbox,dsa";
541
542 ports {
543 #address-cells = <1>;
544 #size-cells = <0>;
545 swp_0: port@0 {
546 reg = <0>;
547 label = "lan0";
548 phy-mode = "rgmii-rxid";
549
550 fixed-link {
551 speed = <100>;
552 full-duplex;
553 };
554 };
555
556 swp_1: port@1 {
557 reg = <1>;
558 label = "lan1";
559 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800560 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800561 };
562
563 port@2 {
564 reg = <2>;
565 ethernet = <&dsa_eth0>;
566
567 fixed-link {
568 speed = <1000>;
569 full-duplex;
570 };
571 };
572 };
573 };
574
Rajan Vaja31b82172018-09-19 03:43:46 -0700575 firmware {
576 sandbox_firmware: sandbox-firmware {
577 compatible = "sandbox,firmware";
578 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200579
Etienne Carriere41d62e22022-02-21 09:22:39 +0100580 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200581 compatible = "sandbox,scmi-agent";
582 #address-cells = <1>;
583 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200584
Etienne Carriere41d62e22022-02-21 09:22:39 +0100585 protocol@10 {
586 reg = <0x10>;
587 };
588
589 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200590 reg = <0x14>;
591 #clock-cells = <1>;
592 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200593
Etienne Carriere41d62e22022-02-21 09:22:39 +0100594 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200595 reg = <0x16>;
596 #reset-cells = <1>;
597 };
Etienne Carriere01242182021-03-08 22:38:07 +0100598
599 protocol@17 {
600 reg = <0x17>;
601
602 regulators {
603 #address-cells = <1>;
604 #size-cells = <0>;
605
Etienne Carriere41d62e22022-02-21 09:22:39 +0100606 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100607 reg = <0>;
608 regulator-name = "sandbox-voltd0";
609 regulator-min-microvolt = <1100000>;
610 regulator-max-microvolt = <3300000>;
611 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100612 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100613 reg = <0x1>;
614 regulator-name = "sandbox-voltd1";
615 regulator-min-microvolt = <1800000>;
616 };
617 };
618 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200619 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700620 };
621
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100622 pinctrl-gpio {
623 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700624
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100625 gpio_a: base-gpios {
626 compatible = "sandbox,gpio";
627 gpio-controller;
628 #gpio-cells = <1>;
629 gpio-bank-name = "a";
630 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200631 hog_input_active_low {
632 gpio-hog;
633 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200634 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200635 };
636 hog_input_active_high {
637 gpio-hog;
638 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200639 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200640 };
641 hog_output_low {
642 gpio-hog;
643 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200644 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200645 };
646 hog_output_high {
647 gpio-hog;
648 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200649 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200650 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100651 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600652
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100653 gpio_b: extra-gpios {
654 compatible = "sandbox,gpio";
655 gpio-controller;
656 #gpio-cells = <5>;
657 gpio-bank-name = "b";
658 sandbox,gpio-count = <10>;
659 };
660
661 gpio_c: pinmux-gpios {
662 compatible = "sandbox,gpio";
663 gpio-controller;
664 #gpio-cells = <2>;
665 gpio-bank-name = "c";
666 sandbox,gpio-count = <10>;
667 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100668 };
669
Simon Glassecc2ed52014-12-10 08:55:55 -0700670 i2c@0 {
671 #address-cells = <1>;
672 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600673 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700674 compatible = "sandbox,i2c";
675 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200676 pinctrl-names = "default";
677 pinctrl-0 = <&pinmux_i2c0_pins>;
678
Simon Glassecc2ed52014-12-10 08:55:55 -0700679 eeprom@2c {
680 reg = <0x2c>;
681 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700682 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200683 partitions {
684 compatible = "fixed-partitions";
685 #address-cells = <1>;
686 #size-cells = <1>;
687 bootcount_i2c: bootcount@10 {
688 reg = <10 2>;
689 };
690 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700691 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200692
Simon Glass52d3bc52015-05-22 15:42:17 -0600693 rtc_0: rtc@43 {
694 reg = <0x43>;
695 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700696 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600697 };
698
699 rtc_1: rtc@61 {
700 reg = <0x61>;
701 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700702 sandbox,emul = <&emul1>;
703 };
704
705 i2c_emul: emul {
706 reg = <0xff>;
707 compatible = "sandbox,i2c-emul-parent";
708 emul_eeprom: emul-eeprom {
709 compatible = "sandbox,i2c-eeprom";
710 sandbox,filename = "i2c.bin";
711 sandbox,size = <256>;
712 };
713 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700714 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700715 };
716 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700717 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600718 };
719 };
720
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200721 sandbox_pmic: sandbox_pmic {
722 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700723 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200724 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200725
726 mc34708: pmic@41 {
727 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700728 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200729 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700730 };
731
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100732 bootcount@0 {
733 compatible = "u-boot,bootcount-rtc";
734 rtc = <&rtc_1>;
735 offset = <0x13>;
736 };
737
Michal Simekf692b472020-05-28 11:48:55 +0200738 bootcount {
739 compatible = "u-boot,bootcount-i2c-eeprom";
740 i2c-eeprom = <&bootcount_i2c>;
741 };
742
Nandor Hanc50b21b2021-06-10 15:40:38 +0300743 bootcount_4@0 {
744 compatible = "u-boot,bootcount-syscon";
745 syscon = <&syscon0>;
746 reg = <0x0 0x04>, <0x0 0x04>;
747 reg-names = "syscon_reg", "offset";
748 };
749
750 bootcount_2@0 {
751 compatible = "u-boot,bootcount-syscon";
752 syscon = <&syscon0>;
753 reg = <0x0 0x04>, <0x0 0x02> ;
754 reg-names = "syscon_reg", "offset";
755 };
756
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100757 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100758 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100759 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100760 vdd-supply = <&buck2>;
761 vss-microvolts = <0>;
762 };
763
Mark Kettenisfb574622021-10-23 16:58:02 +0200764 iommu: iommu@0 {
765 compatible = "sandbox,iommu";
766 #iommu-cells = <0>;
767 };
768
Simon Glass02554352020-02-06 09:55:00 -0700769 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700770 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700771 interrupt-controller;
772 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700773 };
774
Simon Glass3c97c4f2016-01-18 19:52:26 -0700775 lcd {
776 u-boot,dm-pre-reloc;
777 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200778 pinctrl-names = "default";
779 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700780 xres = <1366>;
781 yres = <768>;
782 };
783
Simon Glass3c43fba2015-07-06 12:54:34 -0600784 leds {
785 compatible = "gpio-leds";
786
787 iracibble {
788 gpios = <&gpio_a 1 0>;
789 label = "sandbox:red";
790 };
791
792 martinet {
793 gpios = <&gpio_a 2 0>;
794 label = "sandbox:green";
795 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200796
797 default_on {
798 gpios = <&gpio_a 5 0>;
799 label = "sandbox:default_on";
800 default-state = "on";
801 };
802
803 default_off {
804 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400805 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200806 default-state = "off";
807 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600808 };
809
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200810 gpio-wdt {
811 gpios = <&gpio_a 7 0>;
812 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200813 hw_margin_ms = <100>;
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200814 always-running;
815 };
816
Stephen Warren8961b522016-05-16 17:41:37 -0600817 mbox: mbox {
818 compatible = "sandbox,mbox";
819 #mbox-cells = <1>;
820 };
821
822 mbox-test {
823 compatible = "sandbox,mbox-test";
824 mboxes = <&mbox 100>, <&mbox 1>;
825 mbox-names = "other", "test";
826 };
827
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900828 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200829 #address-cells = <1>;
830 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400831 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200832 cpu1: cpu@1 {
833 device_type = "cpu";
834 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400835 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900836 compatible = "sandbox,cpu_sandbox";
837 u-boot,dm-pre-reloc;
838 };
Mario Sixfa44b532018-08-06 10:23:44 +0200839
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200840 cpu2: cpu@2 {
841 device_type = "cpu";
842 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900843 compatible = "sandbox,cpu_sandbox";
844 u-boot,dm-pre-reloc;
845 };
Mario Sixfa44b532018-08-06 10:23:44 +0200846
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200847 cpu3: cpu@3 {
848 device_type = "cpu";
849 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900850 compatible = "sandbox,cpu_sandbox";
851 u-boot,dm-pre-reloc;
852 };
Mario Sixfa44b532018-08-06 10:23:44 +0200853 };
854
Dave Gerlach21e3c212020-07-15 23:39:58 -0500855 chipid: chipid {
856 compatible = "sandbox,soc";
857 };
858
Simon Glasse96fa6c2018-12-10 10:37:34 -0700859 i2s: i2s {
860 compatible = "sandbox,i2s";
861 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700862 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700863 };
864
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200865 nop-test_0 {
866 compatible = "sandbox,nop_sandbox1";
867 nop-test_1 {
868 compatible = "sandbox,nop_sandbox2";
869 bind = "True";
870 };
871 nop-test_2 {
872 compatible = "sandbox,nop_sandbox2";
873 bind = "False";
874 };
875 };
876
Mario Six004e67c2018-07-31 14:24:14 +0200877 misc-test {
878 compatible = "sandbox,misc_sandbox";
879 };
880
Simon Glasse48eeb92017-04-23 20:02:07 -0600881 mmc2 {
882 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -0600883 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -0600884 };
885
886 mmc1 {
887 compatible = "sandbox,mmc";
888 };
889
890 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600891 compatible = "sandbox,mmc";
892 };
893
Simon Glassb45c8332019-02-16 20:24:50 -0700894 pch {
895 compatible = "sandbox,pch";
896 };
897
Tom Rini42c64d12020-02-11 12:41:23 -0500898 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700899 compatible = "sandbox,pci";
900 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500901 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700902 #address-cells = <3>;
903 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600904 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700905 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700906 pci@0,0 {
907 compatible = "pci-generic";
908 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600909 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700910 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300911 pci@1,0 {
912 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600913 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
914 reg = <0x02000814 0 0 0 0
915 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600916 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300917 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700918 p2sb-pci@2,0 {
919 compatible = "sandbox,p2sb";
920 reg = <0x02001010 0 0 0 0>;
921 sandbox,emul = <&p2sb_emul>;
922
923 adder {
924 intel,p2sb-port-id = <3>;
925 compatible = "sandbox,adder";
926 };
927 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700928 pci@1e,0 {
929 compatible = "sandbox,pmc";
930 reg = <0xf000 0 0 0 0>;
931 sandbox,emul = <&pmc_emul1e>;
932 acpi-base = <0x400>;
933 gpe0-dwx-mask = <0xf>;
934 gpe0-dwx-shift-base = <4>;
935 gpe0-dw = <6 7 9>;
936 gpe0-sts = <0x20>;
937 gpe0-en = <0x30>;
938 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700939 pci@1f,0 {
940 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600941 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
942 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600943 sandbox,emul = <&swap_case_emul0_1f>;
944 };
945 };
946
947 pci-emul0 {
948 compatible = "sandbox,pci-emul-parent";
949 swap_case_emul0_0: emul0@0,0 {
950 compatible = "sandbox,swap-case";
951 };
952 swap_case_emul0_1: emul0@1,0 {
953 compatible = "sandbox,swap-case";
954 use-ea;
955 };
956 swap_case_emul0_1f: emul0@1f,0 {
957 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700958 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700959 p2sb_emul: emul@2,0 {
960 compatible = "sandbox,p2sb-emul";
961 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700962 pmc_emul1e: emul@1e,0 {
963 compatible = "sandbox,pmc-emul";
964 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700965 };
966
Tom Rini42c64d12020-02-11 12:41:23 -0500967 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700968 compatible = "sandbox,pci";
969 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500970 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700971 #address-cells = <3>;
972 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700973 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
974 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
975 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -0700976 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +0200977 0x0c 0x00 0x1234 0x5678
978 0x10 0x00 0x1234 0x5678>;
979 pci@10,0 {
980 reg = <0x8000 0 0 0 0>;
981 };
Bin Mengdee4d752018-08-03 01:14:41 -0700982 };
983
Tom Rini42c64d12020-02-11 12:41:23 -0500984 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -0700985 compatible = "sandbox,pci";
986 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500987 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -0700988 #address-cells = <3>;
989 #size-cells = <2>;
990 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
991 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
992 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
993 pci@1f,0 {
994 compatible = "pci-generic";
995 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600996 sandbox,emul = <&swap_case_emul2_1f>;
997 };
998 };
999
1000 pci-emul2 {
1001 compatible = "sandbox,pci-emul-parent";
1002 swap_case_emul2_1f: emul2@1f,0 {
1003 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001004 };
1005 };
1006
Ramon Friedbb413332019-04-27 11:15:23 +03001007 pci_ep: pci_ep {
1008 compatible = "sandbox,pci_ep";
1009 };
1010
Simon Glass98561572017-04-23 20:10:44 -06001011 probing {
1012 compatible = "simple-bus";
1013 test1 {
1014 compatible = "denx,u-boot-probe-test";
1015 };
1016
1017 test2 {
1018 compatible = "denx,u-boot-probe-test";
1019 };
1020
1021 test3 {
1022 compatible = "denx,u-boot-probe-test";
1023 };
1024
1025 test4 {
1026 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001027 first-syscon = <&syscon0>;
1028 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001029 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001030 };
1031 };
1032
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001033 pwrdom: power-domain {
1034 compatible = "sandbox,power-domain";
1035 #power-domain-cells = <1>;
1036 };
1037
1038 power-domain-test {
1039 compatible = "sandbox,power-domain-test";
1040 power-domains = <&pwrdom 2>;
1041 };
1042
Simon Glass5d9a88f2018-10-01 12:22:40 -06001043 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001044 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001045 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001046 pinctrl-names = "default";
1047 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001048 };
1049
1050 pwm2 {
1051 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001052 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001053 };
1054
Simon Glass64ce0ca2015-07-06 12:54:31 -06001055 ram {
1056 compatible = "sandbox,ram";
1057 };
1058
Simon Glass5010d982015-07-06 12:54:29 -06001059 reset@0 {
1060 compatible = "sandbox,warm-reset";
1061 };
1062
1063 reset@1 {
1064 compatible = "sandbox,reset";
1065 };
1066
Stephen Warren4581b712016-06-17 09:43:59 -06001067 resetc: reset-ctl {
1068 compatible = "sandbox,reset-ctl";
1069 #reset-cells = <1>;
1070 };
1071
1072 reset-ctl-test {
1073 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001074 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1075 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001076 };
1077
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301078 rng {
1079 compatible = "sandbox,sandbox-rng";
1080 };
1081
Nishanth Menon52159402015-09-17 15:42:41 -05001082 rproc_1: rproc@1 {
1083 compatible = "sandbox,test-processor";
1084 remoteproc-name = "remoteproc-test-dev1";
1085 };
1086
1087 rproc_2: rproc@2 {
1088 compatible = "sandbox,test-processor";
1089 internal-memory-mapped;
1090 remoteproc-name = "remoteproc-test-dev2";
1091 };
1092
Simon Glass5d9a88f2018-10-01 12:22:40 -06001093 panel {
1094 compatible = "simple-panel";
1095 backlight = <&backlight 0 100>;
1096 };
1097
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001098 smem@0 {
1099 compatible = "sandbox,smem";
1100 };
1101
Simon Glassd4901892018-12-10 10:37:36 -07001102 sound {
1103 compatible = "sandbox,sound";
1104 cpu {
1105 sound-dai = <&i2s 0>;
1106 };
1107
1108 codec {
1109 sound-dai = <&audio 0>;
1110 };
1111 };
1112
Simon Glass0ae0cb72014-10-13 23:42:11 -06001113 spi@0 {
1114 #address-cells = <1>;
1115 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001116 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001117 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001118 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001119 pinctrl-names = "default";
1120 pinctrl-0 = <&pinmux_spi0_pins>;
1121
Simon Glass0ae0cb72014-10-13 23:42:11 -06001122 spi.bin@0 {
1123 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001124 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001125 spi-max-frequency = <40000000>;
1126 sandbox,filename = "spi.bin";
1127 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001128 spi.bin@1 {
1129 reg = <1>;
1130 compatible = "spansion,m25p16", "jedec,spi-nor";
1131 spi-max-frequency = <50000000>;
1132 sandbox,filename = "spi.bin";
1133 spi-cpol;
1134 spi-cpha;
1135 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001136 };
1137
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001138 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001139 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001140 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001141 };
1142
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001143 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001144 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001145 reg = <0x20 5
1146 0x28 6
1147 0x30 7
1148 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001149 };
1150
Patrick Delaunaya442e612019-03-07 09:57:13 +01001151 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001152 compatible = "simple-mfd", "syscon";
1153 reg = <0x40 5
1154 0x48 6
1155 0x50 7
1156 0x58 8>;
1157 };
1158
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301159 syscon3: syscon@3 {
1160 compatible = "simple-mfd", "syscon";
1161 reg = <0x000100 0x10>;
1162
1163 muxcontroller0: a-mux-controller {
1164 compatible = "mmio-mux";
1165 #mux-control-cells = <1>;
1166
1167 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1168 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1169 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1170 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1171 u-boot,mux-autoprobe;
1172 };
1173 };
1174
1175 muxcontroller1: emul-mux-controller {
1176 compatible = "mux-emul";
1177 #mux-control-cells = <0>;
1178 u-boot,mux-autoprobe;
1179 idle-state = <0xabcd>;
1180 };
1181
Simon Glass93f44e82020-12-16 21:20:27 -07001182 testfdtm0 {
1183 compatible = "denx,u-boot-fdtm-test";
1184 };
1185
1186 testfdtm1: testfdtm1 {
1187 compatible = "denx,u-boot-fdtm-test";
1188 };
1189
1190 testfdtm2 {
1191 compatible = "denx,u-boot-fdtm-test";
1192 };
1193
Sean Anderson7616e362020-09-28 10:52:23 -04001194 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001195 compatible = "sandbox,timer";
1196 clock-frequency = <1000000>;
1197 };
1198
Sean Anderson7616e362020-09-28 10:52:23 -04001199 timer@1 {
1200 compatible = "sandbox,timer";
1201 sandbox,timebase-frequency-fallback;
1202 };
1203
Miquel Raynalb91ad162018-05-15 11:57:27 +02001204 tpm2 {
1205 compatible = "sandbox,tpm2";
1206 };
1207
Simon Glass171e9912015-05-22 15:42:15 -06001208 uart0: serial {
1209 compatible = "sandbox,serial";
1210 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001211 pinctrl-names = "default";
1212 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001213 };
1214
Simon Glasse00cb222015-03-25 12:23:05 -06001215 usb_0: usb@0 {
1216 compatible = "sandbox,usb";
1217 status = "disabled";
1218 hub {
1219 compatible = "sandbox,usb-hub";
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1222 flash-stick {
1223 reg = <0>;
1224 compatible = "sandbox,usb-flash";
1225 };
1226 };
1227 };
1228
1229 usb_1: usb@1 {
1230 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001231 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001232 hub {
1233 compatible = "usb-hub";
1234 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001235 #address-cells = <1>;
1236 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001237 hub-emul {
1238 compatible = "sandbox,usb-hub";
1239 #address-cells = <1>;
1240 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001241 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001242 reg = <0>;
1243 compatible = "sandbox,usb-flash";
1244 sandbox,filepath = "testflash.bin";
1245 };
1246
Simon Glass431cbd62015-11-08 23:48:01 -07001247 flash-stick@1 {
1248 reg = <1>;
1249 compatible = "sandbox,usb-flash";
1250 sandbox,filepath = "testflash1.bin";
1251 };
1252
1253 flash-stick@2 {
1254 reg = <2>;
1255 compatible = "sandbox,usb-flash";
1256 sandbox,filepath = "testflash2.bin";
1257 };
1258
Simon Glassbff1a712015-11-08 23:48:08 -07001259 keyb@3 {
1260 reg = <3>;
1261 compatible = "sandbox,usb-keyb";
1262 };
1263
Simon Glasse00cb222015-03-25 12:23:05 -06001264 };
Michael Wallec03b7612020-06-02 01:47:07 +02001265
1266 usbstor@1 {
1267 reg = <1>;
1268 };
1269 usbstor@3 {
1270 reg = <3>;
1271 };
Simon Glasse00cb222015-03-25 12:23:05 -06001272 };
1273 };
1274
1275 usb_2: usb@2 {
1276 compatible = "sandbox,usb";
1277 status = "disabled";
1278 };
1279
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001280 spmi: spmi@0 {
1281 compatible = "sandbox,spmi";
1282 #address-cells = <0x1>;
1283 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001284 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001285 pm8916@0 {
1286 compatible = "qcom,spmi-pmic";
1287 reg = <0x0 0x1>;
1288 #address-cells = <0x1>;
1289 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001290 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001291
1292 spmi_gpios: gpios@c000 {
1293 compatible = "qcom,pm8916-gpio";
1294 reg = <0xc000 0x400>;
1295 gpio-controller;
1296 gpio-count = <4>;
1297 #gpio-cells = <2>;
1298 gpio-bank-name="spmi";
1299 };
1300 };
1301 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001302
1303 wdt0: wdt@0 {
1304 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001305 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001306 };
Rob Clarkf2006802018-01-10 11:33:30 +01001307
Mario Six957983e2018-08-09 14:51:19 +02001308 axi: axi@0 {
1309 compatible = "sandbox,axi";
1310 #address-cells = <0x1>;
1311 #size-cells = <0x1>;
1312 store@0 {
1313 compatible = "sandbox,sandbox_store";
1314 reg = <0x0 0x400>;
1315 };
1316 };
1317
Rob Clarkf2006802018-01-10 11:33:30 +01001318 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001319 #address-cells = <1>;
1320 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001321 setting = "sunrise ohoka";
1322 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001323 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001324 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001325 chosen-test {
1326 compatible = "denx,u-boot-fdt-test";
1327 reg = <9 1>;
1328 };
1329 };
Mario Sixe8d52912018-03-12 14:53:33 +01001330
1331 translation-test@8000 {
1332 compatible = "simple-bus";
1333 reg = <0x8000 0x4000>;
1334
1335 #address-cells = <0x2>;
1336 #size-cells = <0x1>;
1337
1338 ranges = <0 0x0 0x8000 0x1000
1339 1 0x100 0x9000 0x1000
1340 2 0x200 0xA000 0x1000
1341 3 0x300 0xB000 0x1000
1342 >;
1343
Fabien Dessenne641067f2019-05-31 15:11:30 +02001344 dma-ranges = <0 0x000 0x10000000 0x1000
1345 1 0x100 0x20000000 0x1000
1346 >;
1347
Mario Sixe8d52912018-03-12 14:53:33 +01001348 dev@0,0 {
1349 compatible = "denx,u-boot-fdt-dummy";
1350 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001351 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001352 };
1353
1354 dev@1,100 {
1355 compatible = "denx,u-boot-fdt-dummy";
1356 reg = <1 0x100 0x1000>;
1357
1358 };
1359
1360 dev@2,200 {
1361 compatible = "denx,u-boot-fdt-dummy";
1362 reg = <2 0x200 0x1000>;
1363 };
1364
1365
1366 noxlatebus@3,300 {
1367 compatible = "simple-bus";
1368 reg = <3 0x300 0x1000>;
1369
1370 #address-cells = <0x1>;
1371 #size-cells = <0x0>;
1372
1373 dev@42 {
1374 compatible = "denx,u-boot-fdt-dummy";
1375 reg = <0x42>;
1376 };
1377 };
1378 };
Mario Six4eea5312018-09-27 09:19:31 +02001379
1380 osd {
1381 compatible = "sandbox,sandbox_osd";
1382 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001383
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001384 sandbox_tee {
1385 compatible = "sandbox,tee";
1386 };
Bin Meng4f89d492018-10-15 02:21:26 -07001387
1388 sandbox_virtio1 {
1389 compatible = "sandbox,virtio1";
1390 };
1391
1392 sandbox_virtio2 {
1393 compatible = "sandbox,virtio2";
1394 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001395
Etienne Carriere87d4f272020-09-09 18:44:05 +02001396 sandbox_scmi {
1397 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001398 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001399 resets = <&reset_scmi 3>;
1400 regul0-supply = <&regul0_scmi>;
1401 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001402 };
1403
Patrice Chotardf41a8242018-10-24 14:10:23 +02001404 pinctrl {
1405 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001406
Sean Anderson7f0f1802020-09-14 11:01:57 -04001407 pinctrl-names = "default", "alternate";
1408 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1409 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001410
Sean Anderson7f0f1802020-09-14 11:01:57 -04001411 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001412 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001413 pins = "P5";
1414 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001415 bias-pull-up;
1416 input-disable;
1417 };
1418 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001419 pins = "P6";
1420 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001421 output-high;
1422 drive-open-drain;
1423 };
1424 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001425 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001426 bias-pull-down;
1427 input-enable;
1428 };
1429 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001430 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001431 bias-disable;
1432 };
1433 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001434
1435 pinctrl_i2c: i2c {
1436 groups {
1437 groups = "I2C_UART";
1438 function = "I2C";
1439 };
1440
1441 pins {
1442 pins = "P0", "P1";
1443 drive-open-drain;
1444 };
1445 };
1446
1447 pinctrl_i2s: i2s {
1448 groups = "SPI_I2S";
1449 function = "I2S";
1450 };
1451
1452 pinctrl_spi: spi {
1453 groups = "SPI_I2S";
1454 function = "SPI";
1455
1456 cs {
1457 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1458 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1459 };
1460 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001461 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001462
Dario Binacchi55322622021-04-11 09:39:50 +02001463 pinctrl-single-no-width {
1464 compatible = "pinctrl-single";
1465 reg = <0x0000 0x238>;
1466 #pinctrl-cells = <1>;
1467 pinctrl-single,function-mask = <0x7f>;
1468 };
1469
1470 pinctrl-single-pins {
1471 compatible = "pinctrl-single";
1472 reg = <0x0000 0x238>;
1473 #pinctrl-cells = <1>;
1474 pinctrl-single,register-width = <32>;
1475 pinctrl-single,function-mask = <0x7f>;
1476
1477 pinmux_pwm_pins: pinmux_pwm_pins {
1478 pinctrl-single,pins = < 0x48 0x06 >;
1479 };
1480
1481 pinmux_spi0_pins: pinmux_spi0_pins {
1482 pinctrl-single,pins = <
1483 0x190 0x0c
1484 0x194 0x0c
1485 0x198 0x23
1486 0x19c 0x0c
1487 >;
1488 };
1489
1490 pinmux_uart0_pins: pinmux_uart0_pins {
1491 pinctrl-single,pins = <
1492 0x70 0x30
1493 0x74 0x00
1494 >;
1495 };
1496 };
1497
1498 pinctrl-single-bits {
1499 compatible = "pinctrl-single";
1500 reg = <0x0000 0x50>;
1501 #pinctrl-cells = <2>;
1502 pinctrl-single,bit-per-mux;
1503 pinctrl-single,register-width = <32>;
1504 pinctrl-single,function-mask = <0xf>;
1505
1506 pinmux_i2c0_pins: pinmux_i2c0_pins {
1507 pinctrl-single,bits = <
1508 0x10 0x00002200 0x0000ff00
1509 >;
1510 };
1511
1512 pinmux_lcd_pins: pinmux_lcd_pins {
1513 pinctrl-single,bits = <
1514 0x40 0x22222200 0xffffff00
1515 0x44 0x22222222 0xffffffff
1516 0x48 0x00000022 0x000000ff
1517 0x48 0x02000000 0x0f000000
1518 0x4c 0x02000022 0x0f0000ff
1519 >;
1520 };
1521 };
1522
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001523 hwspinlock@0 {
1524 compatible = "sandbox,hwspinlock";
1525 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001526
1527 dma: dma {
1528 compatible = "sandbox,dma";
1529 #dma-cells = <1>;
1530
1531 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1532 dma-names = "m2m", "tx0", "rx0";
1533 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001534
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001535 /*
1536 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1537 * end of the test. If parent mdio is removed first, clean-up of the
1538 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1539 * active at the end of the test. That it turn doesn't allow the mdio
1540 * class to be destroyed, triggering an error.
1541 */
1542 mdio-mux-test {
1543 compatible = "sandbox,mdio-mux";
1544 #address-cells = <1>;
1545 #size-cells = <0>;
1546 mdio-parent-bus = <&mdio>;
1547
1548 mdio-ch-test@0 {
1549 reg = <0>;
1550 };
1551 mdio-ch-test@1 {
1552 reg = <1>;
1553 };
1554 };
1555
1556 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001557 compatible = "sandbox,mdio";
1558 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001559
1560 pm-bus-test {
1561 compatible = "simple-pm-bus";
1562 clocks = <&clk_sandbox 4>;
1563 power-domains = <&pwrdom 1>;
1564 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001565
1566 resetc2: syscon-reset {
1567 compatible = "syscon-reset";
1568 #reset-cells = <1>;
1569 regmap = <&syscon0>;
1570 offset = <1>;
1571 mask = <0x27FFFFFF>;
1572 assert-high = <0>;
1573 };
1574
1575 syscon-reset-test {
1576 compatible = "sandbox,misc_sandbox";
1577 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1578 reset-names = "valid", "no_mask", "out_of_range";
1579 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301580
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001581 sysinfo {
1582 compatible = "sandbox,sysinfo-sandbox";
1583 };
1584
Sean Anderson1cbfed82021-04-20 10:50:58 -04001585 sysinfo-gpio {
1586 compatible = "gpio-sysinfo";
1587 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1588 revisions = <19>, <5>;
1589 names = "rev_a", "foo";
1590 };
1591
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301592 some_regmapped-bus {
1593 #address-cells = <0x1>;
1594 #size-cells = <0x1>;
1595
1596 ranges = <0x0 0x0 0x10>;
1597 compatible = "simple-bus";
1598
1599 regmap-test_0 {
1600 reg = <0 0x10>;
1601 compatible = "sandbox,regmap_test";
1602 };
1603 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001604};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001605
1606#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001607#include "cros-ec-keyboard.dtsi"