blob: 39d57f51102199f16ef8dfea712ecbddaf043b62 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070040 pci0 = &pci0;
41 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070042 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020043 remoteproc0 = &rproc_1;
44 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060045 rtc0 = &rtc_0;
46 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060047 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020048 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070049 testbus3 = "/some-bus";
50 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070051 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070052 testfdt3 = "/b-test";
53 testfdt5 = "/some-bus/c-test@5";
54 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070055 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020056 fdt-dummy0 = "/translation-test@8000/dev@0,0";
57 fdt-dummy1 = "/translation-test@8000/dev@1,100";
58 fdt-dummy2 = "/translation-test@8000/dev@2,200";
59 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060060 usb0 = &usb_0;
61 usb1 = &usb_1;
62 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020063 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020064 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060065 };
66
Philippe Reynes059df562022-03-28 22:56:53 +020067 binman {
68 };
69
Rasmus Villemoes8c728422021-04-21 11:06:55 +020070 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060071 testing-bool;
72 testing-int = <123>;
73 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020074 environment {
75 from_fdt = "yes";
76 fdt_env_path = "";
77 };
78 };
79
Simon Glassfb1451b2022-04-24 23:31:24 -060080 bootstd {
81 compatible = "u-boot,boot-std";
82
83 filename-prefixes = "/", "/boot/";
84 bootdev-order = "mmc2", "mmc1";
85
86 syslinux {
87 compatible = "u-boot,distro-syslinux";
88 };
89
90 efi {
91 compatible = "u-boot,distro-efi";
92 };
93 };
94
Nandor Hanf9db2f12021-06-10 16:56:44 +030095 reboot-mode0 {
96 compatible = "reboot-mode-gpio";
97 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
98 u-boot,env-variable = "bootstatus";
99 mode-test = <0x01>;
100 mode-download = <0x03>;
101 };
102
Nandor Hanc74675b2021-06-10 16:56:45 +0300103 reboot_mode1: reboot-mode@14 {
104 compatible = "reboot-mode-rtc";
105 rtc = <&rtc_0>;
106 reg = <0x30 4>;
107 u-boot,env-variable = "bootstatus";
108 big-endian;
109 mode-test = <0x21969147>;
110 mode-download = <0x51939147>;
111 };
112
Simon Glassce6d99a2018-12-10 10:37:33 -0700113 audio: audio-codec {
114 compatible = "sandbox,audio-codec";
115 #sound-dai-cells = <1>;
116 };
117
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200118 buttons {
119 compatible = "gpio-keys";
120
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200121 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200122 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200123 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200124 };
125
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200126 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200127 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200128 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200129 };
130 };
131
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100132 buttons2 {
133 compatible = "adc-keys";
134 io-channels = <&adc 3>;
135 keyup-threshold-microvolt = <3000000>;
136
137 button-up {
138 label = "button3";
139 linux,code = <KEY_F3>;
140 press-threshold-microvolt = <1500000>;
141 };
142
143 button-down {
144 label = "button4";
145 linux,code = <KEY_F4>;
146 press-threshold-microvolt = <1000000>;
147 };
148
149 button-enter {
150 label = "button5";
151 linux,code = <KEY_F5>;
152 press-threshold-microvolt = <500000>;
153 };
154 };
155
Simon Glasse96fa6c2018-12-10 10:37:34 -0700156 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600157 reg = <0 0>;
158 compatible = "google,cros-ec-sandbox";
159
160 /*
161 * This describes the flash memory within the EC. Note
162 * that the STM32L flash erases to 0, not 0xff.
163 */
164 flash {
165 image-pos = <0x08000000>;
166 size = <0x20000>;
167 erase-value = <0>;
168
169 /* Information for sandbox */
170 ro {
171 image-pos = <0>;
172 size = <0xf000>;
173 };
174 wp-ro {
175 image-pos = <0xf000>;
176 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700177 used = <0x884>;
178 compress = "lz4";
179 uncomp-size = <0xcf8>;
180 hash {
181 algo = "sha256";
182 value = [00 01 02 03 04 05 06 07
183 08 09 0a 0b 0c 0d 0e 0f
184 10 11 12 13 14 15 16 17
185 18 19 1a 1b 1c 1d 1e 1f];
186 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600187 };
188 rw {
189 image-pos = <0x10000>;
190 size = <0x10000>;
191 };
192 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300193
194 cros_ec_pwm: cros-ec-pwm {
195 compatible = "google,cros-ec-pwm";
196 #pwm-cells = <1>;
197 };
198
Simon Glasse6c5c942018-10-01 12:22:08 -0600199 };
200
Yannick Fertré23f965a2019-10-07 15:29:05 +0200201 dsi_host: dsi_host {
202 compatible = "sandbox,dsi-host";
203 };
204
Simon Glass2e7d35d2014-02-26 15:59:21 -0700205 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600206 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700207 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600208 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700209 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600210 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100211 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
212 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700213 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100214 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
215 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
216 <&gpio_b 7 GPIO_IN 3 2 1>,
217 <&gpio_b 8 GPIO_OUT 3 2 1>,
218 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100219 test3-gpios =
220 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
221 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
222 <&gpio_c 2 GPIO_OUT>,
223 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
224 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200225 <&gpio_c 5 GPIO_IN>,
226 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
227 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530228 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
229 test5-gpios = <&gpio_a 19>;
230
Simon Glassfb933d02021-10-23 17:26:04 -0600231 bool-value;
Simon Glassa1b17e42018-12-10 10:37:37 -0700232 int-value = <1234>;
233 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200234 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200235 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600236 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700237 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600238 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200239 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530240
241 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
242 <&muxcontroller0 2>, <&muxcontroller0 3>,
243 <&muxcontroller1>;
244 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
245 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100246 display-timings {
247 timing0: 240x320 {
248 clock-frequency = <6500000>;
249 hactive = <240>;
250 vactive = <320>;
251 hfront-porch = <6>;
252 hback-porch = <7>;
253 hsync-len = <1>;
254 vback-porch = <5>;
255 vfront-porch = <8>;
256 vsync-len = <2>;
257 hsync-active = <1>;
258 vsync-active = <0>;
259 de-active = <1>;
260 pixelclk-active = <1>;
261 interlaced;
262 doublescan;
263 doubleclk;
264 };
265 timing1: 480x800 {
266 clock-frequency = <9000000>;
267 hactive = <480>;
268 vactive = <800>;
269 hfront-porch = <10>;
270 hback-porch = <59>;
271 hsync-len = <12>;
272 vback-porch = <15>;
273 vfront-porch = <17>;
274 vsync-len = <16>;
275 hsync-active = <0>;
276 vsync-active = <1>;
277 de-active = <0>;
278 pixelclk-active = <0>;
279 };
280 timing2: 800x480 {
281 clock-frequency = <33500000>;
282 hactive = <800>;
283 vactive = <480>;
284 hback-porch = <89>;
285 hfront-porch = <164>;
286 vback-porch = <23>;
287 vfront-porch = <10>;
288 hsync-len = <11>;
289 vsync-len = <13>;
290 };
291 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700292 };
293
294 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600295 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700296 compatible = "not,compatible";
297 };
298
299 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600300 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700301 };
302
Simon Glass5d9a88f2018-10-01 12:22:40 -0600303 backlight: backlight {
304 compatible = "pwm-backlight";
305 enable-gpios = <&gpio_a 1>;
306 power-supply = <&ldo_1>;
307 pwms = <&pwm 0 1000>;
308 default-brightness-level = <5>;
309 brightness-levels = <0 16 32 64 128 170 202 234 255>;
310 };
311
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200312 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200313 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200314 bind-test-child1 {
315 compatible = "sandbox,phy";
316 #phy-cells = <1>;
317 };
318
319 bind-test-child2 {
320 compatible = "simple-bus";
321 };
322 };
323
Simon Glass2e7d35d2014-02-26 15:59:21 -0700324 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600325 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700326 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600327 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700328 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530329
330 mux-controls = <&muxcontroller0 0>;
331 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700332 };
333
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200334 phy_provider0: gen_phy@0 {
335 compatible = "sandbox,phy";
336 #phy-cells = <1>;
337 };
338
339 phy_provider1: gen_phy@1 {
340 compatible = "sandbox,phy";
341 #phy-cells = <0>;
342 broken;
343 };
344
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200345 phy_provider2: gen_phy@2 {
346 compatible = "sandbox,phy";
347 #phy-cells = <0>;
348 };
349
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200350 gen_phy_user: gen_phy_user {
351 compatible = "simple-bus";
352 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
353 phy-names = "phy1", "phy2", "phy3";
354 };
355
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200356 gen_phy_user1: gen_phy_user1 {
357 compatible = "simple-bus";
358 phys = <&phy_provider0 0>, <&phy_provider2>;
359 phy-names = "phy1", "phy2";
360 };
361
Simon Glass2e7d35d2014-02-26 15:59:21 -0700362 some-bus {
363 #address-cells = <1>;
364 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600365 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600366 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600367 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700368 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600369 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700370 compatible = "denx,u-boot-fdt-test";
371 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600372 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700373 ping-add = <5>;
374 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600375 c-test@0 {
376 compatible = "denx,u-boot-fdt-test";
377 reg = <0>;
378 ping-expect = <6>;
379 ping-add = <6>;
380 };
381 c-test@1 {
382 compatible = "denx,u-boot-fdt-test";
383 reg = <1>;
384 ping-expect = <7>;
385 ping-add = <7>;
386 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700387 };
388
389 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600390 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600391 ping-expect = <6>;
392 ping-add = <6>;
393 compatible = "google,another-fdt-test";
394 };
395
396 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600397 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600398 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700399 ping-add = <6>;
400 compatible = "google,another-fdt-test";
401 };
402
Simon Glass9cc36a22015-01-25 08:27:05 -0700403 f-test {
404 compatible = "denx,u-boot-fdt-test";
405 };
406
407 g-test {
408 compatible = "denx,u-boot-fdt-test";
409 };
410
Bin Meng2786cd72018-10-10 22:07:01 -0700411 h-test {
412 compatible = "denx,u-boot-fdt-test1";
413 };
414
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200415 i-test {
416 compatible = "mediatek,u-boot-fdt-test";
417 #address-cells = <1>;
418 #size-cells = <0>;
419
420 subnode@0 {
421 reg = <0>;
422 };
423
424 subnode@1 {
425 reg = <1>;
426 };
427
428 subnode@2 {
429 reg = <2>;
430 };
431 };
432
Simon Glassdc12ebb2019-12-29 21:19:25 -0700433 devres-test {
434 compatible = "denx,u-boot-devres-test";
435 };
436
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530437 another-test {
438 reg = <0 2>;
439 compatible = "denx,u-boot-fdt-test";
440 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
441 test5-gpios = <&gpio_a 19>;
442 };
443
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100444 mmio-bus@0 {
445 #address-cells = <1>;
446 #size-cells = <1>;
447 compatible = "denx,u-boot-test-bus";
448 dma-ranges = <0x10000000 0x00000000 0x00040000>;
449
450 subnode@0 {
451 compatible = "denx,u-boot-fdt-test";
452 };
453 };
454
455 mmio-bus@1 {
456 #address-cells = <1>;
457 #size-cells = <1>;
458 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100459
460 subnode@0 {
461 compatible = "denx,u-boot-fdt-test";
462 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100463 };
464
Simon Glass0f7b1112020-07-07 13:12:06 -0600465 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600466 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600467 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600468 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600469 child {
470 compatible = "denx,u-boot-acpi-test";
471 };
Simon Glassf50cc952020-04-08 16:57:34 -0600472 };
473
Simon Glass0f7b1112020-07-07 13:12:06 -0600474 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600475 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600476 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600477 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600478 };
479
Patrice Chotardee87a092017-09-04 14:55:57 +0200480 clocks {
481 clk_fixed: clk-fixed {
482 compatible = "fixed-clock";
483 #clock-cells = <0>;
484 clock-frequency = <1234>;
485 };
Anup Patelb630d572019-02-25 08:14:55 +0000486
487 clk_fixed_factor: clk-fixed-factor {
488 compatible = "fixed-factor-clock";
489 #clock-cells = <0>;
490 clock-div = <3>;
491 clock-mult = <2>;
492 clocks = <&clk_fixed>;
493 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200494
495 osc {
496 compatible = "fixed-clock";
497 #clock-cells = <0>;
498 clock-frequency = <20000000>;
499 };
Stephen Warren135aa952016-06-17 09:44:00 -0600500 };
501
502 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600503 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600504 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200505 assigned-clocks = <&clk_sandbox 3>;
506 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600507 };
508
509 clk-test {
510 compatible = "sandbox,clk-test";
511 clocks = <&clk_fixed>,
512 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200513 <&clk_sandbox 0>,
514 <&clk_sandbox 3>,
515 <&clk_sandbox 2>;
516 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600517 };
518
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200519 ccf: clk-ccf {
520 compatible = "sandbox,clk-ccf";
521 };
522
Simon Glass42b7f422021-12-04 08:56:31 -0700523 efi-media {
524 compatible = "sandbox,efi-media";
525 };
526
Simon Glass171e9912015-05-22 15:42:15 -0600527 eth@10002000 {
528 compatible = "sandbox,eth";
529 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500530 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600531 };
532
533 eth_5: eth@10003000 {
534 compatible = "sandbox,eth";
535 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500536 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600537 };
538
Bin Meng71d79712015-08-27 22:25:53 -0700539 eth_3: sbe5 {
540 compatible = "sandbox,eth";
541 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500542 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700543 };
544
Simon Glass171e9912015-05-22 15:42:15 -0600545 eth@10004000 {
546 compatible = "sandbox,eth";
547 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500548 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600549 };
550
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200551 phy_eth0: phy-test-eth {
552 compatible = "sandbox,eth";
553 reg = <0x10007000 0x1000>;
554 fake-host-hwaddr = [00 00 66 44 22 77];
555 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200556 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200557 };
558
Claudiu Manoilff98da02021-03-14 20:14:57 +0800559 dsa_eth0: dsa-test-eth {
560 compatible = "sandbox,eth";
561 reg = <0x10006000 0x1000>;
562 fake-host-hwaddr = [00 00 66 44 22 66];
563 };
564
565 dsa-test {
566 compatible = "sandbox,dsa";
567
568 ports {
569 #address-cells = <1>;
570 #size-cells = <0>;
571 swp_0: port@0 {
572 reg = <0>;
573 label = "lan0";
574 phy-mode = "rgmii-rxid";
575
576 fixed-link {
577 speed = <100>;
578 full-duplex;
579 };
580 };
581
582 swp_1: port@1 {
583 reg = <1>;
584 label = "lan1";
585 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800586 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800587 };
588
589 port@2 {
590 reg = <2>;
591 ethernet = <&dsa_eth0>;
592
593 fixed-link {
594 speed = <1000>;
595 full-duplex;
596 };
597 };
598 };
599 };
600
Rajan Vaja31b82172018-09-19 03:43:46 -0700601 firmware {
602 sandbox_firmware: sandbox-firmware {
603 compatible = "sandbox,firmware";
604 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200605
Etienne Carriere41d62e22022-02-21 09:22:39 +0100606 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200607 compatible = "sandbox,scmi-agent";
608 #address-cells = <1>;
609 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200610
Etienne Carriere41d62e22022-02-21 09:22:39 +0100611 protocol@10 {
612 reg = <0x10>;
613 };
614
615 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200616 reg = <0x14>;
617 #clock-cells = <1>;
618 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200619
Etienne Carriere41d62e22022-02-21 09:22:39 +0100620 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200621 reg = <0x16>;
622 #reset-cells = <1>;
623 };
Etienne Carriere01242182021-03-08 22:38:07 +0100624
625 protocol@17 {
626 reg = <0x17>;
627
628 regulators {
629 #address-cells = <1>;
630 #size-cells = <0>;
631
Etienne Carriere41d62e22022-02-21 09:22:39 +0100632 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100633 reg = <0>;
634 regulator-name = "sandbox-voltd0";
635 regulator-min-microvolt = <1100000>;
636 regulator-max-microvolt = <3300000>;
637 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100638 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100639 reg = <0x1>;
640 regulator-name = "sandbox-voltd1";
641 regulator-min-microvolt = <1800000>;
642 };
643 };
644 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200645 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700646 };
647
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100648 pinctrl-gpio {
649 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700650
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100651 gpio_a: base-gpios {
652 compatible = "sandbox,gpio";
653 gpio-controller;
654 #gpio-cells = <1>;
655 gpio-bank-name = "a";
656 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200657 hog_input_active_low {
658 gpio-hog;
659 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200660 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200661 };
662 hog_input_active_high {
663 gpio-hog;
664 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200665 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200666 };
667 hog_output_low {
668 gpio-hog;
669 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200670 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200671 };
672 hog_output_high {
673 gpio-hog;
674 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200675 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200676 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100677 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600678
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100679 gpio_b: extra-gpios {
680 compatible = "sandbox,gpio";
681 gpio-controller;
682 #gpio-cells = <5>;
683 gpio-bank-name = "b";
684 sandbox,gpio-count = <10>;
685 };
686
687 gpio_c: pinmux-gpios {
688 compatible = "sandbox,gpio";
689 gpio-controller;
690 #gpio-cells = <2>;
691 gpio-bank-name = "c";
692 sandbox,gpio-count = <10>;
693 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100694 };
695
Simon Glassecc2ed52014-12-10 08:55:55 -0700696 i2c@0 {
697 #address-cells = <1>;
698 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600699 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700700 compatible = "sandbox,i2c";
701 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200702 pinctrl-names = "default";
703 pinctrl-0 = <&pinmux_i2c0_pins>;
704
Simon Glassecc2ed52014-12-10 08:55:55 -0700705 eeprom@2c {
706 reg = <0x2c>;
707 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700708 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200709 partitions {
710 compatible = "fixed-partitions";
711 #address-cells = <1>;
712 #size-cells = <1>;
713 bootcount_i2c: bootcount@10 {
714 reg = <10 2>;
715 };
716 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700717 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200718
Simon Glass52d3bc52015-05-22 15:42:17 -0600719 rtc_0: rtc@43 {
720 reg = <0x43>;
721 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700722 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600723 };
724
725 rtc_1: rtc@61 {
726 reg = <0x61>;
727 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700728 sandbox,emul = <&emul1>;
729 };
730
731 i2c_emul: emul {
732 reg = <0xff>;
733 compatible = "sandbox,i2c-emul-parent";
734 emul_eeprom: emul-eeprom {
735 compatible = "sandbox,i2c-eeprom";
736 sandbox,filename = "i2c.bin";
737 sandbox,size = <256>;
738 };
739 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700740 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700741 };
742 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700743 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600744 };
745 };
746
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200747 sandbox_pmic: sandbox_pmic {
748 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700749 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200750 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200751
752 mc34708: pmic@41 {
753 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700754 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200755 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700756 };
757
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100758 bootcount@0 {
759 compatible = "u-boot,bootcount-rtc";
760 rtc = <&rtc_1>;
761 offset = <0x13>;
762 };
763
Michal Simekf692b472020-05-28 11:48:55 +0200764 bootcount {
765 compatible = "u-boot,bootcount-i2c-eeprom";
766 i2c-eeprom = <&bootcount_i2c>;
767 };
768
Nandor Hanc50b21b2021-06-10 15:40:38 +0300769 bootcount_4@0 {
770 compatible = "u-boot,bootcount-syscon";
771 syscon = <&syscon0>;
772 reg = <0x0 0x04>, <0x0 0x04>;
773 reg-names = "syscon_reg", "offset";
774 };
775
776 bootcount_2@0 {
777 compatible = "u-boot,bootcount-syscon";
778 syscon = <&syscon0>;
779 reg = <0x0 0x04>, <0x0 0x02> ;
780 reg-names = "syscon_reg", "offset";
781 };
782
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100783 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100784 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100785 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100786 vdd-supply = <&buck2>;
787 vss-microvolts = <0>;
788 };
789
Mark Kettenisfb574622021-10-23 16:58:02 +0200790 iommu: iommu@0 {
791 compatible = "sandbox,iommu";
792 #iommu-cells = <0>;
793 };
794
Simon Glass02554352020-02-06 09:55:00 -0700795 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700796 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700797 interrupt-controller;
798 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700799 };
800
Simon Glass3c97c4f2016-01-18 19:52:26 -0700801 lcd {
802 u-boot,dm-pre-reloc;
803 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200804 pinctrl-names = "default";
805 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700806 xres = <1366>;
807 yres = <768>;
808 };
809
Simon Glass3c43fba2015-07-06 12:54:34 -0600810 leds {
811 compatible = "gpio-leds";
812
813 iracibble {
814 gpios = <&gpio_a 1 0>;
815 label = "sandbox:red";
816 };
817
818 martinet {
819 gpios = <&gpio_a 2 0>;
820 label = "sandbox:green";
821 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200822
823 default_on {
824 gpios = <&gpio_a 5 0>;
825 label = "sandbox:default_on";
826 default-state = "on";
827 };
828
829 default_off {
830 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400831 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200832 default-state = "off";
833 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600834 };
835
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200836 gpio-wdt {
837 gpios = <&gpio_a 7 0>;
838 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200839 hw_margin_ms = <100>;
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200840 always-running;
841 };
842
Stephen Warren8961b522016-05-16 17:41:37 -0600843 mbox: mbox {
844 compatible = "sandbox,mbox";
845 #mbox-cells = <1>;
846 };
847
848 mbox-test {
849 compatible = "sandbox,mbox-test";
850 mboxes = <&mbox 100>, <&mbox 1>;
851 mbox-names = "other", "test";
852 };
853
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900854 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200855 #address-cells = <1>;
856 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400857 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200858 cpu1: cpu@1 {
859 device_type = "cpu";
860 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400861 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900862 compatible = "sandbox,cpu_sandbox";
863 u-boot,dm-pre-reloc;
864 };
Mario Sixfa44b532018-08-06 10:23:44 +0200865
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200866 cpu2: cpu@2 {
867 device_type = "cpu";
868 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900869 compatible = "sandbox,cpu_sandbox";
870 u-boot,dm-pre-reloc;
871 };
Mario Sixfa44b532018-08-06 10:23:44 +0200872
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200873 cpu3: cpu@3 {
874 device_type = "cpu";
875 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900876 compatible = "sandbox,cpu_sandbox";
877 u-boot,dm-pre-reloc;
878 };
Mario Sixfa44b532018-08-06 10:23:44 +0200879 };
880
Dave Gerlach21e3c212020-07-15 23:39:58 -0500881 chipid: chipid {
882 compatible = "sandbox,soc";
883 };
884
Simon Glasse96fa6c2018-12-10 10:37:34 -0700885 i2s: i2s {
886 compatible = "sandbox,i2s";
887 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700888 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700889 };
890
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200891 nop-test_0 {
892 compatible = "sandbox,nop_sandbox1";
893 nop-test_1 {
894 compatible = "sandbox,nop_sandbox2";
895 bind = "True";
896 };
897 nop-test_2 {
898 compatible = "sandbox,nop_sandbox2";
899 bind = "False";
900 };
901 };
902
Mario Six004e67c2018-07-31 14:24:14 +0200903 misc-test {
904 compatible = "sandbox,misc_sandbox";
905 };
906
Simon Glasse48eeb92017-04-23 20:02:07 -0600907 mmc2 {
908 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -0600909 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -0600910 };
911
Simon Glassfb1451b2022-04-24 23:31:24 -0600912 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -0600913 mmc1 {
914 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -0600915 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -0600916 };
917
Simon Glassfb1451b2022-04-24 23:31:24 -0600918 /* This is used for the fastboot tests */
Simon Glasse48eeb92017-04-23 20:02:07 -0600919 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600920 compatible = "sandbox,mmc";
921 };
922
Simon Glassb45c8332019-02-16 20:24:50 -0700923 pch {
924 compatible = "sandbox,pch";
925 };
926
Tom Rini42c64d12020-02-11 12:41:23 -0500927 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700928 compatible = "sandbox,pci";
929 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500930 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700931 #address-cells = <3>;
932 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600933 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700934 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700935 pci@0,0 {
936 compatible = "pci-generic";
937 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600938 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700939 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300940 pci@1,0 {
941 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600942 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
943 reg = <0x02000814 0 0 0 0
944 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600945 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300946 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700947 p2sb-pci@2,0 {
948 compatible = "sandbox,p2sb";
949 reg = <0x02001010 0 0 0 0>;
950 sandbox,emul = <&p2sb_emul>;
951
952 adder {
953 intel,p2sb-port-id = <3>;
954 compatible = "sandbox,adder";
955 };
956 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700957 pci@1e,0 {
958 compatible = "sandbox,pmc";
959 reg = <0xf000 0 0 0 0>;
960 sandbox,emul = <&pmc_emul1e>;
961 acpi-base = <0x400>;
962 gpe0-dwx-mask = <0xf>;
963 gpe0-dwx-shift-base = <4>;
964 gpe0-dw = <6 7 9>;
965 gpe0-sts = <0x20>;
966 gpe0-en = <0x30>;
967 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700968 pci@1f,0 {
969 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600970 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
971 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600972 sandbox,emul = <&swap_case_emul0_1f>;
973 };
974 };
975
976 pci-emul0 {
977 compatible = "sandbox,pci-emul-parent";
978 swap_case_emul0_0: emul0@0,0 {
979 compatible = "sandbox,swap-case";
980 };
981 swap_case_emul0_1: emul0@1,0 {
982 compatible = "sandbox,swap-case";
983 use-ea;
984 };
985 swap_case_emul0_1f: emul0@1f,0 {
986 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700987 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700988 p2sb_emul: emul@2,0 {
989 compatible = "sandbox,p2sb-emul";
990 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700991 pmc_emul1e: emul@1e,0 {
992 compatible = "sandbox,pmc-emul";
993 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700994 };
995
Tom Rini42c64d12020-02-11 12:41:23 -0500996 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700997 compatible = "sandbox,pci";
998 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500999 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001000 #address-cells = <3>;
1001 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001002 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001003 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001004 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001005 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001006 0x0c 0x00 0x1234 0x5678
1007 0x10 0x00 0x1234 0x5678>;
1008 pci@10,0 {
1009 reg = <0x8000 0 0 0 0>;
1010 };
Bin Mengdee4d752018-08-03 01:14:41 -07001011 };
1012
Tom Rini42c64d12020-02-11 12:41:23 -05001013 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001014 compatible = "sandbox,pci";
1015 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001016 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001017 #address-cells = <3>;
1018 #size-cells = <2>;
1019 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1020 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1021 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1022 pci@1f,0 {
1023 compatible = "pci-generic";
1024 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001025 sandbox,emul = <&swap_case_emul2_1f>;
1026 };
1027 };
1028
1029 pci-emul2 {
1030 compatible = "sandbox,pci-emul-parent";
1031 swap_case_emul2_1f: emul2@1f,0 {
1032 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001033 };
1034 };
1035
Ramon Friedbb413332019-04-27 11:15:23 +03001036 pci_ep: pci_ep {
1037 compatible = "sandbox,pci_ep";
1038 };
1039
Simon Glass98561572017-04-23 20:10:44 -06001040 probing {
1041 compatible = "simple-bus";
1042 test1 {
1043 compatible = "denx,u-boot-probe-test";
1044 };
1045
1046 test2 {
1047 compatible = "denx,u-boot-probe-test";
1048 };
1049
1050 test3 {
1051 compatible = "denx,u-boot-probe-test";
1052 };
1053
1054 test4 {
1055 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001056 first-syscon = <&syscon0>;
1057 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001058 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001059 };
1060 };
1061
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001062 pwrdom: power-domain {
1063 compatible = "sandbox,power-domain";
1064 #power-domain-cells = <1>;
1065 };
1066
1067 power-domain-test {
1068 compatible = "sandbox,power-domain-test";
1069 power-domains = <&pwrdom 2>;
1070 };
1071
Simon Glass5d9a88f2018-10-01 12:22:40 -06001072 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001073 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001074 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001075 pinctrl-names = "default";
1076 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001077 };
1078
1079 pwm2 {
1080 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001081 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001082 };
1083
Simon Glass64ce0ca2015-07-06 12:54:31 -06001084 ram {
1085 compatible = "sandbox,ram";
1086 };
1087
Simon Glass5010d982015-07-06 12:54:29 -06001088 reset@0 {
1089 compatible = "sandbox,warm-reset";
1090 };
1091
1092 reset@1 {
1093 compatible = "sandbox,reset";
1094 };
1095
Stephen Warren4581b712016-06-17 09:43:59 -06001096 resetc: reset-ctl {
1097 compatible = "sandbox,reset-ctl";
1098 #reset-cells = <1>;
1099 };
1100
1101 reset-ctl-test {
1102 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001103 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1104 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001105 };
1106
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301107 rng {
1108 compatible = "sandbox,sandbox-rng";
1109 };
1110
Nishanth Menon52159402015-09-17 15:42:41 -05001111 rproc_1: rproc@1 {
1112 compatible = "sandbox,test-processor";
1113 remoteproc-name = "remoteproc-test-dev1";
1114 };
1115
1116 rproc_2: rproc@2 {
1117 compatible = "sandbox,test-processor";
1118 internal-memory-mapped;
1119 remoteproc-name = "remoteproc-test-dev2";
1120 };
1121
Simon Glass5d9a88f2018-10-01 12:22:40 -06001122 panel {
1123 compatible = "simple-panel";
1124 backlight = <&backlight 0 100>;
1125 };
1126
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001127 smem@0 {
1128 compatible = "sandbox,smem";
1129 };
1130
Simon Glassd4901892018-12-10 10:37:36 -07001131 sound {
1132 compatible = "sandbox,sound";
1133 cpu {
1134 sound-dai = <&i2s 0>;
1135 };
1136
1137 codec {
1138 sound-dai = <&audio 0>;
1139 };
1140 };
1141
Simon Glass0ae0cb72014-10-13 23:42:11 -06001142 spi@0 {
1143 #address-cells = <1>;
1144 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001145 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001146 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001147 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001148 pinctrl-names = "default";
1149 pinctrl-0 = <&pinmux_spi0_pins>;
1150
Simon Glass0ae0cb72014-10-13 23:42:11 -06001151 spi.bin@0 {
1152 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001153 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001154 spi-max-frequency = <40000000>;
1155 sandbox,filename = "spi.bin";
1156 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001157 spi.bin@1 {
1158 reg = <1>;
1159 compatible = "spansion,m25p16", "jedec,spi-nor";
1160 spi-max-frequency = <50000000>;
1161 sandbox,filename = "spi.bin";
1162 spi-cpol;
1163 spi-cpha;
1164 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001165 };
1166
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001167 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001168 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001169 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001170 };
1171
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001172 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001173 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001174 reg = <0x20 5
1175 0x28 6
1176 0x30 7
1177 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001178 };
1179
Patrick Delaunaya442e612019-03-07 09:57:13 +01001180 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001181 compatible = "simple-mfd", "syscon";
1182 reg = <0x40 5
1183 0x48 6
1184 0x50 7
1185 0x58 8>;
1186 };
1187
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301188 syscon3: syscon@3 {
1189 compatible = "simple-mfd", "syscon";
1190 reg = <0x000100 0x10>;
1191
1192 muxcontroller0: a-mux-controller {
1193 compatible = "mmio-mux";
1194 #mux-control-cells = <1>;
1195
1196 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1197 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1198 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1199 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1200 u-boot,mux-autoprobe;
1201 };
1202 };
1203
1204 muxcontroller1: emul-mux-controller {
1205 compatible = "mux-emul";
1206 #mux-control-cells = <0>;
1207 u-boot,mux-autoprobe;
1208 idle-state = <0xabcd>;
1209 };
1210
Simon Glass93f44e82020-12-16 21:20:27 -07001211 testfdtm0 {
1212 compatible = "denx,u-boot-fdtm-test";
1213 };
1214
1215 testfdtm1: testfdtm1 {
1216 compatible = "denx,u-boot-fdtm-test";
1217 };
1218
1219 testfdtm2 {
1220 compatible = "denx,u-boot-fdtm-test";
1221 };
1222
Sean Anderson7616e362020-09-28 10:52:23 -04001223 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001224 compatible = "sandbox,timer";
1225 clock-frequency = <1000000>;
1226 };
1227
Sean Anderson7616e362020-09-28 10:52:23 -04001228 timer@1 {
1229 compatible = "sandbox,timer";
1230 sandbox,timebase-frequency-fallback;
1231 };
1232
Miquel Raynalb91ad162018-05-15 11:57:27 +02001233 tpm2 {
1234 compatible = "sandbox,tpm2";
1235 };
1236
Simon Glass171e9912015-05-22 15:42:15 -06001237 uart0: serial {
1238 compatible = "sandbox,serial";
1239 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001240 pinctrl-names = "default";
1241 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001242 };
1243
Simon Glasse00cb222015-03-25 12:23:05 -06001244 usb_0: usb@0 {
1245 compatible = "sandbox,usb";
1246 status = "disabled";
1247 hub {
1248 compatible = "sandbox,usb-hub";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 flash-stick {
1252 reg = <0>;
1253 compatible = "sandbox,usb-flash";
1254 };
1255 };
1256 };
1257
1258 usb_1: usb@1 {
1259 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001260 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001261 hub {
1262 compatible = "usb-hub";
1263 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001264 #address-cells = <1>;
1265 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001266 hub-emul {
1267 compatible = "sandbox,usb-hub";
1268 #address-cells = <1>;
1269 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001270 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001271 reg = <0>;
1272 compatible = "sandbox,usb-flash";
1273 sandbox,filepath = "testflash.bin";
1274 };
1275
Simon Glass431cbd62015-11-08 23:48:01 -07001276 flash-stick@1 {
1277 reg = <1>;
1278 compatible = "sandbox,usb-flash";
1279 sandbox,filepath = "testflash1.bin";
1280 };
1281
1282 flash-stick@2 {
1283 reg = <2>;
1284 compatible = "sandbox,usb-flash";
1285 sandbox,filepath = "testflash2.bin";
1286 };
1287
Simon Glassbff1a712015-11-08 23:48:08 -07001288 keyb@3 {
1289 reg = <3>;
1290 compatible = "sandbox,usb-keyb";
1291 };
1292
Simon Glasse00cb222015-03-25 12:23:05 -06001293 };
Michael Wallec03b7612020-06-02 01:47:07 +02001294
1295 usbstor@1 {
1296 reg = <1>;
1297 };
1298 usbstor@3 {
1299 reg = <3>;
1300 };
Simon Glasse00cb222015-03-25 12:23:05 -06001301 };
1302 };
1303
1304 usb_2: usb@2 {
1305 compatible = "sandbox,usb";
1306 status = "disabled";
1307 };
1308
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001309 spmi: spmi@0 {
1310 compatible = "sandbox,spmi";
1311 #address-cells = <0x1>;
1312 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001313 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001314 pm8916@0 {
1315 compatible = "qcom,spmi-pmic";
1316 reg = <0x0 0x1>;
1317 #address-cells = <0x1>;
1318 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001319 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001320
1321 spmi_gpios: gpios@c000 {
1322 compatible = "qcom,pm8916-gpio";
1323 reg = <0xc000 0x400>;
1324 gpio-controller;
1325 gpio-count = <4>;
1326 #gpio-cells = <2>;
1327 gpio-bank-name="spmi";
1328 };
1329 };
1330 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001331
1332 wdt0: wdt@0 {
1333 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001334 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001335 };
Rob Clarkf2006802018-01-10 11:33:30 +01001336
Mario Six957983e2018-08-09 14:51:19 +02001337 axi: axi@0 {
1338 compatible = "sandbox,axi";
1339 #address-cells = <0x1>;
1340 #size-cells = <0x1>;
1341 store@0 {
1342 compatible = "sandbox,sandbox_store";
1343 reg = <0x0 0x400>;
1344 };
1345 };
1346
Rob Clarkf2006802018-01-10 11:33:30 +01001347 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001348 #address-cells = <1>;
1349 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001350 setting = "sunrise ohoka";
1351 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001352 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001353 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001354 chosen-test {
1355 compatible = "denx,u-boot-fdt-test";
1356 reg = <9 1>;
1357 };
1358 };
Mario Sixe8d52912018-03-12 14:53:33 +01001359
1360 translation-test@8000 {
1361 compatible = "simple-bus";
1362 reg = <0x8000 0x4000>;
1363
1364 #address-cells = <0x2>;
1365 #size-cells = <0x1>;
1366
1367 ranges = <0 0x0 0x8000 0x1000
1368 1 0x100 0x9000 0x1000
1369 2 0x200 0xA000 0x1000
1370 3 0x300 0xB000 0x1000
1371 >;
1372
Fabien Dessenne641067f2019-05-31 15:11:30 +02001373 dma-ranges = <0 0x000 0x10000000 0x1000
1374 1 0x100 0x20000000 0x1000
1375 >;
1376
Mario Sixe8d52912018-03-12 14:53:33 +01001377 dev@0,0 {
1378 compatible = "denx,u-boot-fdt-dummy";
1379 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001380 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001381 };
1382
1383 dev@1,100 {
1384 compatible = "denx,u-boot-fdt-dummy";
1385 reg = <1 0x100 0x1000>;
1386
1387 };
1388
1389 dev@2,200 {
1390 compatible = "denx,u-boot-fdt-dummy";
1391 reg = <2 0x200 0x1000>;
1392 };
1393
1394
1395 noxlatebus@3,300 {
1396 compatible = "simple-bus";
1397 reg = <3 0x300 0x1000>;
1398
1399 #address-cells = <0x1>;
1400 #size-cells = <0x0>;
1401
1402 dev@42 {
1403 compatible = "denx,u-boot-fdt-dummy";
1404 reg = <0x42>;
1405 };
1406 };
1407 };
Mario Six4eea5312018-09-27 09:19:31 +02001408
1409 osd {
1410 compatible = "sandbox,sandbox_osd";
1411 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001412
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001413 sandbox_tee {
1414 compatible = "sandbox,tee";
1415 };
Bin Meng4f89d492018-10-15 02:21:26 -07001416
1417 sandbox_virtio1 {
1418 compatible = "sandbox,virtio1";
1419 };
1420
1421 sandbox_virtio2 {
1422 compatible = "sandbox,virtio2";
1423 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001424
Etienne Carriere87d4f272020-09-09 18:44:05 +02001425 sandbox_scmi {
1426 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001427 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001428 resets = <&reset_scmi 3>;
1429 regul0-supply = <&regul0_scmi>;
1430 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001431 };
1432
Patrice Chotardf41a8242018-10-24 14:10:23 +02001433 pinctrl {
1434 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001435
Sean Anderson7f0f1802020-09-14 11:01:57 -04001436 pinctrl-names = "default", "alternate";
1437 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1438 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001439
Sean Anderson7f0f1802020-09-14 11:01:57 -04001440 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001441 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001442 pins = "P5";
1443 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001444 bias-pull-up;
1445 input-disable;
1446 };
1447 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001448 pins = "P6";
1449 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001450 output-high;
1451 drive-open-drain;
1452 };
1453 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001454 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001455 bias-pull-down;
1456 input-enable;
1457 };
1458 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001459 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001460 bias-disable;
1461 };
1462 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001463
1464 pinctrl_i2c: i2c {
1465 groups {
1466 groups = "I2C_UART";
1467 function = "I2C";
1468 };
1469
1470 pins {
1471 pins = "P0", "P1";
1472 drive-open-drain;
1473 };
1474 };
1475
1476 pinctrl_i2s: i2s {
1477 groups = "SPI_I2S";
1478 function = "I2S";
1479 };
1480
1481 pinctrl_spi: spi {
1482 groups = "SPI_I2S";
1483 function = "SPI";
1484
1485 cs {
1486 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1487 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1488 };
1489 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001490 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001491
Dario Binacchi55322622021-04-11 09:39:50 +02001492 pinctrl-single-no-width {
1493 compatible = "pinctrl-single";
1494 reg = <0x0000 0x238>;
1495 #pinctrl-cells = <1>;
1496 pinctrl-single,function-mask = <0x7f>;
1497 };
1498
1499 pinctrl-single-pins {
1500 compatible = "pinctrl-single";
1501 reg = <0x0000 0x238>;
1502 #pinctrl-cells = <1>;
1503 pinctrl-single,register-width = <32>;
1504 pinctrl-single,function-mask = <0x7f>;
1505
1506 pinmux_pwm_pins: pinmux_pwm_pins {
1507 pinctrl-single,pins = < 0x48 0x06 >;
1508 };
1509
1510 pinmux_spi0_pins: pinmux_spi0_pins {
1511 pinctrl-single,pins = <
1512 0x190 0x0c
1513 0x194 0x0c
1514 0x198 0x23
1515 0x19c 0x0c
1516 >;
1517 };
1518
1519 pinmux_uart0_pins: pinmux_uart0_pins {
1520 pinctrl-single,pins = <
1521 0x70 0x30
1522 0x74 0x00
1523 >;
1524 };
1525 };
1526
1527 pinctrl-single-bits {
1528 compatible = "pinctrl-single";
1529 reg = <0x0000 0x50>;
1530 #pinctrl-cells = <2>;
1531 pinctrl-single,bit-per-mux;
1532 pinctrl-single,register-width = <32>;
1533 pinctrl-single,function-mask = <0xf>;
1534
1535 pinmux_i2c0_pins: pinmux_i2c0_pins {
1536 pinctrl-single,bits = <
1537 0x10 0x00002200 0x0000ff00
1538 >;
1539 };
1540
1541 pinmux_lcd_pins: pinmux_lcd_pins {
1542 pinctrl-single,bits = <
1543 0x40 0x22222200 0xffffff00
1544 0x44 0x22222222 0xffffffff
1545 0x48 0x00000022 0x000000ff
1546 0x48 0x02000000 0x0f000000
1547 0x4c 0x02000022 0x0f0000ff
1548 >;
1549 };
1550 };
1551
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001552 hwspinlock@0 {
1553 compatible = "sandbox,hwspinlock";
1554 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001555
1556 dma: dma {
1557 compatible = "sandbox,dma";
1558 #dma-cells = <1>;
1559
1560 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1561 dma-names = "m2m", "tx0", "rx0";
1562 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001563
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001564 /*
1565 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1566 * end of the test. If parent mdio is removed first, clean-up of the
1567 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1568 * active at the end of the test. That it turn doesn't allow the mdio
1569 * class to be destroyed, triggering an error.
1570 */
1571 mdio-mux-test {
1572 compatible = "sandbox,mdio-mux";
1573 #address-cells = <1>;
1574 #size-cells = <0>;
1575 mdio-parent-bus = <&mdio>;
1576
1577 mdio-ch-test@0 {
1578 reg = <0>;
1579 };
1580 mdio-ch-test@1 {
1581 reg = <1>;
1582 };
1583 };
1584
1585 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001586 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001587 #address-cells = <1>;
1588 #size-cells = <0>;
1589
1590 ethphy1: ethernet-phy@1 {
1591 reg = <1>;
1592 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001593 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001594
1595 pm-bus-test {
1596 compatible = "simple-pm-bus";
1597 clocks = <&clk_sandbox 4>;
1598 power-domains = <&pwrdom 1>;
1599 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001600
1601 resetc2: syscon-reset {
1602 compatible = "syscon-reset";
1603 #reset-cells = <1>;
1604 regmap = <&syscon0>;
1605 offset = <1>;
1606 mask = <0x27FFFFFF>;
1607 assert-high = <0>;
1608 };
1609
1610 syscon-reset-test {
1611 compatible = "sandbox,misc_sandbox";
1612 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1613 reset-names = "valid", "no_mask", "out_of_range";
1614 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301615
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001616 sysinfo {
1617 compatible = "sandbox,sysinfo-sandbox";
1618 };
1619
Sean Anderson1cbfed82021-04-20 10:50:58 -04001620 sysinfo-gpio {
1621 compatible = "gpio-sysinfo";
1622 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1623 revisions = <19>, <5>;
1624 names = "rev_a", "foo";
1625 };
1626
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301627 some_regmapped-bus {
1628 #address-cells = <0x1>;
1629 #size-cells = <0x1>;
1630
1631 ranges = <0x0 0x0 0x10>;
1632 compatible = "simple-bus";
1633
1634 regmap-test_0 {
1635 reg = <0 0x10>;
1636 compatible = "sandbox,regmap_test";
1637 };
1638 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001639};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001640
1641#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001642#include "cros-ec-keyboard.dtsi"