blob: 8f93775ff4a312494c3cb50f801453e46cecdd1b [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5d9a88f2018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060062 };
63
Philippe Reynes059df562022-03-28 22:56:53 +020064 binman {
65 };
66
Rasmus Villemoes8c728422021-04-21 11:06:55 +020067 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060068 testing-bool;
69 testing-int = <123>;
70 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020071 environment {
72 from_fdt = "yes";
73 fdt_env_path = "";
74 };
75 };
76
Simon Glassfb1451b2022-04-24 23:31:24 -060077 bootstd {
78 compatible = "u-boot,boot-std";
79
80 filename-prefixes = "/", "/boot/";
81 bootdev-order = "mmc2", "mmc1";
82
83 syslinux {
84 compatible = "u-boot,distro-syslinux";
85 };
86
87 efi {
88 compatible = "u-boot,distro-efi";
89 };
90 };
91
Nandor Hanf9db2f12021-06-10 16:56:44 +030092 reboot-mode0 {
93 compatible = "reboot-mode-gpio";
94 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
95 u-boot,env-variable = "bootstatus";
96 mode-test = <0x01>;
97 mode-download = <0x03>;
98 };
99
Nandor Hanc74675b2021-06-10 16:56:45 +0300100 reboot_mode1: reboot-mode@14 {
101 compatible = "reboot-mode-rtc";
102 rtc = <&rtc_0>;
103 reg = <0x30 4>;
104 u-boot,env-variable = "bootstatus";
105 big-endian;
106 mode-test = <0x21969147>;
107 mode-download = <0x51939147>;
108 };
109
Simon Glassce6d99a2018-12-10 10:37:33 -0700110 audio: audio-codec {
111 compatible = "sandbox,audio-codec";
112 #sound-dai-cells = <1>;
113 };
114
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200115 buttons {
116 compatible = "gpio-keys";
117
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200118 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200119 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200120 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200121 };
122
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200123 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200124 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200125 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200126 };
127 };
128
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100129 buttons2 {
130 compatible = "adc-keys";
131 io-channels = <&adc 3>;
132 keyup-threshold-microvolt = <3000000>;
133
134 button-up {
135 label = "button3";
136 linux,code = <KEY_F3>;
137 press-threshold-microvolt = <1500000>;
138 };
139
140 button-down {
141 label = "button4";
142 linux,code = <KEY_F4>;
143 press-threshold-microvolt = <1000000>;
144 };
145
146 button-enter {
147 label = "button5";
148 linux,code = <KEY_F5>;
149 press-threshold-microvolt = <500000>;
150 };
151 };
152
Simon Glasse96fa6c2018-12-10 10:37:34 -0700153 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600154 reg = <0 0>;
155 compatible = "google,cros-ec-sandbox";
156
157 /*
158 * This describes the flash memory within the EC. Note
159 * that the STM32L flash erases to 0, not 0xff.
160 */
161 flash {
162 image-pos = <0x08000000>;
163 size = <0x20000>;
164 erase-value = <0>;
165
166 /* Information for sandbox */
167 ro {
168 image-pos = <0>;
169 size = <0xf000>;
170 };
171 wp-ro {
172 image-pos = <0xf000>;
173 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700174 used = <0x884>;
175 compress = "lz4";
176 uncomp-size = <0xcf8>;
177 hash {
178 algo = "sha256";
179 value = [00 01 02 03 04 05 06 07
180 08 09 0a 0b 0c 0d 0e 0f
181 10 11 12 13 14 15 16 17
182 18 19 1a 1b 1c 1d 1e 1f];
183 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600184 };
185 rw {
186 image-pos = <0x10000>;
187 size = <0x10000>;
188 };
189 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300190
191 cros_ec_pwm: cros-ec-pwm {
192 compatible = "google,cros-ec-pwm";
193 #pwm-cells = <1>;
194 };
195
Simon Glasse6c5c942018-10-01 12:22:08 -0600196 };
197
Yannick Fertré23f965a2019-10-07 15:29:05 +0200198 dsi_host: dsi_host {
199 compatible = "sandbox,dsi-host";
200 };
201
Simon Glass2e7d35d2014-02-26 15:59:21 -0700202 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600203 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700204 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600205 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700206 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600207 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100208 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
209 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700210 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100211 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
212 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
213 <&gpio_b 7 GPIO_IN 3 2 1>,
214 <&gpio_b 8 GPIO_OUT 3 2 1>,
215 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100216 test3-gpios =
217 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
218 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
219 <&gpio_c 2 GPIO_OUT>,
220 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
221 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200222 <&gpio_c 5 GPIO_IN>,
223 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
224 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530225 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
226 test5-gpios = <&gpio_a 19>;
227
Simon Glassfb933d02021-10-23 17:26:04 -0600228 bool-value;
Simon Glassa1b17e42018-12-10 10:37:37 -0700229 int-value = <1234>;
230 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200231 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200232 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600233 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700234 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600235 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200236 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530237
238 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
239 <&muxcontroller0 2>, <&muxcontroller0 3>,
240 <&muxcontroller1>;
241 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
242 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100243 display-timings {
244 timing0: 240x320 {
245 clock-frequency = <6500000>;
246 hactive = <240>;
247 vactive = <320>;
248 hfront-porch = <6>;
249 hback-porch = <7>;
250 hsync-len = <1>;
251 vback-porch = <5>;
252 vfront-porch = <8>;
253 vsync-len = <2>;
254 hsync-active = <1>;
255 vsync-active = <0>;
256 de-active = <1>;
257 pixelclk-active = <1>;
258 interlaced;
259 doublescan;
260 doubleclk;
261 };
262 timing1: 480x800 {
263 clock-frequency = <9000000>;
264 hactive = <480>;
265 vactive = <800>;
266 hfront-porch = <10>;
267 hback-porch = <59>;
268 hsync-len = <12>;
269 vback-porch = <15>;
270 vfront-porch = <17>;
271 vsync-len = <16>;
272 hsync-active = <0>;
273 vsync-active = <1>;
274 de-active = <0>;
275 pixelclk-active = <0>;
276 };
277 timing2: 800x480 {
278 clock-frequency = <33500000>;
279 hactive = <800>;
280 vactive = <480>;
281 hback-porch = <89>;
282 hfront-porch = <164>;
283 vback-porch = <23>;
284 vfront-porch = <10>;
285 hsync-len = <11>;
286 vsync-len = <13>;
287 };
288 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700289 };
290
291 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600292 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700293 compatible = "not,compatible";
294 };
295
296 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600297 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700298 };
299
Simon Glass5d9a88f2018-10-01 12:22:40 -0600300 backlight: backlight {
301 compatible = "pwm-backlight";
302 enable-gpios = <&gpio_a 1>;
303 power-supply = <&ldo_1>;
304 pwms = <&pwm 0 1000>;
305 default-brightness-level = <5>;
306 brightness-levels = <0 16 32 64 128 170 202 234 255>;
307 };
308
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200309 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200310 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200311 bind-test-child1 {
312 compatible = "sandbox,phy";
313 #phy-cells = <1>;
314 };
315
316 bind-test-child2 {
317 compatible = "simple-bus";
318 };
319 };
320
Simon Glass2e7d35d2014-02-26 15:59:21 -0700321 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600322 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700323 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600324 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700325 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530326
327 mux-controls = <&muxcontroller0 0>;
328 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700329 };
330
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200331 phy_provider0: gen_phy@0 {
332 compatible = "sandbox,phy";
333 #phy-cells = <1>;
334 };
335
336 phy_provider1: gen_phy@1 {
337 compatible = "sandbox,phy";
338 #phy-cells = <0>;
339 broken;
340 };
341
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200342 phy_provider2: gen_phy@2 {
343 compatible = "sandbox,phy";
344 #phy-cells = <0>;
345 };
346
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200347 gen_phy_user: gen_phy_user {
348 compatible = "simple-bus";
349 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
350 phy-names = "phy1", "phy2", "phy3";
351 };
352
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200353 gen_phy_user1: gen_phy_user1 {
354 compatible = "simple-bus";
355 phys = <&phy_provider0 0>, <&phy_provider2>;
356 phy-names = "phy1", "phy2";
357 };
358
Simon Glass2e7d35d2014-02-26 15:59:21 -0700359 some-bus {
360 #address-cells = <1>;
361 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600362 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600363 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600364 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700365 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600366 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700367 compatible = "denx,u-boot-fdt-test";
368 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600369 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700370 ping-add = <5>;
371 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600372 c-test@0 {
373 compatible = "denx,u-boot-fdt-test";
374 reg = <0>;
375 ping-expect = <6>;
376 ping-add = <6>;
377 };
378 c-test@1 {
379 compatible = "denx,u-boot-fdt-test";
380 reg = <1>;
381 ping-expect = <7>;
382 ping-add = <7>;
383 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700384 };
385
386 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600387 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600388 ping-expect = <6>;
389 ping-add = <6>;
390 compatible = "google,another-fdt-test";
391 };
392
393 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600394 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600395 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700396 ping-add = <6>;
397 compatible = "google,another-fdt-test";
398 };
399
Simon Glass9cc36a22015-01-25 08:27:05 -0700400 f-test {
401 compatible = "denx,u-boot-fdt-test";
402 };
403
404 g-test {
405 compatible = "denx,u-boot-fdt-test";
406 };
407
Bin Meng2786cd72018-10-10 22:07:01 -0700408 h-test {
409 compatible = "denx,u-boot-fdt-test1";
410 };
411
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200412 i-test {
413 compatible = "mediatek,u-boot-fdt-test";
414 #address-cells = <1>;
415 #size-cells = <0>;
416
417 subnode@0 {
418 reg = <0>;
419 };
420
421 subnode@1 {
422 reg = <1>;
423 };
424
425 subnode@2 {
426 reg = <2>;
427 };
428 };
429
Simon Glassdc12ebb2019-12-29 21:19:25 -0700430 devres-test {
431 compatible = "denx,u-boot-devres-test";
432 };
433
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530434 another-test {
435 reg = <0 2>;
436 compatible = "denx,u-boot-fdt-test";
437 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
438 test5-gpios = <&gpio_a 19>;
439 };
440
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100441 mmio-bus@0 {
442 #address-cells = <1>;
443 #size-cells = <1>;
444 compatible = "denx,u-boot-test-bus";
445 dma-ranges = <0x10000000 0x00000000 0x00040000>;
446
447 subnode@0 {
448 compatible = "denx,u-boot-fdt-test";
449 };
450 };
451
452 mmio-bus@1 {
453 #address-cells = <1>;
454 #size-cells = <1>;
455 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100456
457 subnode@0 {
458 compatible = "denx,u-boot-fdt-test";
459 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100460 };
461
Simon Glass0f7b1112020-07-07 13:12:06 -0600462 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600463 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600464 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600465 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600466 child {
467 compatible = "denx,u-boot-acpi-test";
468 };
Simon Glassf50cc952020-04-08 16:57:34 -0600469 };
470
Simon Glass0f7b1112020-07-07 13:12:06 -0600471 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600472 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600473 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600474 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600475 };
476
Patrice Chotardee87a092017-09-04 14:55:57 +0200477 clocks {
478 clk_fixed: clk-fixed {
479 compatible = "fixed-clock";
480 #clock-cells = <0>;
481 clock-frequency = <1234>;
482 };
Anup Patelb630d572019-02-25 08:14:55 +0000483
484 clk_fixed_factor: clk-fixed-factor {
485 compatible = "fixed-factor-clock";
486 #clock-cells = <0>;
487 clock-div = <3>;
488 clock-mult = <2>;
489 clocks = <&clk_fixed>;
490 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200491
492 osc {
493 compatible = "fixed-clock";
494 #clock-cells = <0>;
495 clock-frequency = <20000000>;
496 };
Stephen Warren135aa952016-06-17 09:44:00 -0600497 };
498
499 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600500 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600501 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200502 assigned-clocks = <&clk_sandbox 3>;
503 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600504 };
505
506 clk-test {
507 compatible = "sandbox,clk-test";
508 clocks = <&clk_fixed>,
509 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200510 <&clk_sandbox 0>,
511 <&clk_sandbox 3>,
512 <&clk_sandbox 2>;
513 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600514 };
515
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200516 ccf: clk-ccf {
517 compatible = "sandbox,clk-ccf";
518 };
519
Simon Glass42b7f422021-12-04 08:56:31 -0700520 efi-media {
521 compatible = "sandbox,efi-media";
522 };
523
Simon Glass171e9912015-05-22 15:42:15 -0600524 eth@10002000 {
525 compatible = "sandbox,eth";
526 reg = <0x10002000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500527 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass171e9912015-05-22 15:42:15 -0600528 };
529
530 eth_5: eth@10003000 {
531 compatible = "sandbox,eth";
532 reg = <0x10003000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500533 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass171e9912015-05-22 15:42:15 -0600534 };
535
Bin Meng71d79712015-08-27 22:25:53 -0700536 eth_3: sbe5 {
537 compatible = "sandbox,eth";
538 reg = <0x10005000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500539 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng71d79712015-08-27 22:25:53 -0700540 };
541
Simon Glass171e9912015-05-22 15:42:15 -0600542 eth@10004000 {
543 compatible = "sandbox,eth";
544 reg = <0x10004000 0x1000>;
Joe Hershbergerc6fa51a2018-07-02 14:47:45 -0500545 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass171e9912015-05-22 15:42:15 -0600546 };
547
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200548 phy_eth0: phy-test-eth {
549 compatible = "sandbox,eth";
550 reg = <0x10007000 0x1000>;
551 fake-host-hwaddr = [00 00 66 44 22 77];
552 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200553 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200554 };
555
Claudiu Manoilff98da02021-03-14 20:14:57 +0800556 dsa_eth0: dsa-test-eth {
557 compatible = "sandbox,eth";
558 reg = <0x10006000 0x1000>;
559 fake-host-hwaddr = [00 00 66 44 22 66];
560 };
561
562 dsa-test {
563 compatible = "sandbox,dsa";
564
565 ports {
566 #address-cells = <1>;
567 #size-cells = <0>;
568 swp_0: port@0 {
569 reg = <0>;
570 label = "lan0";
571 phy-mode = "rgmii-rxid";
572
573 fixed-link {
574 speed = <100>;
575 full-duplex;
576 };
577 };
578
579 swp_1: port@1 {
580 reg = <1>;
581 label = "lan1";
582 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800583 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800584 };
585
586 port@2 {
587 reg = <2>;
588 ethernet = <&dsa_eth0>;
589
590 fixed-link {
591 speed = <1000>;
592 full-duplex;
593 };
594 };
595 };
596 };
597
Rajan Vaja31b82172018-09-19 03:43:46 -0700598 firmware {
599 sandbox_firmware: sandbox-firmware {
600 compatible = "sandbox,firmware";
601 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200602
Etienne Carriere41d62e22022-02-21 09:22:39 +0100603 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200604 compatible = "sandbox,scmi-agent";
605 #address-cells = <1>;
606 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200607
Etienne Carriere41d62e22022-02-21 09:22:39 +0100608 protocol@10 {
609 reg = <0x10>;
610 };
611
612 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200613 reg = <0x14>;
614 #clock-cells = <1>;
615 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200616
Etienne Carriere41d62e22022-02-21 09:22:39 +0100617 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200618 reg = <0x16>;
619 #reset-cells = <1>;
620 };
Etienne Carriere01242182021-03-08 22:38:07 +0100621
622 protocol@17 {
623 reg = <0x17>;
624
625 regulators {
626 #address-cells = <1>;
627 #size-cells = <0>;
628
Etienne Carriere41d62e22022-02-21 09:22:39 +0100629 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100630 reg = <0>;
631 regulator-name = "sandbox-voltd0";
632 regulator-min-microvolt = <1100000>;
633 regulator-max-microvolt = <3300000>;
634 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100635 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100636 reg = <0x1>;
637 regulator-name = "sandbox-voltd1";
638 regulator-min-microvolt = <1800000>;
639 };
640 };
641 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200642 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700643 };
644
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100645 pinctrl-gpio {
646 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700647
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100648 gpio_a: base-gpios {
649 compatible = "sandbox,gpio";
650 gpio-controller;
651 #gpio-cells = <1>;
652 gpio-bank-name = "a";
653 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200654 hog_input_active_low {
655 gpio-hog;
656 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200657 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200658 };
659 hog_input_active_high {
660 gpio-hog;
661 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200662 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200663 };
664 hog_output_low {
665 gpio-hog;
666 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200667 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200668 };
669 hog_output_high {
670 gpio-hog;
671 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200672 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200673 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100674 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600675
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100676 gpio_b: extra-gpios {
677 compatible = "sandbox,gpio";
678 gpio-controller;
679 #gpio-cells = <5>;
680 gpio-bank-name = "b";
681 sandbox,gpio-count = <10>;
682 };
683
684 gpio_c: pinmux-gpios {
685 compatible = "sandbox,gpio";
686 gpio-controller;
687 #gpio-cells = <2>;
688 gpio-bank-name = "c";
689 sandbox,gpio-count = <10>;
690 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100691 };
692
Simon Glassecc2ed52014-12-10 08:55:55 -0700693 i2c@0 {
694 #address-cells = <1>;
695 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600696 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700697 compatible = "sandbox,i2c";
698 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200699 pinctrl-names = "default";
700 pinctrl-0 = <&pinmux_i2c0_pins>;
701
Simon Glassecc2ed52014-12-10 08:55:55 -0700702 eeprom@2c {
703 reg = <0x2c>;
704 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700705 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200706 partitions {
707 compatible = "fixed-partitions";
708 #address-cells = <1>;
709 #size-cells = <1>;
710 bootcount_i2c: bootcount@10 {
711 reg = <10 2>;
712 };
713 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700714 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200715
Simon Glass52d3bc52015-05-22 15:42:17 -0600716 rtc_0: rtc@43 {
717 reg = <0x43>;
718 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700719 sandbox,emul = <&emul0>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600720 };
721
722 rtc_1: rtc@61 {
723 reg = <0x61>;
724 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700725 sandbox,emul = <&emul1>;
726 };
727
728 i2c_emul: emul {
729 reg = <0xff>;
730 compatible = "sandbox,i2c-emul-parent";
731 emul_eeprom: emul-eeprom {
732 compatible = "sandbox,i2c-eeprom";
733 sandbox,filename = "i2c.bin";
734 sandbox,size = <256>;
735 };
736 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700737 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700738 };
739 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700740 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600741 };
742 };
743
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200744 sandbox_pmic: sandbox_pmic {
745 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700746 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200747 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200748
749 mc34708: pmic@41 {
750 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700751 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200752 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700753 };
754
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100755 bootcount@0 {
756 compatible = "u-boot,bootcount-rtc";
757 rtc = <&rtc_1>;
758 offset = <0x13>;
759 };
760
Michal Simekf692b472020-05-28 11:48:55 +0200761 bootcount {
762 compatible = "u-boot,bootcount-i2c-eeprom";
763 i2c-eeprom = <&bootcount_i2c>;
764 };
765
Nandor Hanc50b21b2021-06-10 15:40:38 +0300766 bootcount_4@0 {
767 compatible = "u-boot,bootcount-syscon";
768 syscon = <&syscon0>;
769 reg = <0x0 0x04>, <0x0 0x04>;
770 reg-names = "syscon_reg", "offset";
771 };
772
773 bootcount_2@0 {
774 compatible = "u-boot,bootcount-syscon";
775 syscon = <&syscon0>;
776 reg = <0x0 0x04>, <0x0 0x02> ;
777 reg-names = "syscon_reg", "offset";
778 };
779
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100780 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100781 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100782 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100783 vdd-supply = <&buck2>;
784 vss-microvolts = <0>;
785 };
786
Mark Kettenisfb574622021-10-23 16:58:02 +0200787 iommu: iommu@0 {
788 compatible = "sandbox,iommu";
789 #iommu-cells = <0>;
790 };
791
Simon Glass02554352020-02-06 09:55:00 -0700792 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700793 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700794 interrupt-controller;
795 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700796 };
797
Simon Glass3c97c4f2016-01-18 19:52:26 -0700798 lcd {
799 u-boot,dm-pre-reloc;
800 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200801 pinctrl-names = "default";
802 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700803 xres = <1366>;
804 yres = <768>;
805 };
806
Simon Glass3c43fba2015-07-06 12:54:34 -0600807 leds {
808 compatible = "gpio-leds";
809
810 iracibble {
811 gpios = <&gpio_a 1 0>;
812 label = "sandbox:red";
813 };
814
815 martinet {
816 gpios = <&gpio_a 2 0>;
817 label = "sandbox:green";
818 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200819
820 default_on {
821 gpios = <&gpio_a 5 0>;
822 label = "sandbox:default_on";
823 default-state = "on";
824 };
825
826 default_off {
827 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400828 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200829 default-state = "off";
830 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600831 };
832
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200833 gpio-wdt {
834 gpios = <&gpio_a 7 0>;
835 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200836 hw_margin_ms = <100>;
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200837 always-running;
838 };
839
Stephen Warren8961b522016-05-16 17:41:37 -0600840 mbox: mbox {
841 compatible = "sandbox,mbox";
842 #mbox-cells = <1>;
843 };
844
845 mbox-test {
846 compatible = "sandbox,mbox-test";
847 mboxes = <&mbox 100>, <&mbox 1>;
848 mbox-names = "other", "test";
849 };
850
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900851 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200852 #address-cells = <1>;
853 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400854 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200855 cpu1: cpu@1 {
856 device_type = "cpu";
857 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400858 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900859 compatible = "sandbox,cpu_sandbox";
860 u-boot,dm-pre-reloc;
861 };
Mario Sixfa44b532018-08-06 10:23:44 +0200862
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200863 cpu2: cpu@2 {
864 device_type = "cpu";
865 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900866 compatible = "sandbox,cpu_sandbox";
867 u-boot,dm-pre-reloc;
868 };
Mario Sixfa44b532018-08-06 10:23:44 +0200869
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200870 cpu3: cpu@3 {
871 device_type = "cpu";
872 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900873 compatible = "sandbox,cpu_sandbox";
874 u-boot,dm-pre-reloc;
875 };
Mario Sixfa44b532018-08-06 10:23:44 +0200876 };
877
Dave Gerlach21e3c212020-07-15 23:39:58 -0500878 chipid: chipid {
879 compatible = "sandbox,soc";
880 };
881
Simon Glasse96fa6c2018-12-10 10:37:34 -0700882 i2s: i2s {
883 compatible = "sandbox,i2s";
884 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700885 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700886 };
887
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200888 nop-test_0 {
889 compatible = "sandbox,nop_sandbox1";
890 nop-test_1 {
891 compatible = "sandbox,nop_sandbox2";
892 bind = "True";
893 };
894 nop-test_2 {
895 compatible = "sandbox,nop_sandbox2";
896 bind = "False";
897 };
898 };
899
Mario Six004e67c2018-07-31 14:24:14 +0200900 misc-test {
901 compatible = "sandbox,misc_sandbox";
902 };
903
Simon Glasse48eeb92017-04-23 20:02:07 -0600904 mmc2 {
905 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -0600906 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -0600907 };
908
Simon Glassfb1451b2022-04-24 23:31:24 -0600909 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -0600910 mmc1 {
911 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -0600912 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -0600913 };
914
Simon Glassfb1451b2022-04-24 23:31:24 -0600915 /* This is used for the fastboot tests */
Simon Glasse48eeb92017-04-23 20:02:07 -0600916 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600917 compatible = "sandbox,mmc";
918 };
919
Simon Glassb45c8332019-02-16 20:24:50 -0700920 pch {
921 compatible = "sandbox,pch";
922 };
923
Tom Rini42c64d12020-02-11 12:41:23 -0500924 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700925 compatible = "sandbox,pci";
926 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500927 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700928 #address-cells = <3>;
929 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600930 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700931 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700932 pci@0,0 {
933 compatible = "pci-generic";
934 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600935 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700936 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300937 pci@1,0 {
938 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600939 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
940 reg = <0x02000814 0 0 0 0
941 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600942 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300943 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700944 p2sb-pci@2,0 {
945 compatible = "sandbox,p2sb";
946 reg = <0x02001010 0 0 0 0>;
947 sandbox,emul = <&p2sb_emul>;
948
949 adder {
950 intel,p2sb-port-id = <3>;
951 compatible = "sandbox,adder";
952 };
953 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700954 pci@1e,0 {
955 compatible = "sandbox,pmc";
956 reg = <0xf000 0 0 0 0>;
957 sandbox,emul = <&pmc_emul1e>;
958 acpi-base = <0x400>;
959 gpe0-dwx-mask = <0xf>;
960 gpe0-dwx-shift-base = <4>;
961 gpe0-dw = <6 7 9>;
962 gpe0-sts = <0x20>;
963 gpe0-en = <0x30>;
964 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700965 pci@1f,0 {
966 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600967 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
968 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600969 sandbox,emul = <&swap_case_emul0_1f>;
970 };
971 };
972
973 pci-emul0 {
974 compatible = "sandbox,pci-emul-parent";
975 swap_case_emul0_0: emul0@0,0 {
976 compatible = "sandbox,swap-case";
977 };
978 swap_case_emul0_1: emul0@1,0 {
979 compatible = "sandbox,swap-case";
980 use-ea;
981 };
982 swap_case_emul0_1f: emul0@1f,0 {
983 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700984 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700985 p2sb_emul: emul@2,0 {
986 compatible = "sandbox,p2sb-emul";
987 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700988 pmc_emul1e: emul@1e,0 {
989 compatible = "sandbox,pmc-emul";
990 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700991 };
992
Tom Rini42c64d12020-02-11 12:41:23 -0500993 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -0700994 compatible = "sandbox,pci";
995 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500996 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -0700997 #address-cells = <3>;
998 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -0700999 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001000 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001001 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001002 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001003 0x0c 0x00 0x1234 0x5678
1004 0x10 0x00 0x1234 0x5678>;
1005 pci@10,0 {
1006 reg = <0x8000 0 0 0 0>;
1007 };
Bin Mengdee4d752018-08-03 01:14:41 -07001008 };
1009
Tom Rini42c64d12020-02-11 12:41:23 -05001010 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001011 compatible = "sandbox,pci";
1012 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001013 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001014 #address-cells = <3>;
1015 #size-cells = <2>;
1016 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1017 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1018 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1019 pci@1f,0 {
1020 compatible = "pci-generic";
1021 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001022 sandbox,emul = <&swap_case_emul2_1f>;
1023 };
1024 };
1025
1026 pci-emul2 {
1027 compatible = "sandbox,pci-emul-parent";
1028 swap_case_emul2_1f: emul2@1f,0 {
1029 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001030 };
1031 };
1032
Ramon Friedbb413332019-04-27 11:15:23 +03001033 pci_ep: pci_ep {
1034 compatible = "sandbox,pci_ep";
1035 };
1036
Simon Glass98561572017-04-23 20:10:44 -06001037 probing {
1038 compatible = "simple-bus";
1039 test1 {
1040 compatible = "denx,u-boot-probe-test";
1041 };
1042
1043 test2 {
1044 compatible = "denx,u-boot-probe-test";
1045 };
1046
1047 test3 {
1048 compatible = "denx,u-boot-probe-test";
1049 };
1050
1051 test4 {
1052 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001053 first-syscon = <&syscon0>;
1054 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001055 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001056 };
1057 };
1058
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001059 pwrdom: power-domain {
1060 compatible = "sandbox,power-domain";
1061 #power-domain-cells = <1>;
1062 };
1063
1064 power-domain-test {
1065 compatible = "sandbox,power-domain-test";
1066 power-domains = <&pwrdom 2>;
1067 };
1068
Simon Glass5d9a88f2018-10-01 12:22:40 -06001069 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001070 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001071 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001072 pinctrl-names = "default";
1073 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001074 };
1075
1076 pwm2 {
1077 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001078 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001079 };
1080
Simon Glass64ce0ca2015-07-06 12:54:31 -06001081 ram {
1082 compatible = "sandbox,ram";
1083 };
1084
Simon Glass5010d982015-07-06 12:54:29 -06001085 reset@0 {
1086 compatible = "sandbox,warm-reset";
1087 };
1088
1089 reset@1 {
1090 compatible = "sandbox,reset";
1091 };
1092
Stephen Warren4581b712016-06-17 09:43:59 -06001093 resetc: reset-ctl {
1094 compatible = "sandbox,reset-ctl";
1095 #reset-cells = <1>;
1096 };
1097
1098 reset-ctl-test {
1099 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001100 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1101 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001102 };
1103
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301104 rng {
1105 compatible = "sandbox,sandbox-rng";
1106 };
1107
Nishanth Menon52159402015-09-17 15:42:41 -05001108 rproc_1: rproc@1 {
1109 compatible = "sandbox,test-processor";
1110 remoteproc-name = "remoteproc-test-dev1";
1111 };
1112
1113 rproc_2: rproc@2 {
1114 compatible = "sandbox,test-processor";
1115 internal-memory-mapped;
1116 remoteproc-name = "remoteproc-test-dev2";
1117 };
1118
Simon Glass5d9a88f2018-10-01 12:22:40 -06001119 panel {
1120 compatible = "simple-panel";
1121 backlight = <&backlight 0 100>;
1122 };
1123
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001124 smem@0 {
1125 compatible = "sandbox,smem";
1126 };
1127
Simon Glassd4901892018-12-10 10:37:36 -07001128 sound {
1129 compatible = "sandbox,sound";
1130 cpu {
1131 sound-dai = <&i2s 0>;
1132 };
1133
1134 codec {
1135 sound-dai = <&audio 0>;
1136 };
1137 };
1138
Simon Glass0ae0cb72014-10-13 23:42:11 -06001139 spi@0 {
1140 #address-cells = <1>;
1141 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001142 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001143 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001144 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001145 pinctrl-names = "default";
1146 pinctrl-0 = <&pinmux_spi0_pins>;
1147
Simon Glass0ae0cb72014-10-13 23:42:11 -06001148 spi.bin@0 {
1149 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001150 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001151 spi-max-frequency = <40000000>;
1152 sandbox,filename = "spi.bin";
1153 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001154 spi.bin@1 {
1155 reg = <1>;
1156 compatible = "spansion,m25p16", "jedec,spi-nor";
1157 spi-max-frequency = <50000000>;
1158 sandbox,filename = "spi.bin";
1159 spi-cpol;
1160 spi-cpha;
1161 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001162 };
1163
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001164 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001165 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001166 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001167 };
1168
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001169 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001170 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001171 reg = <0x20 5
1172 0x28 6
1173 0x30 7
1174 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001175 };
1176
Patrick Delaunaya442e612019-03-07 09:57:13 +01001177 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001178 compatible = "simple-mfd", "syscon";
1179 reg = <0x40 5
1180 0x48 6
1181 0x50 7
1182 0x58 8>;
1183 };
1184
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301185 syscon3: syscon@3 {
1186 compatible = "simple-mfd", "syscon";
1187 reg = <0x000100 0x10>;
1188
1189 muxcontroller0: a-mux-controller {
1190 compatible = "mmio-mux";
1191 #mux-control-cells = <1>;
1192
1193 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1194 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1195 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1196 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1197 u-boot,mux-autoprobe;
1198 };
1199 };
1200
1201 muxcontroller1: emul-mux-controller {
1202 compatible = "mux-emul";
1203 #mux-control-cells = <0>;
1204 u-boot,mux-autoprobe;
1205 idle-state = <0xabcd>;
1206 };
1207
Simon Glass93f44e82020-12-16 21:20:27 -07001208 testfdtm0 {
1209 compatible = "denx,u-boot-fdtm-test";
1210 };
1211
1212 testfdtm1: testfdtm1 {
1213 compatible = "denx,u-boot-fdtm-test";
1214 };
1215
1216 testfdtm2 {
1217 compatible = "denx,u-boot-fdtm-test";
1218 };
1219
Sean Anderson7616e362020-09-28 10:52:23 -04001220 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001221 compatible = "sandbox,timer";
1222 clock-frequency = <1000000>;
1223 };
1224
Sean Anderson7616e362020-09-28 10:52:23 -04001225 timer@1 {
1226 compatible = "sandbox,timer";
1227 sandbox,timebase-frequency-fallback;
1228 };
1229
Miquel Raynalb91ad162018-05-15 11:57:27 +02001230 tpm2 {
1231 compatible = "sandbox,tpm2";
1232 };
1233
Simon Glass171e9912015-05-22 15:42:15 -06001234 uart0: serial {
1235 compatible = "sandbox,serial";
1236 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001237 pinctrl-names = "default";
1238 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001239 };
1240
Simon Glasse00cb222015-03-25 12:23:05 -06001241 usb_0: usb@0 {
1242 compatible = "sandbox,usb";
1243 status = "disabled";
1244 hub {
1245 compatible = "sandbox,usb-hub";
1246 #address-cells = <1>;
1247 #size-cells = <0>;
1248 flash-stick {
1249 reg = <0>;
1250 compatible = "sandbox,usb-flash";
1251 };
1252 };
1253 };
1254
1255 usb_1: usb@1 {
1256 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001257 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001258 hub {
1259 compatible = "usb-hub";
1260 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001261 #address-cells = <1>;
1262 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001263 hub-emul {
1264 compatible = "sandbox,usb-hub";
1265 #address-cells = <1>;
1266 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001267 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001268 reg = <0>;
1269 compatible = "sandbox,usb-flash";
1270 sandbox,filepath = "testflash.bin";
1271 };
1272
Simon Glass431cbd62015-11-08 23:48:01 -07001273 flash-stick@1 {
1274 reg = <1>;
1275 compatible = "sandbox,usb-flash";
1276 sandbox,filepath = "testflash1.bin";
1277 };
1278
1279 flash-stick@2 {
1280 reg = <2>;
1281 compatible = "sandbox,usb-flash";
1282 sandbox,filepath = "testflash2.bin";
1283 };
1284
Simon Glassbff1a712015-11-08 23:48:08 -07001285 keyb@3 {
1286 reg = <3>;
1287 compatible = "sandbox,usb-keyb";
1288 };
1289
Simon Glasse00cb222015-03-25 12:23:05 -06001290 };
Michael Wallec03b7612020-06-02 01:47:07 +02001291
1292 usbstor@1 {
1293 reg = <1>;
1294 };
1295 usbstor@3 {
1296 reg = <3>;
1297 };
Simon Glasse00cb222015-03-25 12:23:05 -06001298 };
1299 };
1300
1301 usb_2: usb@2 {
1302 compatible = "sandbox,usb";
1303 status = "disabled";
1304 };
1305
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001306 spmi: spmi@0 {
1307 compatible = "sandbox,spmi";
1308 #address-cells = <0x1>;
1309 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001310 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001311 pm8916@0 {
1312 compatible = "qcom,spmi-pmic";
1313 reg = <0x0 0x1>;
1314 #address-cells = <0x1>;
1315 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001316 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001317
1318 spmi_gpios: gpios@c000 {
1319 compatible = "qcom,pm8916-gpio";
1320 reg = <0xc000 0x400>;
1321 gpio-controller;
1322 gpio-count = <4>;
1323 #gpio-cells = <2>;
1324 gpio-bank-name="spmi";
1325 };
1326 };
1327 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001328
1329 wdt0: wdt@0 {
1330 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001331 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001332 };
Rob Clarkf2006802018-01-10 11:33:30 +01001333
Mario Six957983e2018-08-09 14:51:19 +02001334 axi: axi@0 {
1335 compatible = "sandbox,axi";
1336 #address-cells = <0x1>;
1337 #size-cells = <0x1>;
1338 store@0 {
1339 compatible = "sandbox,sandbox_store";
1340 reg = <0x0 0x400>;
1341 };
1342 };
1343
Rob Clarkf2006802018-01-10 11:33:30 +01001344 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001345 #address-cells = <1>;
1346 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001347 setting = "sunrise ohoka";
1348 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001349 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001350 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001351 chosen-test {
1352 compatible = "denx,u-boot-fdt-test";
1353 reg = <9 1>;
1354 };
1355 };
Mario Sixe8d52912018-03-12 14:53:33 +01001356
1357 translation-test@8000 {
1358 compatible = "simple-bus";
1359 reg = <0x8000 0x4000>;
1360
1361 #address-cells = <0x2>;
1362 #size-cells = <0x1>;
1363
1364 ranges = <0 0x0 0x8000 0x1000
1365 1 0x100 0x9000 0x1000
1366 2 0x200 0xA000 0x1000
1367 3 0x300 0xB000 0x1000
1368 >;
1369
Fabien Dessenne641067f2019-05-31 15:11:30 +02001370 dma-ranges = <0 0x000 0x10000000 0x1000
1371 1 0x100 0x20000000 0x1000
1372 >;
1373
Mario Sixe8d52912018-03-12 14:53:33 +01001374 dev@0,0 {
1375 compatible = "denx,u-boot-fdt-dummy";
1376 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001377 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001378 };
1379
1380 dev@1,100 {
1381 compatible = "denx,u-boot-fdt-dummy";
1382 reg = <1 0x100 0x1000>;
1383
1384 };
1385
1386 dev@2,200 {
1387 compatible = "denx,u-boot-fdt-dummy";
1388 reg = <2 0x200 0x1000>;
1389 };
1390
1391
1392 noxlatebus@3,300 {
1393 compatible = "simple-bus";
1394 reg = <3 0x300 0x1000>;
1395
1396 #address-cells = <0x1>;
1397 #size-cells = <0x0>;
1398
1399 dev@42 {
1400 compatible = "denx,u-boot-fdt-dummy";
1401 reg = <0x42>;
1402 };
1403 };
1404 };
Mario Six4eea5312018-09-27 09:19:31 +02001405
1406 osd {
1407 compatible = "sandbox,sandbox_osd";
1408 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001409
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001410 sandbox_tee {
1411 compatible = "sandbox,tee";
1412 };
Bin Meng4f89d492018-10-15 02:21:26 -07001413
1414 sandbox_virtio1 {
1415 compatible = "sandbox,virtio1";
1416 };
1417
1418 sandbox_virtio2 {
1419 compatible = "sandbox,virtio2";
1420 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001421
Etienne Carriere87d4f272020-09-09 18:44:05 +02001422 sandbox_scmi {
1423 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001424 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001425 resets = <&reset_scmi 3>;
1426 regul0-supply = <&regul0_scmi>;
1427 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001428 };
1429
Patrice Chotardf41a8242018-10-24 14:10:23 +02001430 pinctrl {
1431 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001432
Sean Anderson7f0f1802020-09-14 11:01:57 -04001433 pinctrl-names = "default", "alternate";
1434 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1435 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001436
Sean Anderson7f0f1802020-09-14 11:01:57 -04001437 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001438 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001439 pins = "P5";
1440 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001441 bias-pull-up;
1442 input-disable;
1443 };
1444 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001445 pins = "P6";
1446 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001447 output-high;
1448 drive-open-drain;
1449 };
1450 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001451 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001452 bias-pull-down;
1453 input-enable;
1454 };
1455 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001456 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001457 bias-disable;
1458 };
1459 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001460
1461 pinctrl_i2c: i2c {
1462 groups {
1463 groups = "I2C_UART";
1464 function = "I2C";
1465 };
1466
1467 pins {
1468 pins = "P0", "P1";
1469 drive-open-drain;
1470 };
1471 };
1472
1473 pinctrl_i2s: i2s {
1474 groups = "SPI_I2S";
1475 function = "I2S";
1476 };
1477
1478 pinctrl_spi: spi {
1479 groups = "SPI_I2S";
1480 function = "SPI";
1481
1482 cs {
1483 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1484 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1485 };
1486 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001487 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001488
Dario Binacchi55322622021-04-11 09:39:50 +02001489 pinctrl-single-no-width {
1490 compatible = "pinctrl-single";
1491 reg = <0x0000 0x238>;
1492 #pinctrl-cells = <1>;
1493 pinctrl-single,function-mask = <0x7f>;
1494 };
1495
1496 pinctrl-single-pins {
1497 compatible = "pinctrl-single";
1498 reg = <0x0000 0x238>;
1499 #pinctrl-cells = <1>;
1500 pinctrl-single,register-width = <32>;
1501 pinctrl-single,function-mask = <0x7f>;
1502
1503 pinmux_pwm_pins: pinmux_pwm_pins {
1504 pinctrl-single,pins = < 0x48 0x06 >;
1505 };
1506
1507 pinmux_spi0_pins: pinmux_spi0_pins {
1508 pinctrl-single,pins = <
1509 0x190 0x0c
1510 0x194 0x0c
1511 0x198 0x23
1512 0x19c 0x0c
1513 >;
1514 };
1515
1516 pinmux_uart0_pins: pinmux_uart0_pins {
1517 pinctrl-single,pins = <
1518 0x70 0x30
1519 0x74 0x00
1520 >;
1521 };
1522 };
1523
1524 pinctrl-single-bits {
1525 compatible = "pinctrl-single";
1526 reg = <0x0000 0x50>;
1527 #pinctrl-cells = <2>;
1528 pinctrl-single,bit-per-mux;
1529 pinctrl-single,register-width = <32>;
1530 pinctrl-single,function-mask = <0xf>;
1531
1532 pinmux_i2c0_pins: pinmux_i2c0_pins {
1533 pinctrl-single,bits = <
1534 0x10 0x00002200 0x0000ff00
1535 >;
1536 };
1537
1538 pinmux_lcd_pins: pinmux_lcd_pins {
1539 pinctrl-single,bits = <
1540 0x40 0x22222200 0xffffff00
1541 0x44 0x22222222 0xffffffff
1542 0x48 0x00000022 0x000000ff
1543 0x48 0x02000000 0x0f000000
1544 0x4c 0x02000022 0x0f0000ff
1545 >;
1546 };
1547 };
1548
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001549 hwspinlock@0 {
1550 compatible = "sandbox,hwspinlock";
1551 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001552
1553 dma: dma {
1554 compatible = "sandbox,dma";
1555 #dma-cells = <1>;
1556
1557 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1558 dma-names = "m2m", "tx0", "rx0";
1559 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001560
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001561 /*
1562 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1563 * end of the test. If parent mdio is removed first, clean-up of the
1564 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1565 * active at the end of the test. That it turn doesn't allow the mdio
1566 * class to be destroyed, triggering an error.
1567 */
1568 mdio-mux-test {
1569 compatible = "sandbox,mdio-mux";
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1572 mdio-parent-bus = <&mdio>;
1573
1574 mdio-ch-test@0 {
1575 reg = <0>;
1576 };
1577 mdio-ch-test@1 {
1578 reg = <1>;
1579 };
1580 };
1581
1582 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001583 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001584 #address-cells = <1>;
1585 #size-cells = <0>;
1586
1587 ethphy1: ethernet-phy@1 {
1588 reg = <1>;
1589 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001590 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001591
1592 pm-bus-test {
1593 compatible = "simple-pm-bus";
1594 clocks = <&clk_sandbox 4>;
1595 power-domains = <&pwrdom 1>;
1596 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001597
1598 resetc2: syscon-reset {
1599 compatible = "syscon-reset";
1600 #reset-cells = <1>;
1601 regmap = <&syscon0>;
1602 offset = <1>;
1603 mask = <0x27FFFFFF>;
1604 assert-high = <0>;
1605 };
1606
1607 syscon-reset-test {
1608 compatible = "sandbox,misc_sandbox";
1609 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1610 reset-names = "valid", "no_mask", "out_of_range";
1611 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301612
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001613 sysinfo {
1614 compatible = "sandbox,sysinfo-sandbox";
1615 };
1616
Sean Anderson1cbfed82021-04-20 10:50:58 -04001617 sysinfo-gpio {
1618 compatible = "gpio-sysinfo";
1619 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1620 revisions = <19>, <5>;
1621 names = "rev_a", "foo";
1622 };
1623
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301624 some_regmapped-bus {
1625 #address-cells = <0x1>;
1626 #size-cells = <0x1>;
1627
1628 ranges = <0x0 0x0 0x10>;
1629 compatible = "simple-bus";
1630
1631 regmap-test_0 {
1632 reg = <0 0x10>;
1633 compatible = "sandbox,regmap_test";
1634 };
1635 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001636};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001637
1638#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001639#include "cros-ec-keyboard.dtsi"