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Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Bin Mengdee4d752018-08-03 01:14:41 -070040 pci0 = &pci0;
41 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070042 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020043 remoteproc0 = &rproc_1;
44 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060045 rtc0 = &rtc_0;
46 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060047 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020048 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070049 testbus3 = "/some-bus";
50 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070051 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070052 testfdt3 = "/b-test";
53 testfdt5 = "/some-bus/c-test@5";
54 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070055 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020056 fdt-dummy0 = "/translation-test@8000/dev@0,0";
57 fdt-dummy1 = "/translation-test@8000/dev@1,100";
58 fdt-dummy2 = "/translation-test@8000/dev@2,200";
59 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060060 usb0 = &usb_0;
61 usb1 = &usb_1;
62 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020063 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020064 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060065 };
66
Philippe Reynes059df562022-03-28 22:56:53 +020067 binman {
68 };
69
Rasmus Villemoes8c728422021-04-21 11:06:55 +020070 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060071 testing-bool;
72 testing-int = <123>;
73 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020074 environment {
75 from_fdt = "yes";
76 fdt_env_path = "";
77 };
78 };
79
Simon Glassfb1451b2022-04-24 23:31:24 -060080 bootstd {
81 compatible = "u-boot,boot-std";
82
83 filename-prefixes = "/", "/boot/";
84 bootdev-order = "mmc2", "mmc1";
85
86 syslinux {
87 compatible = "u-boot,distro-syslinux";
88 };
89
90 efi {
91 compatible = "u-boot,distro-efi";
92 };
93 };
94
Nandor Hanf9db2f12021-06-10 16:56:44 +030095 reboot-mode0 {
96 compatible = "reboot-mode-gpio";
97 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
98 u-boot,env-variable = "bootstatus";
99 mode-test = <0x01>;
100 mode-download = <0x03>;
101 };
102
Nandor Hanc74675b2021-06-10 16:56:45 +0300103 reboot_mode1: reboot-mode@14 {
104 compatible = "reboot-mode-rtc";
105 rtc = <&rtc_0>;
106 reg = <0x30 4>;
107 u-boot,env-variable = "bootstatus";
108 big-endian;
109 mode-test = <0x21969147>;
110 mode-download = <0x51939147>;
111 };
112
Simon Glassce6d99a2018-12-10 10:37:33 -0700113 audio: audio-codec {
114 compatible = "sandbox,audio-codec";
115 #sound-dai-cells = <1>;
116 };
117
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200118 buttons {
119 compatible = "gpio-keys";
120
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200121 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200122 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200123 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200124 };
125
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200126 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200127 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200128 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200129 };
130 };
131
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100132 buttons2 {
133 compatible = "adc-keys";
134 io-channels = <&adc 3>;
135 keyup-threshold-microvolt = <3000000>;
136
137 button-up {
138 label = "button3";
139 linux,code = <KEY_F3>;
140 press-threshold-microvolt = <1500000>;
141 };
142
143 button-down {
144 label = "button4";
145 linux,code = <KEY_F4>;
146 press-threshold-microvolt = <1000000>;
147 };
148
149 button-enter {
150 label = "button5";
151 linux,code = <KEY_F5>;
152 press-threshold-microvolt = <500000>;
153 };
154 };
155
Simon Glasse96fa6c2018-12-10 10:37:34 -0700156 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600157 reg = <0 0>;
158 compatible = "google,cros-ec-sandbox";
159
160 /*
161 * This describes the flash memory within the EC. Note
162 * that the STM32L flash erases to 0, not 0xff.
163 */
164 flash {
165 image-pos = <0x08000000>;
166 size = <0x20000>;
167 erase-value = <0>;
168
169 /* Information for sandbox */
170 ro {
171 image-pos = <0>;
172 size = <0xf000>;
173 };
174 wp-ro {
175 image-pos = <0xf000>;
176 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700177 used = <0x884>;
178 compress = "lz4";
179 uncomp-size = <0xcf8>;
180 hash {
181 algo = "sha256";
182 value = [00 01 02 03 04 05 06 07
183 08 09 0a 0b 0c 0d 0e 0f
184 10 11 12 13 14 15 16 17
185 18 19 1a 1b 1c 1d 1e 1f];
186 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600187 };
188 rw {
189 image-pos = <0x10000>;
190 size = <0x10000>;
191 };
192 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300193
194 cros_ec_pwm: cros-ec-pwm {
195 compatible = "google,cros-ec-pwm";
196 #pwm-cells = <1>;
197 };
198
Simon Glasse6c5c942018-10-01 12:22:08 -0600199 };
200
Yannick Fertré23f965a2019-10-07 15:29:05 +0200201 dsi_host: dsi_host {
202 compatible = "sandbox,dsi-host";
203 };
204
Simon Glass2e7d35d2014-02-26 15:59:21 -0700205 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600206 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700207 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600208 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700209 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600210 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100211 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
212 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700213 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100214 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
215 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
216 <&gpio_b 7 GPIO_IN 3 2 1>,
217 <&gpio_b 8 GPIO_OUT 3 2 1>,
218 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100219 test3-gpios =
220 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
221 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
222 <&gpio_c 2 GPIO_OUT>,
223 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
224 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200225 <&gpio_c 5 GPIO_IN>,
226 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
227 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530228 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
229 test5-gpios = <&gpio_a 19>;
230
Simon Glassfb933d02021-10-23 17:26:04 -0600231 bool-value;
Simon Glassa1b17e42018-12-10 10:37:37 -0700232 int-value = <1234>;
233 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200234 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200235 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600236 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700237 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600238 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200239 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530240
241 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
242 <&muxcontroller0 2>, <&muxcontroller0 3>,
243 <&muxcontroller1>;
244 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
245 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100246 display-timings {
247 timing0: 240x320 {
248 clock-frequency = <6500000>;
249 hactive = <240>;
250 vactive = <320>;
251 hfront-porch = <6>;
252 hback-porch = <7>;
253 hsync-len = <1>;
254 vback-porch = <5>;
255 vfront-porch = <8>;
256 vsync-len = <2>;
257 hsync-active = <1>;
258 vsync-active = <0>;
259 de-active = <1>;
260 pixelclk-active = <1>;
261 interlaced;
262 doublescan;
263 doubleclk;
264 };
265 timing1: 480x800 {
266 clock-frequency = <9000000>;
267 hactive = <480>;
268 vactive = <800>;
269 hfront-porch = <10>;
270 hback-porch = <59>;
271 hsync-len = <12>;
272 vback-porch = <15>;
273 vfront-porch = <17>;
274 vsync-len = <16>;
275 hsync-active = <0>;
276 vsync-active = <1>;
277 de-active = <0>;
278 pixelclk-active = <0>;
279 };
280 timing2: 800x480 {
281 clock-frequency = <33500000>;
282 hactive = <800>;
283 vactive = <480>;
284 hback-porch = <89>;
285 hfront-porch = <164>;
286 vback-porch = <23>;
287 vfront-porch = <10>;
288 hsync-len = <11>;
289 vsync-len = <13>;
290 };
291 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700292 };
293
294 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600295 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700296 compatible = "not,compatible";
297 };
298
299 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600300 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700301 };
302
Simon Glass5d9a88f2018-10-01 12:22:40 -0600303 backlight: backlight {
304 compatible = "pwm-backlight";
305 enable-gpios = <&gpio_a 1>;
306 power-supply = <&ldo_1>;
307 pwms = <&pwm 0 1000>;
308 default-brightness-level = <5>;
309 brightness-levels = <0 16 32 64 128 170 202 234 255>;
310 };
311
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200312 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200313 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200314 bind-test-child1 {
315 compatible = "sandbox,phy";
316 #phy-cells = <1>;
317 };
318
319 bind-test-child2 {
320 compatible = "simple-bus";
321 };
322 };
323
Simon Glass2e7d35d2014-02-26 15:59:21 -0700324 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600325 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700326 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600327 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700328 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530329
330 mux-controls = <&muxcontroller0 0>;
331 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700332 };
333
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200334 phy_provider0: gen_phy@0 {
335 compatible = "sandbox,phy";
336 #phy-cells = <1>;
337 };
338
339 phy_provider1: gen_phy@1 {
340 compatible = "sandbox,phy";
341 #phy-cells = <0>;
342 broken;
343 };
344
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200345 phy_provider2: gen_phy@2 {
346 compatible = "sandbox,phy";
347 #phy-cells = <0>;
348 };
349
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200350 gen_phy_user: gen_phy_user {
351 compatible = "simple-bus";
352 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
353 phy-names = "phy1", "phy2", "phy3";
354 };
355
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200356 gen_phy_user1: gen_phy_user1 {
357 compatible = "simple-bus";
358 phys = <&phy_provider0 0>, <&phy_provider2>;
359 phy-names = "phy1", "phy2";
360 };
361
Simon Glass2e7d35d2014-02-26 15:59:21 -0700362 some-bus {
363 #address-cells = <1>;
364 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600365 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600366 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600367 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700368 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600369 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700370 compatible = "denx,u-boot-fdt-test";
371 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600372 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700373 ping-add = <5>;
374 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600375 c-test@0 {
376 compatible = "denx,u-boot-fdt-test";
377 reg = <0>;
378 ping-expect = <6>;
379 ping-add = <6>;
380 };
381 c-test@1 {
382 compatible = "denx,u-boot-fdt-test";
383 reg = <1>;
384 ping-expect = <7>;
385 ping-add = <7>;
386 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700387 };
388
389 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600390 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600391 ping-expect = <6>;
392 ping-add = <6>;
393 compatible = "google,another-fdt-test";
394 };
395
396 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600397 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600398 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700399 ping-add = <6>;
400 compatible = "google,another-fdt-test";
401 };
402
Simon Glass9cc36a22015-01-25 08:27:05 -0700403 f-test {
404 compatible = "denx,u-boot-fdt-test";
405 };
406
407 g-test {
408 compatible = "denx,u-boot-fdt-test";
409 };
410
Bin Meng2786cd72018-10-10 22:07:01 -0700411 h-test {
412 compatible = "denx,u-boot-fdt-test1";
413 };
414
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200415 i-test {
416 compatible = "mediatek,u-boot-fdt-test";
417 #address-cells = <1>;
418 #size-cells = <0>;
419
420 subnode@0 {
421 reg = <0>;
422 };
423
424 subnode@1 {
425 reg = <1>;
426 };
427
428 subnode@2 {
429 reg = <2>;
430 };
431 };
432
Simon Glassdc12ebb2019-12-29 21:19:25 -0700433 devres-test {
434 compatible = "denx,u-boot-devres-test";
435 };
436
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530437 another-test {
438 reg = <0 2>;
439 compatible = "denx,u-boot-fdt-test";
440 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
441 test5-gpios = <&gpio_a 19>;
442 };
443
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100444 mmio-bus@0 {
445 #address-cells = <1>;
446 #size-cells = <1>;
447 compatible = "denx,u-boot-test-bus";
448 dma-ranges = <0x10000000 0x00000000 0x00040000>;
449
450 subnode@0 {
451 compatible = "denx,u-boot-fdt-test";
452 };
453 };
454
455 mmio-bus@1 {
456 #address-cells = <1>;
457 #size-cells = <1>;
458 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100459
460 subnode@0 {
461 compatible = "denx,u-boot-fdt-test";
462 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100463 };
464
Simon Glass0f7b1112020-07-07 13:12:06 -0600465 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600466 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600467 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600468 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600469 child {
470 compatible = "denx,u-boot-acpi-test";
471 };
Simon Glassf50cc952020-04-08 16:57:34 -0600472 };
473
Simon Glass0f7b1112020-07-07 13:12:06 -0600474 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600475 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600476 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600477 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600478 };
479
Patrice Chotardee87a092017-09-04 14:55:57 +0200480 clocks {
481 clk_fixed: clk-fixed {
482 compatible = "fixed-clock";
483 #clock-cells = <0>;
484 clock-frequency = <1234>;
485 };
Anup Patelb630d572019-02-25 08:14:55 +0000486
487 clk_fixed_factor: clk-fixed-factor {
488 compatible = "fixed-factor-clock";
489 #clock-cells = <0>;
490 clock-div = <3>;
491 clock-mult = <2>;
492 clocks = <&clk_fixed>;
493 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200494
495 osc {
496 compatible = "fixed-clock";
497 #clock-cells = <0>;
498 clock-frequency = <20000000>;
499 };
Stephen Warren135aa952016-06-17 09:44:00 -0600500 };
501
502 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600503 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600504 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200505 assigned-clocks = <&clk_sandbox 3>;
506 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600507 };
508
509 clk-test {
510 compatible = "sandbox,clk-test";
511 clocks = <&clk_fixed>,
512 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200513 <&clk_sandbox 0>,
514 <&clk_sandbox 3>,
515 <&clk_sandbox 2>;
516 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600517 };
518
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200519 ccf: clk-ccf {
520 compatible = "sandbox,clk-ccf";
521 };
522
Simon Glass42b7f422021-12-04 08:56:31 -0700523 efi-media {
524 compatible = "sandbox,efi-media";
525 };
526
Simon Glass171e9912015-05-22 15:42:15 -0600527 eth@10002000 {
528 compatible = "sandbox,eth";
529 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600530 };
531
532 eth_5: eth@10003000 {
533 compatible = "sandbox,eth";
534 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400535 nvmem-cells = <&eth5_addr>;
536 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600537 };
538
Bin Meng71d79712015-08-27 22:25:53 -0700539 eth_3: sbe5 {
540 compatible = "sandbox,eth";
541 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400542 nvmem-cells = <&eth3_addr>;
543 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700544 };
545
Simon Glass171e9912015-05-22 15:42:15 -0600546 eth@10004000 {
547 compatible = "sandbox,eth";
548 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600549 };
550
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200551 phy_eth0: phy-test-eth {
552 compatible = "sandbox,eth";
553 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400554 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200555 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200556 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200557 };
558
Claudiu Manoilff98da02021-03-14 20:14:57 +0800559 dsa_eth0: dsa-test-eth {
560 compatible = "sandbox,eth";
561 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400562 nvmem-cells = <&eth4_addr>;
563 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800564 };
565
566 dsa-test {
567 compatible = "sandbox,dsa";
568
569 ports {
570 #address-cells = <1>;
571 #size-cells = <0>;
572 swp_0: port@0 {
573 reg = <0>;
574 label = "lan0";
575 phy-mode = "rgmii-rxid";
576
577 fixed-link {
578 speed = <100>;
579 full-duplex;
580 };
581 };
582
583 swp_1: port@1 {
584 reg = <1>;
585 label = "lan1";
586 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800587 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800588 };
589
590 port@2 {
591 reg = <2>;
592 ethernet = <&dsa_eth0>;
593
594 fixed-link {
595 speed = <1000>;
596 full-duplex;
597 };
598 };
599 };
600 };
601
Rajan Vaja31b82172018-09-19 03:43:46 -0700602 firmware {
603 sandbox_firmware: sandbox-firmware {
604 compatible = "sandbox,firmware";
605 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200606
Etienne Carriere41d62e22022-02-21 09:22:39 +0100607 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200608 compatible = "sandbox,scmi-agent";
609 #address-cells = <1>;
610 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200611
Etienne Carriere41d62e22022-02-21 09:22:39 +0100612 protocol@10 {
613 reg = <0x10>;
614 };
615
616 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200617 reg = <0x14>;
618 #clock-cells = <1>;
619 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200620
Etienne Carriere41d62e22022-02-21 09:22:39 +0100621 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200622 reg = <0x16>;
623 #reset-cells = <1>;
624 };
Etienne Carriere01242182021-03-08 22:38:07 +0100625
626 protocol@17 {
627 reg = <0x17>;
628
629 regulators {
630 #address-cells = <1>;
631 #size-cells = <0>;
632
Etienne Carriere41d62e22022-02-21 09:22:39 +0100633 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100634 reg = <0>;
635 regulator-name = "sandbox-voltd0";
636 regulator-min-microvolt = <1100000>;
637 regulator-max-microvolt = <3300000>;
638 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100639 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100640 reg = <0x1>;
641 regulator-name = "sandbox-voltd1";
642 regulator-min-microvolt = <1800000>;
643 };
644 };
645 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200646 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700647 };
648
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100649 pinctrl-gpio {
650 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700651
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100652 gpio_a: base-gpios {
653 compatible = "sandbox,gpio";
654 gpio-controller;
655 #gpio-cells = <1>;
656 gpio-bank-name = "a";
657 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200658 hog_input_active_low {
659 gpio-hog;
660 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200661 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200662 };
663 hog_input_active_high {
664 gpio-hog;
665 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200666 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200667 };
668 hog_output_low {
669 gpio-hog;
670 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200671 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200672 };
673 hog_output_high {
674 gpio-hog;
675 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200676 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200677 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100678 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600679
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100680 gpio_b: extra-gpios {
681 compatible = "sandbox,gpio";
682 gpio-controller;
683 #gpio-cells = <5>;
684 gpio-bank-name = "b";
685 sandbox,gpio-count = <10>;
686 };
687
688 gpio_c: pinmux-gpios {
689 compatible = "sandbox,gpio";
690 gpio-controller;
691 #gpio-cells = <2>;
692 gpio-bank-name = "c";
693 sandbox,gpio-count = <10>;
694 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100695 };
696
Simon Glassecc2ed52014-12-10 08:55:55 -0700697 i2c@0 {
698 #address-cells = <1>;
699 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600700 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700701 compatible = "sandbox,i2c";
702 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200703 pinctrl-names = "default";
704 pinctrl-0 = <&pinmux_i2c0_pins>;
705
Simon Glassecc2ed52014-12-10 08:55:55 -0700706 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400707 #address-cells = <1>;
708 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700709 reg = <0x2c>;
710 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700711 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200712 partitions {
713 compatible = "fixed-partitions";
714 #address-cells = <1>;
715 #size-cells = <1>;
716 bootcount_i2c: bootcount@10 {
717 reg = <10 2>;
718 };
719 };
Sean Anderson472caa62022-05-05 13:11:42 -0400720
721 eth3_addr: mac-address@24 {
722 reg = <24 6>;
723 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700724 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200725
Simon Glass52d3bc52015-05-22 15:42:17 -0600726 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400727 #address-cells = <1>;
728 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600729 reg = <0x43>;
730 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700731 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400732
733 eth4_addr: mac-address@40 {
734 reg = <0x40 6>;
735 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600736 };
737
738 rtc_1: rtc@61 {
739 reg = <0x61>;
740 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700741 sandbox,emul = <&emul1>;
742 };
743
744 i2c_emul: emul {
745 reg = <0xff>;
746 compatible = "sandbox,i2c-emul-parent";
747 emul_eeprom: emul-eeprom {
748 compatible = "sandbox,i2c-eeprom";
749 sandbox,filename = "i2c.bin";
750 sandbox,size = <256>;
751 };
752 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700753 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700754 };
755 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700756 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600757 };
758 };
759
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200760 sandbox_pmic: sandbox_pmic {
761 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700762 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200763 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200764
765 mc34708: pmic@41 {
766 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700767 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200768 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700769 };
770
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100771 bootcount@0 {
772 compatible = "u-boot,bootcount-rtc";
773 rtc = <&rtc_1>;
774 offset = <0x13>;
775 };
776
Michal Simekf692b472020-05-28 11:48:55 +0200777 bootcount {
778 compatible = "u-boot,bootcount-i2c-eeprom";
779 i2c-eeprom = <&bootcount_i2c>;
780 };
781
Nandor Hanc50b21b2021-06-10 15:40:38 +0300782 bootcount_4@0 {
783 compatible = "u-boot,bootcount-syscon";
784 syscon = <&syscon0>;
785 reg = <0x0 0x04>, <0x0 0x04>;
786 reg-names = "syscon_reg", "offset";
787 };
788
789 bootcount_2@0 {
790 compatible = "u-boot,bootcount-syscon";
791 syscon = <&syscon0>;
792 reg = <0x0 0x04>, <0x0 0x02> ;
793 reg-names = "syscon_reg", "offset";
794 };
795
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100796 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100797 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100798 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100799 vdd-supply = <&buck2>;
800 vss-microvolts = <0>;
801 };
802
Mark Kettenisfb574622021-10-23 16:58:02 +0200803 iommu: iommu@0 {
804 compatible = "sandbox,iommu";
805 #iommu-cells = <0>;
806 };
807
Simon Glass02554352020-02-06 09:55:00 -0700808 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700809 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700810 interrupt-controller;
811 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700812 };
813
Simon Glass3c97c4f2016-01-18 19:52:26 -0700814 lcd {
815 u-boot,dm-pre-reloc;
816 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200817 pinctrl-names = "default";
818 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700819 xres = <1366>;
820 yres = <768>;
821 };
822
Simon Glass3c43fba2015-07-06 12:54:34 -0600823 leds {
824 compatible = "gpio-leds";
825
826 iracibble {
827 gpios = <&gpio_a 1 0>;
828 label = "sandbox:red";
829 };
830
831 martinet {
832 gpios = <&gpio_a 2 0>;
833 label = "sandbox:green";
834 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200835
836 default_on {
837 gpios = <&gpio_a 5 0>;
838 label = "sandbox:default_on";
839 default-state = "on";
840 };
841
842 default_off {
843 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400844 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200845 default-state = "off";
846 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600847 };
848
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200849 gpio-wdt {
850 gpios = <&gpio_a 7 0>;
851 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200852 hw_margin_ms = <100>;
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200853 always-running;
854 };
855
Stephen Warren8961b522016-05-16 17:41:37 -0600856 mbox: mbox {
857 compatible = "sandbox,mbox";
858 #mbox-cells = <1>;
859 };
860
861 mbox-test {
862 compatible = "sandbox,mbox-test";
863 mboxes = <&mbox 100>, <&mbox 1>;
864 mbox-names = "other", "test";
865 };
866
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900867 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200868 #address-cells = <1>;
869 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400870 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200871 cpu1: cpu@1 {
872 device_type = "cpu";
873 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400874 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900875 compatible = "sandbox,cpu_sandbox";
876 u-boot,dm-pre-reloc;
877 };
Mario Sixfa44b532018-08-06 10:23:44 +0200878
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200879 cpu2: cpu@2 {
880 device_type = "cpu";
881 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900882 compatible = "sandbox,cpu_sandbox";
883 u-boot,dm-pre-reloc;
884 };
Mario Sixfa44b532018-08-06 10:23:44 +0200885
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200886 cpu3: cpu@3 {
887 device_type = "cpu";
888 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900889 compatible = "sandbox,cpu_sandbox";
890 u-boot,dm-pre-reloc;
891 };
Mario Sixfa44b532018-08-06 10:23:44 +0200892 };
893
Dave Gerlach21e3c212020-07-15 23:39:58 -0500894 chipid: chipid {
895 compatible = "sandbox,soc";
896 };
897
Simon Glasse96fa6c2018-12-10 10:37:34 -0700898 i2s: i2s {
899 compatible = "sandbox,i2s";
900 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700901 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700902 };
903
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200904 nop-test_0 {
905 compatible = "sandbox,nop_sandbox1";
906 nop-test_1 {
907 compatible = "sandbox,nop_sandbox2";
908 bind = "True";
909 };
910 nop-test_2 {
911 compatible = "sandbox,nop_sandbox2";
912 bind = "False";
913 };
914 };
915
Mario Six004e67c2018-07-31 14:24:14 +0200916 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -0400917 #address-cells = <1>;
918 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +0200919 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -0400920
921 eth5_addr: mac-address@10 {
922 reg = <0x10 6>;
923 };
Mario Six004e67c2018-07-31 14:24:14 +0200924 };
925
Simon Glasse48eeb92017-04-23 20:02:07 -0600926 mmc2 {
927 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -0600928 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -0600929 };
930
Simon Glassfb1451b2022-04-24 23:31:24 -0600931 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -0600932 mmc1 {
933 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -0600934 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -0600935 };
936
Simon Glassfb1451b2022-04-24 23:31:24 -0600937 /* This is used for the fastboot tests */
Simon Glasse48eeb92017-04-23 20:02:07 -0600938 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -0600939 compatible = "sandbox,mmc";
940 };
941
Simon Glassb45c8332019-02-16 20:24:50 -0700942 pch {
943 compatible = "sandbox,pch";
944 };
945
Tom Rini42c64d12020-02-11 12:41:23 -0500946 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -0700947 compatible = "sandbox,pci";
948 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -0500949 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -0700950 #address-cells = <3>;
951 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -0600952 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -0700953 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700954 pci@0,0 {
955 compatible = "pci-generic";
956 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600957 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -0700958 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300959 pci@1,0 {
960 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600961 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
962 reg = <0x02000814 0 0 0 0
963 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600964 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +0300965 };
Simon Glass3e17ffb2019-12-06 21:41:57 -0700966 p2sb-pci@2,0 {
967 compatible = "sandbox,p2sb";
968 reg = <0x02001010 0 0 0 0>;
969 sandbox,emul = <&p2sb_emul>;
970
971 adder {
972 intel,p2sb-port-id = <3>;
973 compatible = "sandbox,adder";
974 };
975 };
Simon Glass3b65ee32019-12-06 21:41:54 -0700976 pci@1e,0 {
977 compatible = "sandbox,pmc";
978 reg = <0xf000 0 0 0 0>;
979 sandbox,emul = <&pmc_emul1e>;
980 acpi-base = <0x400>;
981 gpe0-dwx-mask = <0xf>;
982 gpe0-dwx-shift-base = <4>;
983 gpe0-dw = <6 7 9>;
984 gpe0-sts = <0x20>;
985 gpe0-en = <0x30>;
986 };
Simon Glassd3b7ff12015-03-05 12:25:34 -0700987 pci@1f,0 {
988 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -0600989 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
990 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -0600991 sandbox,emul = <&swap_case_emul0_1f>;
992 };
993 };
994
995 pci-emul0 {
996 compatible = "sandbox,pci-emul-parent";
997 swap_case_emul0_0: emul0@0,0 {
998 compatible = "sandbox,swap-case";
999 };
1000 swap_case_emul0_1: emul0@1,0 {
1001 compatible = "sandbox,swap-case";
1002 use-ea;
1003 };
1004 swap_case_emul0_1f: emul0@1f,0 {
1005 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001006 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001007 p2sb_emul: emul@2,0 {
1008 compatible = "sandbox,p2sb-emul";
1009 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001010 pmc_emul1e: emul@1e,0 {
1011 compatible = "sandbox,pmc-emul";
1012 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001013 };
1014
Tom Rini42c64d12020-02-11 12:41:23 -05001015 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001016 compatible = "sandbox,pci";
1017 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001018 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001019 #address-cells = <3>;
1020 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001021 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001022 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001023 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001024 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001025 0x0c 0x00 0x1234 0x5678
1026 0x10 0x00 0x1234 0x5678>;
1027 pci@10,0 {
1028 reg = <0x8000 0 0 0 0>;
1029 };
Bin Mengdee4d752018-08-03 01:14:41 -07001030 };
1031
Tom Rini42c64d12020-02-11 12:41:23 -05001032 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001033 compatible = "sandbox,pci";
1034 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001035 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001036 #address-cells = <3>;
1037 #size-cells = <2>;
1038 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1039 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1040 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1041 pci@1f,0 {
1042 compatible = "pci-generic";
1043 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001044 sandbox,emul = <&swap_case_emul2_1f>;
1045 };
1046 };
1047
1048 pci-emul2 {
1049 compatible = "sandbox,pci-emul-parent";
1050 swap_case_emul2_1f: emul2@1f,0 {
1051 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001052 };
1053 };
1054
Ramon Friedbb413332019-04-27 11:15:23 +03001055 pci_ep: pci_ep {
1056 compatible = "sandbox,pci_ep";
1057 };
1058
Simon Glass98561572017-04-23 20:10:44 -06001059 probing {
1060 compatible = "simple-bus";
1061 test1 {
1062 compatible = "denx,u-boot-probe-test";
1063 };
1064
1065 test2 {
1066 compatible = "denx,u-boot-probe-test";
1067 };
1068
1069 test3 {
1070 compatible = "denx,u-boot-probe-test";
1071 };
1072
1073 test4 {
1074 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001075 first-syscon = <&syscon0>;
1076 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001077 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001078 };
1079 };
1080
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001081 pwrdom: power-domain {
1082 compatible = "sandbox,power-domain";
1083 #power-domain-cells = <1>;
1084 };
1085
1086 power-domain-test {
1087 compatible = "sandbox,power-domain-test";
1088 power-domains = <&pwrdom 2>;
1089 };
1090
Simon Glass5d9a88f2018-10-01 12:22:40 -06001091 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001092 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001093 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001094 pinctrl-names = "default";
1095 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001096 };
1097
1098 pwm2 {
1099 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001100 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001101 };
1102
Simon Glass64ce0ca2015-07-06 12:54:31 -06001103 ram {
1104 compatible = "sandbox,ram";
1105 };
1106
Simon Glass5010d982015-07-06 12:54:29 -06001107 reset@0 {
1108 compatible = "sandbox,warm-reset";
1109 };
1110
1111 reset@1 {
1112 compatible = "sandbox,reset";
1113 };
1114
Stephen Warren4581b712016-06-17 09:43:59 -06001115 resetc: reset-ctl {
1116 compatible = "sandbox,reset-ctl";
1117 #reset-cells = <1>;
1118 };
1119
1120 reset-ctl-test {
1121 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001122 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1123 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001124 };
1125
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301126 rng {
1127 compatible = "sandbox,sandbox-rng";
1128 };
1129
Nishanth Menon52159402015-09-17 15:42:41 -05001130 rproc_1: rproc@1 {
1131 compatible = "sandbox,test-processor";
1132 remoteproc-name = "remoteproc-test-dev1";
1133 };
1134
1135 rproc_2: rproc@2 {
1136 compatible = "sandbox,test-processor";
1137 internal-memory-mapped;
1138 remoteproc-name = "remoteproc-test-dev2";
1139 };
1140
Simon Glass5d9a88f2018-10-01 12:22:40 -06001141 panel {
1142 compatible = "simple-panel";
1143 backlight = <&backlight 0 100>;
1144 };
1145
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001146 smem@0 {
1147 compatible = "sandbox,smem";
1148 };
1149
Simon Glassd4901892018-12-10 10:37:36 -07001150 sound {
1151 compatible = "sandbox,sound";
1152 cpu {
1153 sound-dai = <&i2s 0>;
1154 };
1155
1156 codec {
1157 sound-dai = <&audio 0>;
1158 };
1159 };
1160
Simon Glass0ae0cb72014-10-13 23:42:11 -06001161 spi@0 {
1162 #address-cells = <1>;
1163 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001164 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001165 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001166 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001167 pinctrl-names = "default";
1168 pinctrl-0 = <&pinmux_spi0_pins>;
1169
Simon Glass0ae0cb72014-10-13 23:42:11 -06001170 spi.bin@0 {
1171 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001172 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001173 spi-max-frequency = <40000000>;
1174 sandbox,filename = "spi.bin";
1175 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001176 spi.bin@1 {
1177 reg = <1>;
1178 compatible = "spansion,m25p16", "jedec,spi-nor";
1179 spi-max-frequency = <50000000>;
1180 sandbox,filename = "spi.bin";
1181 spi-cpol;
1182 spi-cpha;
1183 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001184 };
1185
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001186 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001187 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001188 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001189 };
1190
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001191 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001192 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001193 reg = <0x20 5
1194 0x28 6
1195 0x30 7
1196 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001197 };
1198
Patrick Delaunaya442e612019-03-07 09:57:13 +01001199 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001200 compatible = "simple-mfd", "syscon";
1201 reg = <0x40 5
1202 0x48 6
1203 0x50 7
1204 0x58 8>;
1205 };
1206
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301207 syscon3: syscon@3 {
1208 compatible = "simple-mfd", "syscon";
1209 reg = <0x000100 0x10>;
1210
1211 muxcontroller0: a-mux-controller {
1212 compatible = "mmio-mux";
1213 #mux-control-cells = <1>;
1214
1215 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1216 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1217 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1218 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1219 u-boot,mux-autoprobe;
1220 };
1221 };
1222
1223 muxcontroller1: emul-mux-controller {
1224 compatible = "mux-emul";
1225 #mux-control-cells = <0>;
1226 u-boot,mux-autoprobe;
1227 idle-state = <0xabcd>;
1228 };
1229
Simon Glass93f44e82020-12-16 21:20:27 -07001230 testfdtm0 {
1231 compatible = "denx,u-boot-fdtm-test";
1232 };
1233
1234 testfdtm1: testfdtm1 {
1235 compatible = "denx,u-boot-fdtm-test";
1236 };
1237
1238 testfdtm2 {
1239 compatible = "denx,u-boot-fdtm-test";
1240 };
1241
Sean Anderson7616e362020-09-28 10:52:23 -04001242 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001243 compatible = "sandbox,timer";
1244 clock-frequency = <1000000>;
1245 };
1246
Sean Anderson7616e362020-09-28 10:52:23 -04001247 timer@1 {
1248 compatible = "sandbox,timer";
1249 sandbox,timebase-frequency-fallback;
1250 };
1251
Miquel Raynalb91ad162018-05-15 11:57:27 +02001252 tpm2 {
1253 compatible = "sandbox,tpm2";
1254 };
1255
Simon Glass171e9912015-05-22 15:42:15 -06001256 uart0: serial {
1257 compatible = "sandbox,serial";
1258 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001259 pinctrl-names = "default";
1260 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001261 };
1262
Simon Glasse00cb222015-03-25 12:23:05 -06001263 usb_0: usb@0 {
1264 compatible = "sandbox,usb";
1265 status = "disabled";
1266 hub {
1267 compatible = "sandbox,usb-hub";
1268 #address-cells = <1>;
1269 #size-cells = <0>;
1270 flash-stick {
1271 reg = <0>;
1272 compatible = "sandbox,usb-flash";
1273 };
1274 };
1275 };
1276
1277 usb_1: usb@1 {
1278 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001279 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001280 hub {
1281 compatible = "usb-hub";
1282 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001283 #address-cells = <1>;
1284 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001285 hub-emul {
1286 compatible = "sandbox,usb-hub";
1287 #address-cells = <1>;
1288 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001289 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001290 reg = <0>;
1291 compatible = "sandbox,usb-flash";
1292 sandbox,filepath = "testflash.bin";
1293 };
1294
Simon Glass431cbd62015-11-08 23:48:01 -07001295 flash-stick@1 {
1296 reg = <1>;
1297 compatible = "sandbox,usb-flash";
1298 sandbox,filepath = "testflash1.bin";
1299 };
1300
1301 flash-stick@2 {
1302 reg = <2>;
1303 compatible = "sandbox,usb-flash";
1304 sandbox,filepath = "testflash2.bin";
1305 };
1306
Simon Glassbff1a712015-11-08 23:48:08 -07001307 keyb@3 {
1308 reg = <3>;
1309 compatible = "sandbox,usb-keyb";
1310 };
1311
Simon Glasse00cb222015-03-25 12:23:05 -06001312 };
Michael Wallec03b7612020-06-02 01:47:07 +02001313
1314 usbstor@1 {
1315 reg = <1>;
1316 };
1317 usbstor@3 {
1318 reg = <3>;
1319 };
Simon Glasse00cb222015-03-25 12:23:05 -06001320 };
1321 };
1322
1323 usb_2: usb@2 {
1324 compatible = "sandbox,usb";
1325 status = "disabled";
1326 };
1327
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001328 spmi: spmi@0 {
1329 compatible = "sandbox,spmi";
1330 #address-cells = <0x1>;
1331 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001332 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001333 pm8916@0 {
1334 compatible = "qcom,spmi-pmic";
1335 reg = <0x0 0x1>;
1336 #address-cells = <0x1>;
1337 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001338 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001339
1340 spmi_gpios: gpios@c000 {
1341 compatible = "qcom,pm8916-gpio";
1342 reg = <0xc000 0x400>;
1343 gpio-controller;
1344 gpio-count = <4>;
1345 #gpio-cells = <2>;
1346 gpio-bank-name="spmi";
1347 };
1348 };
1349 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001350
1351 wdt0: wdt@0 {
1352 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001353 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001354 };
Rob Clarkf2006802018-01-10 11:33:30 +01001355
Mario Six957983e2018-08-09 14:51:19 +02001356 axi: axi@0 {
1357 compatible = "sandbox,axi";
1358 #address-cells = <0x1>;
1359 #size-cells = <0x1>;
1360 store@0 {
1361 compatible = "sandbox,sandbox_store";
1362 reg = <0x0 0x400>;
1363 };
1364 };
1365
Rob Clarkf2006802018-01-10 11:33:30 +01001366 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001367 #address-cells = <1>;
1368 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001369 setting = "sunrise ohoka";
1370 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001371 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001372 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001373 chosen-test {
1374 compatible = "denx,u-boot-fdt-test";
1375 reg = <9 1>;
1376 };
1377 };
Mario Sixe8d52912018-03-12 14:53:33 +01001378
1379 translation-test@8000 {
1380 compatible = "simple-bus";
1381 reg = <0x8000 0x4000>;
1382
1383 #address-cells = <0x2>;
1384 #size-cells = <0x1>;
1385
1386 ranges = <0 0x0 0x8000 0x1000
1387 1 0x100 0x9000 0x1000
1388 2 0x200 0xA000 0x1000
1389 3 0x300 0xB000 0x1000
1390 >;
1391
Fabien Dessenne641067f2019-05-31 15:11:30 +02001392 dma-ranges = <0 0x000 0x10000000 0x1000
1393 1 0x100 0x20000000 0x1000
1394 >;
1395
Mario Sixe8d52912018-03-12 14:53:33 +01001396 dev@0,0 {
1397 compatible = "denx,u-boot-fdt-dummy";
1398 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001399 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001400 };
1401
1402 dev@1,100 {
1403 compatible = "denx,u-boot-fdt-dummy";
1404 reg = <1 0x100 0x1000>;
1405
1406 };
1407
1408 dev@2,200 {
1409 compatible = "denx,u-boot-fdt-dummy";
1410 reg = <2 0x200 0x1000>;
1411 };
1412
1413
1414 noxlatebus@3,300 {
1415 compatible = "simple-bus";
1416 reg = <3 0x300 0x1000>;
1417
1418 #address-cells = <0x1>;
1419 #size-cells = <0x0>;
1420
1421 dev@42 {
1422 compatible = "denx,u-boot-fdt-dummy";
1423 reg = <0x42>;
1424 };
1425 };
1426 };
Mario Six4eea5312018-09-27 09:19:31 +02001427
1428 osd {
1429 compatible = "sandbox,sandbox_osd";
1430 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001431
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001432 sandbox_tee {
1433 compatible = "sandbox,tee";
1434 };
Bin Meng4f89d492018-10-15 02:21:26 -07001435
1436 sandbox_virtio1 {
1437 compatible = "sandbox,virtio1";
1438 };
1439
1440 sandbox_virtio2 {
1441 compatible = "sandbox,virtio2";
1442 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001443
Etienne Carriere87d4f272020-09-09 18:44:05 +02001444 sandbox_scmi {
1445 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001446 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001447 resets = <&reset_scmi 3>;
1448 regul0-supply = <&regul0_scmi>;
1449 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001450 };
1451
Patrice Chotardf41a8242018-10-24 14:10:23 +02001452 pinctrl {
1453 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001454
Sean Anderson7f0f1802020-09-14 11:01:57 -04001455 pinctrl-names = "default", "alternate";
1456 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1457 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001458
Sean Anderson7f0f1802020-09-14 11:01:57 -04001459 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001460 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001461 pins = "P5";
1462 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001463 bias-pull-up;
1464 input-disable;
1465 };
1466 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001467 pins = "P6";
1468 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001469 output-high;
1470 drive-open-drain;
1471 };
1472 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001473 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001474 bias-pull-down;
1475 input-enable;
1476 };
1477 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001478 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001479 bias-disable;
1480 };
1481 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001482
1483 pinctrl_i2c: i2c {
1484 groups {
1485 groups = "I2C_UART";
1486 function = "I2C";
1487 };
1488
1489 pins {
1490 pins = "P0", "P1";
1491 drive-open-drain;
1492 };
1493 };
1494
1495 pinctrl_i2s: i2s {
1496 groups = "SPI_I2S";
1497 function = "I2S";
1498 };
1499
1500 pinctrl_spi: spi {
1501 groups = "SPI_I2S";
1502 function = "SPI";
1503
1504 cs {
1505 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1506 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1507 };
1508 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001509 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001510
Dario Binacchi55322622021-04-11 09:39:50 +02001511 pinctrl-single-no-width {
1512 compatible = "pinctrl-single";
1513 reg = <0x0000 0x238>;
1514 #pinctrl-cells = <1>;
1515 pinctrl-single,function-mask = <0x7f>;
1516 };
1517
1518 pinctrl-single-pins {
1519 compatible = "pinctrl-single";
1520 reg = <0x0000 0x238>;
1521 #pinctrl-cells = <1>;
1522 pinctrl-single,register-width = <32>;
1523 pinctrl-single,function-mask = <0x7f>;
1524
1525 pinmux_pwm_pins: pinmux_pwm_pins {
1526 pinctrl-single,pins = < 0x48 0x06 >;
1527 };
1528
1529 pinmux_spi0_pins: pinmux_spi0_pins {
1530 pinctrl-single,pins = <
1531 0x190 0x0c
1532 0x194 0x0c
1533 0x198 0x23
1534 0x19c 0x0c
1535 >;
1536 };
1537
1538 pinmux_uart0_pins: pinmux_uart0_pins {
1539 pinctrl-single,pins = <
1540 0x70 0x30
1541 0x74 0x00
1542 >;
1543 };
1544 };
1545
1546 pinctrl-single-bits {
1547 compatible = "pinctrl-single";
1548 reg = <0x0000 0x50>;
1549 #pinctrl-cells = <2>;
1550 pinctrl-single,bit-per-mux;
1551 pinctrl-single,register-width = <32>;
1552 pinctrl-single,function-mask = <0xf>;
1553
1554 pinmux_i2c0_pins: pinmux_i2c0_pins {
1555 pinctrl-single,bits = <
1556 0x10 0x00002200 0x0000ff00
1557 >;
1558 };
1559
1560 pinmux_lcd_pins: pinmux_lcd_pins {
1561 pinctrl-single,bits = <
1562 0x40 0x22222200 0xffffff00
1563 0x44 0x22222222 0xffffffff
1564 0x48 0x00000022 0x000000ff
1565 0x48 0x02000000 0x0f000000
1566 0x4c 0x02000022 0x0f0000ff
1567 >;
1568 };
1569 };
1570
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001571 hwspinlock@0 {
1572 compatible = "sandbox,hwspinlock";
1573 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001574
1575 dma: dma {
1576 compatible = "sandbox,dma";
1577 #dma-cells = <1>;
1578
1579 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1580 dma-names = "m2m", "tx0", "rx0";
1581 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001582
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001583 /*
1584 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1585 * end of the test. If parent mdio is removed first, clean-up of the
1586 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1587 * active at the end of the test. That it turn doesn't allow the mdio
1588 * class to be destroyed, triggering an error.
1589 */
1590 mdio-mux-test {
1591 compatible = "sandbox,mdio-mux";
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1594 mdio-parent-bus = <&mdio>;
1595
1596 mdio-ch-test@0 {
1597 reg = <0>;
1598 };
1599 mdio-ch-test@1 {
1600 reg = <1>;
1601 };
1602 };
1603
1604 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001605 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001606 #address-cells = <1>;
1607 #size-cells = <0>;
1608
1609 ethphy1: ethernet-phy@1 {
1610 reg = <1>;
1611 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001612 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001613
1614 pm-bus-test {
1615 compatible = "simple-pm-bus";
1616 clocks = <&clk_sandbox 4>;
1617 power-domains = <&pwrdom 1>;
1618 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001619
1620 resetc2: syscon-reset {
1621 compatible = "syscon-reset";
1622 #reset-cells = <1>;
1623 regmap = <&syscon0>;
1624 offset = <1>;
1625 mask = <0x27FFFFFF>;
1626 assert-high = <0>;
1627 };
1628
1629 syscon-reset-test {
1630 compatible = "sandbox,misc_sandbox";
1631 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1632 reset-names = "valid", "no_mask", "out_of_range";
1633 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301634
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001635 sysinfo {
1636 compatible = "sandbox,sysinfo-sandbox";
1637 };
1638
Sean Anderson1cbfed82021-04-20 10:50:58 -04001639 sysinfo-gpio {
1640 compatible = "gpio-sysinfo";
1641 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1642 revisions = <19>, <5>;
1643 names = "rev_a", "foo";
1644 };
1645
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301646 some_regmapped-bus {
1647 #address-cells = <0x1>;
1648 #size-cells = <0x1>;
1649
1650 ranges = <0x0 0x0 0x10>;
1651 compatible = "simple-bus";
1652
1653 regmap-test_0 {
1654 reg = <0 0x10>;
1655 compatible = "sandbox,regmap_test";
1656 };
1657 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001658};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001659
1660#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001661#include "cros-ec-keyboard.dtsi"