blob: 25fd2bcab871f715eb3eb5a909f456244fa35a8c [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Bin Mengdee4d752018-08-03 01:14:41 -070042 pci0 = &pci0;
43 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070044 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020045 remoteproc0 = &rproc_1;
46 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060047 rtc0 = &rtc_0;
48 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060049 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020050 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070051 testbus3 = "/some-bus";
52 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070053 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070054 testfdt3 = "/b-test";
55 testfdt5 = "/some-bus/c-test@5";
56 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070057 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020058 fdt-dummy0 = "/translation-test@8000/dev@0,0";
59 fdt-dummy1 = "/translation-test@8000/dev@1,100";
60 fdt-dummy2 = "/translation-test@8000/dev@2,200";
61 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060062 usb0 = &usb_0;
63 usb1 = &usb_1;
64 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020065 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020066 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060067 };
68
Simon Glass8de98962022-10-20 18:23:15 -060069 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020070 };
71
Rasmus Villemoes8c728422021-04-21 11:06:55 +020072 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060073 testing-bool;
74 testing-int = <123>;
75 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020076 environment {
77 from_fdt = "yes";
78 fdt_env_path = "";
79 };
80 };
81
Simon Glassfb1451b2022-04-24 23:31:24 -060082 bootstd {
Simon Glassa56f6632022-10-20 18:23:14 -060083 u-boot,dm-vpl;
Simon Glassfb1451b2022-04-24 23:31:24 -060084 compatible = "u-boot,boot-std";
85
86 filename-prefixes = "/", "/boot/";
87 bootdev-order = "mmc2", "mmc1";
88
89 syslinux {
90 compatible = "u-boot,distro-syslinux";
91 };
92
93 efi {
94 compatible = "u-boot,distro-efi";
95 };
Simon Glassa56f6632022-10-20 18:23:14 -060096
Simon Glass77bec9e2022-10-20 18:23:20 -060097 /*
98 * This is used for the VBE OS-request tests. A FAT filesystem
99 * created in a partition with the VBE information appearing
100 * before the parititon starts
101 */
Simon Glassa56f6632022-10-20 18:23:14 -0600102 firmware0 {
103 u-boot,dm-vpl;
104 compatible = "fwupd,vbe-simple";
105 storage = "mmc1";
106 skip-offset = <0x200>;
107 area-start = <0x400>;
108 area-size = <0x1000>;
109 state-offset = <0x400>;
110 state-size = <0x40>;
111 version-offset = <0x800>;
112 version-size = <0x100>;
113 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600114
115 /*
116 * This is used for the VBE VPL tests. The MMC device holds the
117 * binman image.bin file. The test progresses through each phase
118 * of U-Boot, loading each in turn from MMC.
119 *
120 * Note that the test enables this node (and mmc3) before
121 * running U-Boot
122 */
123 firmware1 {
124 u-boot,dm-vpl;
125 status = "disabled";
126 compatible = "fwupd,vbe-simple";
127 storage = "mmc3";
128 skip-offset = <0x400000>;
129 area-start = <0>;
130 area-size = <0xe00000>;
131 state-offset = <0xdffc00>;
132 state-size = <0x40>;
133 version-offset = <0xdffe00>;
134 version-size = <0x100>;
135 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600136 };
137
Andrew Scull0518e7a2022-05-30 10:00:12 +0000138 fuzzing-engine {
139 compatible = "sandbox,fuzzing-engine";
140 };
141
Nandor Hanf9db2f12021-06-10 16:56:44 +0300142 reboot-mode0 {
143 compatible = "reboot-mode-gpio";
144 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
145 u-boot,env-variable = "bootstatus";
146 mode-test = <0x01>;
147 mode-download = <0x03>;
148 };
149
Nandor Hanc74675b2021-06-10 16:56:45 +0300150 reboot_mode1: reboot-mode@14 {
151 compatible = "reboot-mode-rtc";
152 rtc = <&rtc_0>;
153 reg = <0x30 4>;
154 u-boot,env-variable = "bootstatus";
155 big-endian;
156 mode-test = <0x21969147>;
157 mode-download = <0x51939147>;
158 };
159
Simon Glassce6d99a2018-12-10 10:37:33 -0700160 audio: audio-codec {
161 compatible = "sandbox,audio-codec";
162 #sound-dai-cells = <1>;
163 };
164
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200165 buttons {
166 compatible = "gpio-keys";
167
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200168 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200169 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200170 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200171 };
172
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200173 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200174 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200175 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200176 };
177 };
178
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100179 buttons2 {
180 compatible = "adc-keys";
181 io-channels = <&adc 3>;
182 keyup-threshold-microvolt = <3000000>;
183
184 button-up {
185 label = "button3";
186 linux,code = <KEY_F3>;
187 press-threshold-microvolt = <1500000>;
188 };
189
190 button-down {
191 label = "button4";
192 linux,code = <KEY_F4>;
193 press-threshold-microvolt = <1000000>;
194 };
195
196 button-enter {
197 label = "button5";
198 linux,code = <KEY_F5>;
199 press-threshold-microvolt = <500000>;
200 };
201 };
202
Simon Glasse96fa6c2018-12-10 10:37:34 -0700203 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600204 reg = <0 0>;
205 compatible = "google,cros-ec-sandbox";
206
207 /*
208 * This describes the flash memory within the EC. Note
209 * that the STM32L flash erases to 0, not 0xff.
210 */
211 flash {
212 image-pos = <0x08000000>;
213 size = <0x20000>;
214 erase-value = <0>;
215
216 /* Information for sandbox */
217 ro {
218 image-pos = <0>;
219 size = <0xf000>;
220 };
221 wp-ro {
222 image-pos = <0xf000>;
223 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700224 used = <0x884>;
225 compress = "lz4";
226 uncomp-size = <0xcf8>;
227 hash {
228 algo = "sha256";
229 value = [00 01 02 03 04 05 06 07
230 08 09 0a 0b 0c 0d 0e 0f
231 10 11 12 13 14 15 16 17
232 18 19 1a 1b 1c 1d 1e 1f];
233 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600234 };
235 rw {
236 image-pos = <0x10000>;
237 size = <0x10000>;
238 };
239 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300240
241 cros_ec_pwm: cros-ec-pwm {
242 compatible = "google,cros-ec-pwm";
243 #pwm-cells = <1>;
244 };
245
Simon Glasse6c5c942018-10-01 12:22:08 -0600246 };
247
Yannick Fertré23f965a2019-10-07 15:29:05 +0200248 dsi_host: dsi_host {
249 compatible = "sandbox,dsi-host";
250 };
251
Simon Glass2e7d35d2014-02-26 15:59:21 -0700252 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600253 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700254 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600255 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700256 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600257 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100258 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
259 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700260 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100261 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
262 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
263 <&gpio_b 7 GPIO_IN 3 2 1>,
264 <&gpio_b 8 GPIO_OUT 3 2 1>,
265 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100266 test3-gpios =
267 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
268 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
269 <&gpio_c 2 GPIO_OUT>,
270 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
271 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200272 <&gpio_c 5 GPIO_IN>,
273 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
274 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530275 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
276 test5-gpios = <&gpio_a 19>;
277
Simon Glassfb933d02021-10-23 17:26:04 -0600278 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200279 int8-value = /bits/ 8 <0x12>;
280 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700281 int-value = <1234>;
282 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200283 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200284 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600285 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700286 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600287 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200288 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530289
290 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
291 <&muxcontroller0 2>, <&muxcontroller0 3>,
292 <&muxcontroller1>;
293 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
294 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100295 display-timings {
296 timing0: 240x320 {
297 clock-frequency = <6500000>;
298 hactive = <240>;
299 vactive = <320>;
300 hfront-porch = <6>;
301 hback-porch = <7>;
302 hsync-len = <1>;
303 vback-porch = <5>;
304 vfront-porch = <8>;
305 vsync-len = <2>;
306 hsync-active = <1>;
307 vsync-active = <0>;
308 de-active = <1>;
309 pixelclk-active = <1>;
310 interlaced;
311 doublescan;
312 doubleclk;
313 };
314 timing1: 480x800 {
315 clock-frequency = <9000000>;
316 hactive = <480>;
317 vactive = <800>;
318 hfront-porch = <10>;
319 hback-porch = <59>;
320 hsync-len = <12>;
321 vback-porch = <15>;
322 vfront-porch = <17>;
323 vsync-len = <16>;
324 hsync-active = <0>;
325 vsync-active = <1>;
326 de-active = <0>;
327 pixelclk-active = <0>;
328 };
329 timing2: 800x480 {
330 clock-frequency = <33500000>;
331 hactive = <800>;
332 vactive = <480>;
333 hback-porch = <89>;
334 hfront-porch = <164>;
335 vback-porch = <23>;
336 vfront-porch = <10>;
337 hsync-len = <11>;
338 vsync-len = <13>;
339 };
340 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700341 };
342
343 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600344 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700345 compatible = "not,compatible";
346 };
347
348 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600349 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700350 };
351
Simon Glass5d9a88f2018-10-01 12:22:40 -0600352 backlight: backlight {
353 compatible = "pwm-backlight";
354 enable-gpios = <&gpio_a 1>;
355 power-supply = <&ldo_1>;
356 pwms = <&pwm 0 1000>;
357 default-brightness-level = <5>;
358 brightness-levels = <0 16 32 64 128 170 202 234 255>;
359 };
360
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200361 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200362 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200363 bind-test-child1 {
364 compatible = "sandbox,phy";
365 #phy-cells = <1>;
366 };
367
368 bind-test-child2 {
369 compatible = "simple-bus";
370 };
371 };
372
Simon Glass2e7d35d2014-02-26 15:59:21 -0700373 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600374 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700375 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600376 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700377 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530378
379 mux-controls = <&muxcontroller0 0>;
380 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700381 };
382
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200383 phy_provider0: gen_phy@0 {
384 compatible = "sandbox,phy";
385 #phy-cells = <1>;
386 };
387
388 phy_provider1: gen_phy@1 {
389 compatible = "sandbox,phy";
390 #phy-cells = <0>;
391 broken;
392 };
393
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200394 phy_provider2: gen_phy@2 {
395 compatible = "sandbox,phy";
396 #phy-cells = <0>;
397 };
398
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200399 gen_phy_user: gen_phy_user {
400 compatible = "simple-bus";
401 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
402 phy-names = "phy1", "phy2", "phy3";
403 };
404
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200405 gen_phy_user1: gen_phy_user1 {
406 compatible = "simple-bus";
407 phys = <&phy_provider0 0>, <&phy_provider2>;
408 phy-names = "phy1", "phy2";
409 };
410
Simon Glass2e7d35d2014-02-26 15:59:21 -0700411 some-bus {
412 #address-cells = <1>;
413 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600414 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600415 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600416 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700417 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600418 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700419 compatible = "denx,u-boot-fdt-test";
420 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600421 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700422 ping-add = <5>;
423 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600424 c-test@0 {
425 compatible = "denx,u-boot-fdt-test";
426 reg = <0>;
427 ping-expect = <6>;
428 ping-add = <6>;
429 };
430 c-test@1 {
431 compatible = "denx,u-boot-fdt-test";
432 reg = <1>;
433 ping-expect = <7>;
434 ping-add = <7>;
435 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700436 };
437
438 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600439 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600440 ping-expect = <6>;
441 ping-add = <6>;
442 compatible = "google,another-fdt-test";
443 };
444
445 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600446 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600447 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700448 ping-add = <6>;
449 compatible = "google,another-fdt-test";
450 };
451
Simon Glass9cc36a22015-01-25 08:27:05 -0700452 f-test {
453 compatible = "denx,u-boot-fdt-test";
454 };
455
456 g-test {
457 compatible = "denx,u-boot-fdt-test";
458 };
459
Bin Meng2786cd72018-10-10 22:07:01 -0700460 h-test {
461 compatible = "denx,u-boot-fdt-test1";
462 };
463
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200464 i-test {
465 compatible = "mediatek,u-boot-fdt-test";
466 #address-cells = <1>;
467 #size-cells = <0>;
468
469 subnode@0 {
470 reg = <0>;
471 };
472
473 subnode@1 {
474 reg = <1>;
475 };
476
477 subnode@2 {
478 reg = <2>;
479 };
480 };
481
Simon Glassdc12ebb2019-12-29 21:19:25 -0700482 devres-test {
483 compatible = "denx,u-boot-devres-test";
484 };
485
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530486 another-test {
487 reg = <0 2>;
488 compatible = "denx,u-boot-fdt-test";
489 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
490 test5-gpios = <&gpio_a 19>;
491 };
492
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100493 mmio-bus@0 {
494 #address-cells = <1>;
495 #size-cells = <1>;
496 compatible = "denx,u-boot-test-bus";
497 dma-ranges = <0x10000000 0x00000000 0x00040000>;
498
499 subnode@0 {
500 compatible = "denx,u-boot-fdt-test";
501 };
502 };
503
504 mmio-bus@1 {
505 #address-cells = <1>;
506 #size-cells = <1>;
507 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100508
509 subnode@0 {
510 compatible = "denx,u-boot-fdt-test";
511 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100512 };
513
Simon Glass0f7b1112020-07-07 13:12:06 -0600514 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600515 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600516 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600517 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600518 child {
519 compatible = "denx,u-boot-acpi-test";
520 };
Simon Glassf50cc952020-04-08 16:57:34 -0600521 };
522
Simon Glass0f7b1112020-07-07 13:12:06 -0600523 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600524 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600525 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600526 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600527 };
528
Patrice Chotardee87a092017-09-04 14:55:57 +0200529 clocks {
530 clk_fixed: clk-fixed {
531 compatible = "fixed-clock";
532 #clock-cells = <0>;
533 clock-frequency = <1234>;
534 };
Anup Patelb630d572019-02-25 08:14:55 +0000535
536 clk_fixed_factor: clk-fixed-factor {
537 compatible = "fixed-factor-clock";
538 #clock-cells = <0>;
539 clock-div = <3>;
540 clock-mult = <2>;
541 clocks = <&clk_fixed>;
542 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200543
544 osc {
545 compatible = "fixed-clock";
546 #clock-cells = <0>;
547 clock-frequency = <20000000>;
548 };
Stephen Warren135aa952016-06-17 09:44:00 -0600549 };
550
551 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600552 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600553 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200554 assigned-clocks = <&clk_sandbox 3>;
555 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600556 };
557
558 clk-test {
559 compatible = "sandbox,clk-test";
560 clocks = <&clk_fixed>,
561 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200562 <&clk_sandbox 0>,
563 <&clk_sandbox 3>,
564 <&clk_sandbox 2>;
565 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600566 };
567
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200568 ccf: clk-ccf {
569 compatible = "sandbox,clk-ccf";
570 };
571
Simon Glass42b7f422021-12-04 08:56:31 -0700572 efi-media {
573 compatible = "sandbox,efi-media";
574 };
575
Simon Glass171e9912015-05-22 15:42:15 -0600576 eth@10002000 {
577 compatible = "sandbox,eth";
578 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600579 };
580
581 eth_5: eth@10003000 {
582 compatible = "sandbox,eth";
583 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400584 nvmem-cells = <&eth5_addr>;
585 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600586 };
587
Bin Meng71d79712015-08-27 22:25:53 -0700588 eth_3: sbe5 {
589 compatible = "sandbox,eth";
590 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400591 nvmem-cells = <&eth3_addr>;
592 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700593 };
594
Simon Glass171e9912015-05-22 15:42:15 -0600595 eth@10004000 {
596 compatible = "sandbox,eth";
597 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600598 };
599
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200600 phy_eth0: phy-test-eth {
601 compatible = "sandbox,eth";
602 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400603 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200604 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200605 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200606 };
607
Claudiu Manoilff98da02021-03-14 20:14:57 +0800608 dsa_eth0: dsa-test-eth {
609 compatible = "sandbox,eth";
610 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400611 nvmem-cells = <&eth4_addr>;
612 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800613 };
614
615 dsa-test {
616 compatible = "sandbox,dsa";
617
618 ports {
619 #address-cells = <1>;
620 #size-cells = <0>;
621 swp_0: port@0 {
622 reg = <0>;
623 label = "lan0";
624 phy-mode = "rgmii-rxid";
625
626 fixed-link {
627 speed = <100>;
628 full-duplex;
629 };
630 };
631
632 swp_1: port@1 {
633 reg = <1>;
634 label = "lan1";
635 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800636 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800637 };
638
639 port@2 {
640 reg = <2>;
641 ethernet = <&dsa_eth0>;
642
643 fixed-link {
644 speed = <1000>;
645 full-duplex;
646 };
647 };
648 };
649 };
650
Rajan Vaja31b82172018-09-19 03:43:46 -0700651 firmware {
652 sandbox_firmware: sandbox-firmware {
653 compatible = "sandbox,firmware";
654 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200655
Etienne Carriere41d62e22022-02-21 09:22:39 +0100656 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200657 compatible = "sandbox,scmi-agent";
658 #address-cells = <1>;
659 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200660
Etienne Carriere41d62e22022-02-21 09:22:39 +0100661 protocol@10 {
662 reg = <0x10>;
663 };
664
665 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200666 reg = <0x14>;
667 #clock-cells = <1>;
668 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200669
Etienne Carriere41d62e22022-02-21 09:22:39 +0100670 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200671 reg = <0x16>;
672 #reset-cells = <1>;
673 };
Etienne Carriere01242182021-03-08 22:38:07 +0100674
675 protocol@17 {
676 reg = <0x17>;
677
678 regulators {
679 #address-cells = <1>;
680 #size-cells = <0>;
681
Etienne Carriere41d62e22022-02-21 09:22:39 +0100682 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100683 reg = <0>;
684 regulator-name = "sandbox-voltd0";
685 regulator-min-microvolt = <1100000>;
686 regulator-max-microvolt = <3300000>;
687 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100688 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100689 reg = <0x1>;
690 regulator-name = "sandbox-voltd1";
691 regulator-min-microvolt = <1800000>;
692 };
693 };
694 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200695 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700696 };
697
Alexander Dahl1323d082022-09-30 14:04:30 +0200698 fpga {
699 compatible = "sandbox,fpga";
700 };
701
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100702 pinctrl-gpio {
703 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700704
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100705 gpio_a: base-gpios {
706 compatible = "sandbox,gpio";
707 gpio-controller;
708 #gpio-cells = <1>;
709 gpio-bank-name = "a";
710 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200711 hog_input_active_low {
712 gpio-hog;
713 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200714 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200715 };
716 hog_input_active_high {
717 gpio-hog;
718 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200719 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200720 };
721 hog_output_low {
722 gpio-hog;
723 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200724 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200725 };
726 hog_output_high {
727 gpio-hog;
728 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200729 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200730 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100731 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600732
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100733 gpio_b: extra-gpios {
734 compatible = "sandbox,gpio";
735 gpio-controller;
736 #gpio-cells = <5>;
737 gpio-bank-name = "b";
738 sandbox,gpio-count = <10>;
739 };
740
741 gpio_c: pinmux-gpios {
742 compatible = "sandbox,gpio";
743 gpio-controller;
744 #gpio-cells = <2>;
745 gpio-bank-name = "c";
746 sandbox,gpio-count = <10>;
747 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100748 };
749
Simon Glassecc2ed52014-12-10 08:55:55 -0700750 i2c@0 {
751 #address-cells = <1>;
752 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600753 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700754 compatible = "sandbox,i2c";
755 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200756 pinctrl-names = "default";
757 pinctrl-0 = <&pinmux_i2c0_pins>;
758
Simon Glassecc2ed52014-12-10 08:55:55 -0700759 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400760 #address-cells = <1>;
761 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700762 reg = <0x2c>;
763 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700764 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200765 partitions {
766 compatible = "fixed-partitions";
767 #address-cells = <1>;
768 #size-cells = <1>;
769 bootcount_i2c: bootcount@10 {
770 reg = <10 2>;
771 };
772 };
Sean Anderson472caa62022-05-05 13:11:42 -0400773
774 eth3_addr: mac-address@24 {
775 reg = <24 6>;
776 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700777 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200778
Simon Glass52d3bc52015-05-22 15:42:17 -0600779 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400780 #address-cells = <1>;
781 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600782 reg = <0x43>;
783 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700784 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400785
786 eth4_addr: mac-address@40 {
787 reg = <0x40 6>;
788 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600789 };
790
791 rtc_1: rtc@61 {
792 reg = <0x61>;
793 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700794 sandbox,emul = <&emul1>;
795 };
796
797 i2c_emul: emul {
798 reg = <0xff>;
799 compatible = "sandbox,i2c-emul-parent";
800 emul_eeprom: emul-eeprom {
801 compatible = "sandbox,i2c-eeprom";
802 sandbox,filename = "i2c.bin";
803 sandbox,size = <256>;
804 };
805 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700806 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700807 };
808 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700809 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600810 };
811 };
812
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200813 sandbox_pmic: sandbox_pmic {
814 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700815 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200816 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200817
818 mc34708: pmic@41 {
819 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700820 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200821 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700822 };
823
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100824 bootcount@0 {
825 compatible = "u-boot,bootcount-rtc";
826 rtc = <&rtc_1>;
827 offset = <0x13>;
828 };
829
Michal Simekf692b472020-05-28 11:48:55 +0200830 bootcount {
831 compatible = "u-boot,bootcount-i2c-eeprom";
832 i2c-eeprom = <&bootcount_i2c>;
833 };
834
Nandor Hanc50b21b2021-06-10 15:40:38 +0300835 bootcount_4@0 {
836 compatible = "u-boot,bootcount-syscon";
837 syscon = <&syscon0>;
838 reg = <0x0 0x04>, <0x0 0x04>;
839 reg-names = "syscon_reg", "offset";
840 };
841
842 bootcount_2@0 {
843 compatible = "u-boot,bootcount-syscon";
844 syscon = <&syscon0>;
845 reg = <0x0 0x04>, <0x0 0x02> ;
846 reg-names = "syscon_reg", "offset";
847 };
848
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100849 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100850 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100851 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100852 vdd-supply = <&buck2>;
853 vss-microvolts = <0>;
854 };
855
Mark Kettenisfb574622021-10-23 16:58:02 +0200856 iommu: iommu@0 {
857 compatible = "sandbox,iommu";
858 #iommu-cells = <0>;
859 };
860
Simon Glass02554352020-02-06 09:55:00 -0700861 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700862 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700863 interrupt-controller;
864 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700865 };
866
Simon Glass3c97c4f2016-01-18 19:52:26 -0700867 lcd {
868 u-boot,dm-pre-reloc;
869 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200870 pinctrl-names = "default";
871 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700872 xres = <1366>;
873 yres = <768>;
874 };
875
Simon Glass3c43fba2015-07-06 12:54:34 -0600876 leds {
877 compatible = "gpio-leds";
878
879 iracibble {
880 gpios = <&gpio_a 1 0>;
881 label = "sandbox:red";
882 };
883
884 martinet {
885 gpios = <&gpio_a 2 0>;
886 label = "sandbox:green";
887 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200888
889 default_on {
890 gpios = <&gpio_a 5 0>;
891 label = "sandbox:default_on";
892 default-state = "on";
893 };
894
895 default_off {
896 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400897 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200898 default-state = "off";
899 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600900 };
901
Paul Doelle1fc45d62022-07-04 09:00:25 +0000902 wdt-gpio-toggle {
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200903 gpios = <&gpio_a 7 0>;
904 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200905 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000906 hw_algo = "toggle";
907 always-running;
908 };
909
910 wdt-gpio-level {
911 gpios = <&gpio_a 7 0>;
912 compatible = "linux,wdt-gpio";
913 hw_margin_ms = <100>;
914 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200915 always-running;
916 };
917
Stephen Warren8961b522016-05-16 17:41:37 -0600918 mbox: mbox {
919 compatible = "sandbox,mbox";
920 #mbox-cells = <1>;
921 };
922
923 mbox-test {
924 compatible = "sandbox,mbox-test";
925 mboxes = <&mbox 100>, <&mbox 1>;
926 mbox-names = "other", "test";
927 };
928
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900929 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200930 #address-cells = <1>;
931 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400932 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200933 cpu1: cpu@1 {
934 device_type = "cpu";
935 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400936 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900937 compatible = "sandbox,cpu_sandbox";
938 u-boot,dm-pre-reloc;
939 };
Mario Sixfa44b532018-08-06 10:23:44 +0200940
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200941 cpu2: cpu@2 {
942 device_type = "cpu";
943 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900944 compatible = "sandbox,cpu_sandbox";
945 u-boot,dm-pre-reloc;
946 };
Mario Sixfa44b532018-08-06 10:23:44 +0200947
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200948 cpu3: cpu@3 {
949 device_type = "cpu";
950 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900951 compatible = "sandbox,cpu_sandbox";
952 u-boot,dm-pre-reloc;
953 };
Mario Sixfa44b532018-08-06 10:23:44 +0200954 };
955
Dave Gerlach21e3c212020-07-15 23:39:58 -0500956 chipid: chipid {
957 compatible = "sandbox,soc";
958 };
959
Simon Glasse96fa6c2018-12-10 10:37:34 -0700960 i2s: i2s {
961 compatible = "sandbox,i2s";
962 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700963 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700964 };
965
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200966 nop-test_0 {
967 compatible = "sandbox,nop_sandbox1";
968 nop-test_1 {
969 compatible = "sandbox,nop_sandbox2";
970 bind = "True";
971 };
972 nop-test_2 {
973 compatible = "sandbox,nop_sandbox2";
974 bind = "False";
975 };
976 };
977
Roger Quadros2c120372022-10-20 16:30:46 +0300978 memory-controller {
979 compatible = "sandbox,memory";
980 };
981
Mario Six004e67c2018-07-31 14:24:14 +0200982 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -0400983 #address-cells = <1>;
984 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +0200985 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -0400986
987 eth5_addr: mac-address@10 {
988 reg = <0x10 6>;
989 };
Mario Six004e67c2018-07-31 14:24:14 +0200990 };
991
Simon Glasse48eeb92017-04-23 20:02:07 -0600992 mmc2 {
993 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -0600994 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -0600995 };
996
Simon Glassfb1451b2022-04-24 23:31:24 -0600997 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -0600998 mmc1 {
999 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001000 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001001 };
1002
Simon Glassfb1451b2022-04-24 23:31:24 -06001003 /* This is used for the fastboot tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001004 mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001005 compatible = "sandbox,mmc";
1006 };
1007
Simon Glass77bec9e2022-10-20 18:23:20 -06001008 /* This is used for VBE VPL tests */
1009 mmc3 {
1010 status = "disabled";
1011 compatible = "sandbox,mmc";
1012 filename = "image.bin";
1013 non-removable;
1014 };
1015
Simon Glassb45c8332019-02-16 20:24:50 -07001016 pch {
1017 compatible = "sandbox,pch";
1018 };
1019
Tom Rini42c64d12020-02-11 12:41:23 -05001020 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001021 compatible = "sandbox,pci";
1022 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001023 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001024 #address-cells = <3>;
1025 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001026 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001027 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001028 pci@0,0 {
1029 compatible = "pci-generic";
1030 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001031 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001032 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001033 pci@1,0 {
1034 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001035 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1036 reg = <0x02000814 0 0 0 0
1037 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001038 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001039 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001040 p2sb-pci@2,0 {
1041 compatible = "sandbox,p2sb";
1042 reg = <0x02001010 0 0 0 0>;
1043 sandbox,emul = <&p2sb_emul>;
1044
1045 adder {
1046 intel,p2sb-port-id = <3>;
1047 compatible = "sandbox,adder";
1048 };
1049 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001050 pci@1e,0 {
1051 compatible = "sandbox,pmc";
1052 reg = <0xf000 0 0 0 0>;
1053 sandbox,emul = <&pmc_emul1e>;
1054 acpi-base = <0x400>;
1055 gpe0-dwx-mask = <0xf>;
1056 gpe0-dwx-shift-base = <4>;
1057 gpe0-dw = <6 7 9>;
1058 gpe0-sts = <0x20>;
1059 gpe0-en = <0x30>;
1060 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001061 pci@1f,0 {
1062 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001063 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1064 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001065 sandbox,emul = <&swap_case_emul0_1f>;
1066 };
1067 };
1068
1069 pci-emul0 {
1070 compatible = "sandbox,pci-emul-parent";
1071 swap_case_emul0_0: emul0@0,0 {
1072 compatible = "sandbox,swap-case";
1073 };
1074 swap_case_emul0_1: emul0@1,0 {
1075 compatible = "sandbox,swap-case";
1076 use-ea;
1077 };
1078 swap_case_emul0_1f: emul0@1f,0 {
1079 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001080 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001081 p2sb_emul: emul@2,0 {
1082 compatible = "sandbox,p2sb-emul";
1083 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001084 pmc_emul1e: emul@1e,0 {
1085 compatible = "sandbox,pmc-emul";
1086 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001087 };
1088
Tom Rini42c64d12020-02-11 12:41:23 -05001089 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001090 compatible = "sandbox,pci";
1091 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001092 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001093 #address-cells = <3>;
1094 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001095 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001096 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001097 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001098 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001099 0x0c 0x00 0x1234 0x5678
1100 0x10 0x00 0x1234 0x5678>;
1101 pci@10,0 {
1102 reg = <0x8000 0 0 0 0>;
1103 };
Bin Mengdee4d752018-08-03 01:14:41 -07001104 };
1105
Tom Rini42c64d12020-02-11 12:41:23 -05001106 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001107 compatible = "sandbox,pci";
1108 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001109 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001110 #address-cells = <3>;
1111 #size-cells = <2>;
1112 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1113 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1114 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1115 pci@1f,0 {
1116 compatible = "pci-generic";
1117 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001118 sandbox,emul = <&swap_case_emul2_1f>;
1119 };
1120 };
1121
1122 pci-emul2 {
1123 compatible = "sandbox,pci-emul-parent";
1124 swap_case_emul2_1f: emul2@1f,0 {
1125 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001126 };
1127 };
1128
Ramon Friedbb413332019-04-27 11:15:23 +03001129 pci_ep: pci_ep {
1130 compatible = "sandbox,pci_ep";
1131 };
1132
Simon Glass98561572017-04-23 20:10:44 -06001133 probing {
1134 compatible = "simple-bus";
1135 test1 {
1136 compatible = "denx,u-boot-probe-test";
1137 };
1138
1139 test2 {
1140 compatible = "denx,u-boot-probe-test";
1141 };
1142
1143 test3 {
1144 compatible = "denx,u-boot-probe-test";
1145 };
1146
1147 test4 {
1148 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001149 first-syscon = <&syscon0>;
1150 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001151 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001152 };
1153 };
1154
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001155 pwrdom: power-domain {
1156 compatible = "sandbox,power-domain";
1157 #power-domain-cells = <1>;
1158 };
1159
1160 power-domain-test {
1161 compatible = "sandbox,power-domain-test";
1162 power-domains = <&pwrdom 2>;
1163 };
1164
Simon Glass5d9a88f2018-10-01 12:22:40 -06001165 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001166 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001167 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001168 pinctrl-names = "default";
1169 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001170 };
1171
1172 pwm2 {
1173 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001174 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001175 };
1176
Simon Glass64ce0ca2015-07-06 12:54:31 -06001177 ram {
1178 compatible = "sandbox,ram";
1179 };
1180
Simon Glass5010d982015-07-06 12:54:29 -06001181 reset@0 {
1182 compatible = "sandbox,warm-reset";
Michal Suchanek5b2f49c2022-10-10 20:29:39 +02001183 u-boot,dm-pre-proper;
Simon Glass5010d982015-07-06 12:54:29 -06001184 };
1185
1186 reset@1 {
1187 compatible = "sandbox,reset";
Michal Suchanek5b2f49c2022-10-10 20:29:39 +02001188 u-boot,dm-pre-proper;
Simon Glass5010d982015-07-06 12:54:29 -06001189 };
1190
Stephen Warren4581b712016-06-17 09:43:59 -06001191 resetc: reset-ctl {
1192 compatible = "sandbox,reset-ctl";
1193 #reset-cells = <1>;
1194 };
1195
1196 reset-ctl-test {
1197 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001198 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1199 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001200 };
1201
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301202 rng {
1203 compatible = "sandbox,sandbox-rng";
1204 };
1205
Nishanth Menon52159402015-09-17 15:42:41 -05001206 rproc_1: rproc@1 {
1207 compatible = "sandbox,test-processor";
1208 remoteproc-name = "remoteproc-test-dev1";
1209 };
1210
1211 rproc_2: rproc@2 {
1212 compatible = "sandbox,test-processor";
1213 internal-memory-mapped;
1214 remoteproc-name = "remoteproc-test-dev2";
1215 };
1216
Simon Glass5d9a88f2018-10-01 12:22:40 -06001217 panel {
1218 compatible = "simple-panel";
1219 backlight = <&backlight 0 100>;
1220 };
1221
Simon Glass22c80d52022-09-21 16:21:47 +02001222 scsi {
1223 compatible = "sandbox,scsi";
1224 sandbox,filepath = "scsi.img";
1225 };
1226
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001227 smem@0 {
1228 compatible = "sandbox,smem";
1229 };
1230
Simon Glassd4901892018-12-10 10:37:36 -07001231 sound {
1232 compatible = "sandbox,sound";
1233 cpu {
1234 sound-dai = <&i2s 0>;
1235 };
1236
1237 codec {
1238 sound-dai = <&audio 0>;
1239 };
1240 };
1241
Simon Glass0ae0cb72014-10-13 23:42:11 -06001242 spi@0 {
1243 #address-cells = <1>;
1244 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001245 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001246 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001247 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001248 pinctrl-names = "default";
1249 pinctrl-0 = <&pinmux_spi0_pins>;
1250
Simon Glass0ae0cb72014-10-13 23:42:11 -06001251 spi.bin@0 {
1252 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001253 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001254 spi-max-frequency = <40000000>;
1255 sandbox,filename = "spi.bin";
1256 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001257 spi.bin@1 {
1258 reg = <1>;
1259 compatible = "spansion,m25p16", "jedec,spi-nor";
1260 spi-max-frequency = <50000000>;
1261 sandbox,filename = "spi.bin";
1262 spi-cpol;
1263 spi-cpha;
1264 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001265 };
1266
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001267 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001268 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001269 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001270 };
1271
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001272 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001273 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001274 reg = <0x20 5
1275 0x28 6
1276 0x30 7
1277 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001278 };
1279
Patrick Delaunaya442e612019-03-07 09:57:13 +01001280 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001281 compatible = "simple-mfd", "syscon";
1282 reg = <0x40 5
1283 0x48 6
1284 0x50 7
1285 0x58 8>;
1286 };
1287
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301288 syscon3: syscon@3 {
1289 compatible = "simple-mfd", "syscon";
1290 reg = <0x000100 0x10>;
1291
1292 muxcontroller0: a-mux-controller {
1293 compatible = "mmio-mux";
1294 #mux-control-cells = <1>;
1295
1296 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1297 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1298 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1299 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1300 u-boot,mux-autoprobe;
1301 };
1302 };
1303
1304 muxcontroller1: emul-mux-controller {
1305 compatible = "mux-emul";
1306 #mux-control-cells = <0>;
1307 u-boot,mux-autoprobe;
1308 idle-state = <0xabcd>;
1309 };
1310
Simon Glass93f44e82020-12-16 21:20:27 -07001311 testfdtm0 {
1312 compatible = "denx,u-boot-fdtm-test";
1313 };
1314
1315 testfdtm1: testfdtm1 {
1316 compatible = "denx,u-boot-fdtm-test";
1317 };
1318
1319 testfdtm2 {
1320 compatible = "denx,u-boot-fdtm-test";
1321 };
1322
Sean Anderson7616e362020-09-28 10:52:23 -04001323 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001324 compatible = "sandbox,timer";
1325 clock-frequency = <1000000>;
1326 };
1327
Sean Anderson7616e362020-09-28 10:52:23 -04001328 timer@1 {
1329 compatible = "sandbox,timer";
1330 sandbox,timebase-frequency-fallback;
1331 };
1332
Miquel Raynalb91ad162018-05-15 11:57:27 +02001333 tpm2 {
1334 compatible = "sandbox,tpm2";
1335 };
1336
Simon Glass171e9912015-05-22 15:42:15 -06001337 uart0: serial {
1338 compatible = "sandbox,serial";
1339 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001340 pinctrl-names = "default";
1341 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001342 };
1343
Simon Glasse00cb222015-03-25 12:23:05 -06001344 usb_0: usb@0 {
1345 compatible = "sandbox,usb";
1346 status = "disabled";
1347 hub {
1348 compatible = "sandbox,usb-hub";
1349 #address-cells = <1>;
1350 #size-cells = <0>;
1351 flash-stick {
1352 reg = <0>;
1353 compatible = "sandbox,usb-flash";
1354 };
1355 };
1356 };
1357
1358 usb_1: usb@1 {
1359 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001360 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001361 hub {
1362 compatible = "usb-hub";
1363 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001364 #address-cells = <1>;
1365 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001366 hub-emul {
1367 compatible = "sandbox,usb-hub";
1368 #address-cells = <1>;
1369 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001370 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001371 reg = <0>;
1372 compatible = "sandbox,usb-flash";
1373 sandbox,filepath = "testflash.bin";
1374 };
1375
Simon Glass431cbd62015-11-08 23:48:01 -07001376 flash-stick@1 {
1377 reg = <1>;
1378 compatible = "sandbox,usb-flash";
1379 sandbox,filepath = "testflash1.bin";
1380 };
1381
1382 flash-stick@2 {
1383 reg = <2>;
1384 compatible = "sandbox,usb-flash";
1385 sandbox,filepath = "testflash2.bin";
1386 };
1387
Simon Glassbff1a712015-11-08 23:48:08 -07001388 keyb@3 {
1389 reg = <3>;
1390 compatible = "sandbox,usb-keyb";
1391 };
1392
Simon Glasse00cb222015-03-25 12:23:05 -06001393 };
Michael Wallec03b7612020-06-02 01:47:07 +02001394
1395 usbstor@1 {
1396 reg = <1>;
1397 };
1398 usbstor@3 {
1399 reg = <3>;
1400 };
Simon Glasse00cb222015-03-25 12:23:05 -06001401 };
1402 };
1403
1404 usb_2: usb@2 {
1405 compatible = "sandbox,usb";
1406 status = "disabled";
1407 };
1408
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001409 spmi: spmi@0 {
1410 compatible = "sandbox,spmi";
1411 #address-cells = <0x1>;
1412 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001413 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001414 pm8916@0 {
1415 compatible = "qcom,spmi-pmic";
1416 reg = <0x0 0x1>;
1417 #address-cells = <0x1>;
1418 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001419 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001420
1421 spmi_gpios: gpios@c000 {
1422 compatible = "qcom,pm8916-gpio";
1423 reg = <0xc000 0x400>;
1424 gpio-controller;
1425 gpio-count = <4>;
1426 #gpio-cells = <2>;
1427 gpio-bank-name="spmi";
1428 };
1429 };
1430 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001431
1432 wdt0: wdt@0 {
1433 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001434 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001435 };
Rob Clarkf2006802018-01-10 11:33:30 +01001436
Mario Six957983e2018-08-09 14:51:19 +02001437 axi: axi@0 {
1438 compatible = "sandbox,axi";
1439 #address-cells = <0x1>;
1440 #size-cells = <0x1>;
1441 store@0 {
1442 compatible = "sandbox,sandbox_store";
1443 reg = <0x0 0x400>;
1444 };
1445 };
1446
Rob Clarkf2006802018-01-10 11:33:30 +01001447 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001448 #address-cells = <1>;
1449 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001450 setting = "sunrise ohoka";
1451 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001452 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001453 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001454 chosen-test {
1455 compatible = "denx,u-boot-fdt-test";
1456 reg = <9 1>;
1457 };
1458 };
Mario Sixe8d52912018-03-12 14:53:33 +01001459
1460 translation-test@8000 {
1461 compatible = "simple-bus";
1462 reg = <0x8000 0x4000>;
1463
1464 #address-cells = <0x2>;
1465 #size-cells = <0x1>;
1466
1467 ranges = <0 0x0 0x8000 0x1000
1468 1 0x100 0x9000 0x1000
1469 2 0x200 0xA000 0x1000
1470 3 0x300 0xB000 0x1000
1471 >;
1472
Fabien Dessenne641067f2019-05-31 15:11:30 +02001473 dma-ranges = <0 0x000 0x10000000 0x1000
1474 1 0x100 0x20000000 0x1000
1475 >;
1476
Mario Sixe8d52912018-03-12 14:53:33 +01001477 dev@0,0 {
1478 compatible = "denx,u-boot-fdt-dummy";
1479 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001480 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001481 };
1482
1483 dev@1,100 {
1484 compatible = "denx,u-boot-fdt-dummy";
1485 reg = <1 0x100 0x1000>;
1486
1487 };
1488
1489 dev@2,200 {
1490 compatible = "denx,u-boot-fdt-dummy";
1491 reg = <2 0x200 0x1000>;
1492 };
1493
1494
1495 noxlatebus@3,300 {
1496 compatible = "simple-bus";
1497 reg = <3 0x300 0x1000>;
1498
1499 #address-cells = <0x1>;
1500 #size-cells = <0x0>;
1501
1502 dev@42 {
1503 compatible = "denx,u-boot-fdt-dummy";
1504 reg = <0x42>;
1505 };
1506 };
1507 };
Mario Six4eea5312018-09-27 09:19:31 +02001508
1509 osd {
1510 compatible = "sandbox,sandbox_osd";
1511 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001512
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001513 sandbox_tee {
1514 compatible = "sandbox,tee";
1515 };
Bin Meng4f89d492018-10-15 02:21:26 -07001516
1517 sandbox_virtio1 {
1518 compatible = "sandbox,virtio1";
1519 };
1520
1521 sandbox_virtio2 {
1522 compatible = "sandbox,virtio2";
1523 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001524
Etienne Carriere87d4f272020-09-09 18:44:05 +02001525 sandbox_scmi {
1526 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001527 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001528 resets = <&reset_scmi 3>;
1529 regul0-supply = <&regul0_scmi>;
1530 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001531 };
1532
Patrice Chotardf41a8242018-10-24 14:10:23 +02001533 pinctrl {
1534 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001535
Sean Anderson7f0f1802020-09-14 11:01:57 -04001536 pinctrl-names = "default", "alternate";
1537 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1538 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001539
Sean Anderson7f0f1802020-09-14 11:01:57 -04001540 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001541 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001542 pins = "P5";
1543 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001544 bias-pull-up;
1545 input-disable;
1546 };
1547 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001548 pins = "P6";
1549 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001550 output-high;
1551 drive-open-drain;
1552 };
1553 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001554 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001555 bias-pull-down;
1556 input-enable;
1557 };
1558 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001559 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001560 bias-disable;
1561 };
1562 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001563
1564 pinctrl_i2c: i2c {
1565 groups {
1566 groups = "I2C_UART";
1567 function = "I2C";
1568 };
1569
1570 pins {
1571 pins = "P0", "P1";
1572 drive-open-drain;
1573 };
1574 };
1575
1576 pinctrl_i2s: i2s {
1577 groups = "SPI_I2S";
1578 function = "I2S";
1579 };
1580
1581 pinctrl_spi: spi {
1582 groups = "SPI_I2S";
1583 function = "SPI";
1584
1585 cs {
1586 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1587 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1588 };
1589 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001590 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001591
Dario Binacchi55322622021-04-11 09:39:50 +02001592 pinctrl-single-no-width {
1593 compatible = "pinctrl-single";
1594 reg = <0x0000 0x238>;
1595 #pinctrl-cells = <1>;
1596 pinctrl-single,function-mask = <0x7f>;
1597 };
1598
1599 pinctrl-single-pins {
1600 compatible = "pinctrl-single";
1601 reg = <0x0000 0x238>;
1602 #pinctrl-cells = <1>;
1603 pinctrl-single,register-width = <32>;
1604 pinctrl-single,function-mask = <0x7f>;
1605
1606 pinmux_pwm_pins: pinmux_pwm_pins {
1607 pinctrl-single,pins = < 0x48 0x06 >;
1608 };
1609
1610 pinmux_spi0_pins: pinmux_spi0_pins {
1611 pinctrl-single,pins = <
1612 0x190 0x0c
1613 0x194 0x0c
1614 0x198 0x23
1615 0x19c 0x0c
1616 >;
1617 };
1618
1619 pinmux_uart0_pins: pinmux_uart0_pins {
1620 pinctrl-single,pins = <
1621 0x70 0x30
1622 0x74 0x00
1623 >;
1624 };
1625 };
1626
1627 pinctrl-single-bits {
1628 compatible = "pinctrl-single";
1629 reg = <0x0000 0x50>;
1630 #pinctrl-cells = <2>;
1631 pinctrl-single,bit-per-mux;
1632 pinctrl-single,register-width = <32>;
1633 pinctrl-single,function-mask = <0xf>;
1634
1635 pinmux_i2c0_pins: pinmux_i2c0_pins {
1636 pinctrl-single,bits = <
1637 0x10 0x00002200 0x0000ff00
1638 >;
1639 };
1640
1641 pinmux_lcd_pins: pinmux_lcd_pins {
1642 pinctrl-single,bits = <
1643 0x40 0x22222200 0xffffff00
1644 0x44 0x22222222 0xffffffff
1645 0x48 0x00000022 0x000000ff
1646 0x48 0x02000000 0x0f000000
1647 0x4c 0x02000022 0x0f0000ff
1648 >;
1649 };
1650 };
1651
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001652 hwspinlock@0 {
1653 compatible = "sandbox,hwspinlock";
1654 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001655
1656 dma: dma {
1657 compatible = "sandbox,dma";
1658 #dma-cells = <1>;
1659
1660 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1661 dma-names = "m2m", "tx0", "rx0";
1662 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001663
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001664 /*
1665 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1666 * end of the test. If parent mdio is removed first, clean-up of the
1667 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1668 * active at the end of the test. That it turn doesn't allow the mdio
1669 * class to be destroyed, triggering an error.
1670 */
1671 mdio-mux-test {
1672 compatible = "sandbox,mdio-mux";
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675 mdio-parent-bus = <&mdio>;
1676
1677 mdio-ch-test@0 {
1678 reg = <0>;
1679 };
1680 mdio-ch-test@1 {
1681 reg = <1>;
1682 };
1683 };
1684
1685 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001686 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001687 #address-cells = <1>;
1688 #size-cells = <0>;
1689
1690 ethphy1: ethernet-phy@1 {
1691 reg = <1>;
1692 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001693 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001694
1695 pm-bus-test {
1696 compatible = "simple-pm-bus";
1697 clocks = <&clk_sandbox 4>;
1698 power-domains = <&pwrdom 1>;
1699 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001700
1701 resetc2: syscon-reset {
1702 compatible = "syscon-reset";
1703 #reset-cells = <1>;
1704 regmap = <&syscon0>;
1705 offset = <1>;
1706 mask = <0x27FFFFFF>;
1707 assert-high = <0>;
1708 };
1709
1710 syscon-reset-test {
1711 compatible = "sandbox,misc_sandbox";
1712 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1713 reset-names = "valid", "no_mask", "out_of_range";
1714 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301715
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001716 sysinfo {
1717 compatible = "sandbox,sysinfo-sandbox";
1718 };
1719
Sean Anderson1cbfed82021-04-20 10:50:58 -04001720 sysinfo-gpio {
1721 compatible = "gpio-sysinfo";
1722 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1723 revisions = <19>, <5>;
1724 names = "rev_a", "foo";
1725 };
1726
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301727 some_regmapped-bus {
1728 #address-cells = <0x1>;
1729 #size-cells = <0x1>;
1730
1731 ranges = <0x0 0x0 0x10>;
1732 compatible = "simple-bus";
1733
1734 regmap-test_0 {
1735 reg = <0 0x10>;
1736 compatible = "sandbox,regmap_test";
1737 };
1738 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001739
1740 thermal {
1741 compatible = "sandbox,thermal";
1742 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001743};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001744
1745#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001746#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001747
1748#ifdef CONFIG_SANDBOX_VPL
1749#include "sandbox_vpl.dtsi"
1750#endif