blob: 716e8c718565a409fe4dbbc079fd6700e7c68c98 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Bin Mengdee4d752018-08-03 01:14:41 -070042 pci0 = &pci0;
43 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070044 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020045 remoteproc0 = &rproc_1;
46 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060047 rtc0 = &rtc_0;
48 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060049 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020050 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070051 testbus3 = "/some-bus";
52 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070053 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070054 testfdt3 = "/b-test";
55 testfdt5 = "/some-bus/c-test@5";
56 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070057 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020058 fdt-dummy0 = "/translation-test@8000/dev@0,0";
59 fdt-dummy1 = "/translation-test@8000/dev@1,100";
60 fdt-dummy2 = "/translation-test@8000/dev@2,200";
61 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060062 usb0 = &usb_0;
63 usb1 = &usb_1;
64 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020065 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020066 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060067 };
68
Simon Glass8de98962022-10-20 18:23:15 -060069 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020070 };
71
Rasmus Villemoes8c728422021-04-21 11:06:55 +020072 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060073 testing-bool;
74 testing-int = <123>;
75 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020076 environment {
77 from_fdt = "yes";
78 fdt_env_path = "";
79 };
80 };
81
Simon Glassfb1451b2022-04-24 23:31:24 -060082 bootstd {
Simon Glassa56f6632022-10-20 18:23:14 -060083 u-boot,dm-vpl;
Simon Glassfb1451b2022-04-24 23:31:24 -060084 compatible = "u-boot,boot-std";
85
86 filename-prefixes = "/", "/boot/";
87 bootdev-order = "mmc2", "mmc1";
88
89 syslinux {
90 compatible = "u-boot,distro-syslinux";
91 };
92
93 efi {
94 compatible = "u-boot,distro-efi";
95 };
Simon Glassa56f6632022-10-20 18:23:14 -060096
Simon Glassd985f1d2023-01-06 08:52:41 -060097 theme {
98 font-size = <30>;
99 };
100
Simon Glass77bec9e2022-10-20 18:23:20 -0600101 /*
102 * This is used for the VBE OS-request tests. A FAT filesystem
103 * created in a partition with the VBE information appearing
104 * before the parititon starts
105 */
Simon Glassa56f6632022-10-20 18:23:14 -0600106 firmware0 {
107 u-boot,dm-vpl;
108 compatible = "fwupd,vbe-simple";
109 storage = "mmc1";
110 skip-offset = <0x200>;
111 area-start = <0x400>;
112 area-size = <0x1000>;
113 state-offset = <0x400>;
114 state-size = <0x40>;
115 version-offset = <0x800>;
116 version-size = <0x100>;
117 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600118
119 /*
120 * This is used for the VBE VPL tests. The MMC device holds the
121 * binman image.bin file. The test progresses through each phase
122 * of U-Boot, loading each in turn from MMC.
123 *
124 * Note that the test enables this node (and mmc3) before
125 * running U-Boot
126 */
127 firmware1 {
128 u-boot,dm-vpl;
129 status = "disabled";
130 compatible = "fwupd,vbe-simple";
131 storage = "mmc3";
132 skip-offset = <0x400000>;
133 area-start = <0>;
134 area-size = <0xe00000>;
135 state-offset = <0xdffc00>;
136 state-size = <0x40>;
137 version-offset = <0xdffe00>;
138 version-size = <0x100>;
139 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600140 };
141
Andrew Scull0518e7a2022-05-30 10:00:12 +0000142 fuzzing-engine {
143 compatible = "sandbox,fuzzing-engine";
144 };
145
Nandor Hanf9db2f12021-06-10 16:56:44 +0300146 reboot-mode0 {
147 compatible = "reboot-mode-gpio";
148 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
149 u-boot,env-variable = "bootstatus";
150 mode-test = <0x01>;
151 mode-download = <0x03>;
152 };
153
Nandor Hanc74675b2021-06-10 16:56:45 +0300154 reboot_mode1: reboot-mode@14 {
155 compatible = "reboot-mode-rtc";
156 rtc = <&rtc_0>;
157 reg = <0x30 4>;
158 u-boot,env-variable = "bootstatus";
159 big-endian;
160 mode-test = <0x21969147>;
161 mode-download = <0x51939147>;
162 };
163
Simon Glassce6d99a2018-12-10 10:37:33 -0700164 audio: audio-codec {
165 compatible = "sandbox,audio-codec";
166 #sound-dai-cells = <1>;
167 };
168
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200169 buttons {
170 compatible = "gpio-keys";
171
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200172 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200173 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200174 label = "button1";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200175 };
176
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200177 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200178 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200179 label = "button2";
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200180 };
181 };
182
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100183 buttons2 {
184 compatible = "adc-keys";
185 io-channels = <&adc 3>;
186 keyup-threshold-microvolt = <3000000>;
187
188 button-up {
189 label = "button3";
190 linux,code = <KEY_F3>;
191 press-threshold-microvolt = <1500000>;
192 };
193
194 button-down {
195 label = "button4";
196 linux,code = <KEY_F4>;
197 press-threshold-microvolt = <1000000>;
198 };
199
200 button-enter {
201 label = "button5";
202 linux,code = <KEY_F5>;
203 press-threshold-microvolt = <500000>;
204 };
205 };
206
Simon Glasse96fa6c2018-12-10 10:37:34 -0700207 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600208 reg = <0 0>;
209 compatible = "google,cros-ec-sandbox";
210
211 /*
212 * This describes the flash memory within the EC. Note
213 * that the STM32L flash erases to 0, not 0xff.
214 */
215 flash {
216 image-pos = <0x08000000>;
217 size = <0x20000>;
218 erase-value = <0>;
219
220 /* Information for sandbox */
221 ro {
222 image-pos = <0>;
223 size = <0xf000>;
224 };
225 wp-ro {
226 image-pos = <0xf000>;
227 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700228 used = <0x884>;
229 compress = "lz4";
230 uncomp-size = <0xcf8>;
231 hash {
232 algo = "sha256";
233 value = [00 01 02 03 04 05 06 07
234 08 09 0a 0b 0c 0d 0e 0f
235 10 11 12 13 14 15 16 17
236 18 19 1a 1b 1c 1d 1e 1f];
237 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600238 };
239 rw {
240 image-pos = <0x10000>;
241 size = <0x10000>;
242 };
243 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300244
245 cros_ec_pwm: cros-ec-pwm {
246 compatible = "google,cros-ec-pwm";
247 #pwm-cells = <1>;
248 };
249
Simon Glasse6c5c942018-10-01 12:22:08 -0600250 };
251
Yannick Fertré23f965a2019-10-07 15:29:05 +0200252 dsi_host: dsi_host {
253 compatible = "sandbox,dsi-host";
254 };
255
Simon Glass2e7d35d2014-02-26 15:59:21 -0700256 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600257 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700258 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600259 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700260 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600261 u-boot,dm-pre-reloc;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100262 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
263 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700264 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100265 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
266 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
267 <&gpio_b 7 GPIO_IN 3 2 1>,
268 <&gpio_b 8 GPIO_OUT 3 2 1>,
269 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100270 test3-gpios =
271 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
272 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
273 <&gpio_c 2 GPIO_OUT>,
274 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
275 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200276 <&gpio_c 5 GPIO_IN>,
277 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
278 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530279 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
280 test5-gpios = <&gpio_a 19>;
281
Simon Glassfb933d02021-10-23 17:26:04 -0600282 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200283 int8-value = /bits/ 8 <0x12>;
284 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700285 int-value = <1234>;
286 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200287 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200288 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600289 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700290 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600291 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200292 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530293
294 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
295 <&muxcontroller0 2>, <&muxcontroller0 3>,
296 <&muxcontroller1>;
297 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
298 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100299 display-timings {
300 timing0: 240x320 {
301 clock-frequency = <6500000>;
302 hactive = <240>;
303 vactive = <320>;
304 hfront-porch = <6>;
305 hback-porch = <7>;
306 hsync-len = <1>;
307 vback-porch = <5>;
308 vfront-porch = <8>;
309 vsync-len = <2>;
310 hsync-active = <1>;
311 vsync-active = <0>;
312 de-active = <1>;
313 pixelclk-active = <1>;
314 interlaced;
315 doublescan;
316 doubleclk;
317 };
318 timing1: 480x800 {
319 clock-frequency = <9000000>;
320 hactive = <480>;
321 vactive = <800>;
322 hfront-porch = <10>;
323 hback-porch = <59>;
324 hsync-len = <12>;
325 vback-porch = <15>;
326 vfront-porch = <17>;
327 vsync-len = <16>;
328 hsync-active = <0>;
329 vsync-active = <1>;
330 de-active = <0>;
331 pixelclk-active = <0>;
332 };
333 timing2: 800x480 {
334 clock-frequency = <33500000>;
335 hactive = <800>;
336 vactive = <480>;
337 hback-porch = <89>;
338 hfront-porch = <164>;
339 vback-porch = <23>;
340 vfront-porch = <10>;
341 hsync-len = <11>;
342 vsync-len = <13>;
343 };
344 };
Nikhil M Jain2f3d6a42023-01-31 15:35:15 +0530345 panel-timings {
346 clock-frequency = <6500000>;
347 hactive = <240>;
348 vactive = <320>;
349 hfront-porch = <6>;
350 hback-porch = <7>;
351 hsync-len = <1>;
352 vback-porch = <5>;
353 vfront-porch = <8>;
354 vsync-len = <2>;
355 hsync-active = <1>;
356 vsync-active = <0>;
357 de-active = <1>;
358 pixelclk-active = <1>;
359 interlaced;
360 doublescan;
361 doubleclk;
362 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700363 };
364
365 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600366 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700367 compatible = "not,compatible";
368 };
369
370 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600371 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700372 };
373
Simon Glass5d9a88f2018-10-01 12:22:40 -0600374 backlight: backlight {
375 compatible = "pwm-backlight";
376 enable-gpios = <&gpio_a 1>;
377 power-supply = <&ldo_1>;
378 pwms = <&pwm 0 1000>;
379 default-brightness-level = <5>;
380 brightness-levels = <0 16 32 64 128 170 202 234 255>;
381 };
382
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200383 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200384 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200385 bind-test-child1 {
386 compatible = "sandbox,phy";
387 #phy-cells = <1>;
388 };
389
390 bind-test-child2 {
391 compatible = "simple-bus";
392 };
393 };
394
Simon Glass2e7d35d2014-02-26 15:59:21 -0700395 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600396 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700397 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600398 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700399 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530400
401 mux-controls = <&muxcontroller0 0>;
402 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700403 };
404
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200405 phy_provider0: gen_phy@0 {
406 compatible = "sandbox,phy";
407 #phy-cells = <1>;
408 };
409
410 phy_provider1: gen_phy@1 {
411 compatible = "sandbox,phy";
412 #phy-cells = <0>;
413 broken;
414 };
415
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200416 phy_provider2: gen_phy@2 {
417 compatible = "sandbox,phy";
418 #phy-cells = <0>;
419 };
420
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200421 gen_phy_user: gen_phy_user {
422 compatible = "simple-bus";
423 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
424 phy-names = "phy1", "phy2", "phy3";
425 };
426
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200427 gen_phy_user1: gen_phy_user1 {
428 compatible = "simple-bus";
429 phys = <&phy_provider0 0>, <&phy_provider2>;
430 phy-names = "phy1", "phy2";
431 };
432
Simon Glass2e7d35d2014-02-26 15:59:21 -0700433 some-bus {
434 #address-cells = <1>;
435 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600436 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600437 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600438 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700439 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600440 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700441 compatible = "denx,u-boot-fdt-test";
442 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600443 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700444 ping-add = <5>;
445 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600446 c-test@0 {
447 compatible = "denx,u-boot-fdt-test";
448 reg = <0>;
449 ping-expect = <6>;
450 ping-add = <6>;
451 };
452 c-test@1 {
453 compatible = "denx,u-boot-fdt-test";
454 reg = <1>;
455 ping-expect = <7>;
456 ping-add = <7>;
457 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700458 };
459
460 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600461 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600462 ping-expect = <6>;
463 ping-add = <6>;
464 compatible = "google,another-fdt-test";
465 };
466
467 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600468 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600469 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700470 ping-add = <6>;
471 compatible = "google,another-fdt-test";
472 };
473
Simon Glass9cc36a22015-01-25 08:27:05 -0700474 f-test {
475 compatible = "denx,u-boot-fdt-test";
476 };
477
478 g-test {
479 compatible = "denx,u-boot-fdt-test";
480 };
481
Bin Meng2786cd72018-10-10 22:07:01 -0700482 h-test {
483 compatible = "denx,u-boot-fdt-test1";
484 };
485
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200486 i-test {
487 compatible = "mediatek,u-boot-fdt-test";
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 subnode@0 {
492 reg = <0>;
493 };
494
495 subnode@1 {
496 reg = <1>;
497 };
498
499 subnode@2 {
500 reg = <2>;
501 };
502 };
503
Simon Glassdc12ebb2019-12-29 21:19:25 -0700504 devres-test {
505 compatible = "denx,u-boot-devres-test";
506 };
507
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530508 another-test {
509 reg = <0 2>;
510 compatible = "denx,u-boot-fdt-test";
511 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
512 test5-gpios = <&gpio_a 19>;
513 };
514
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100515 mmio-bus@0 {
516 #address-cells = <1>;
517 #size-cells = <1>;
518 compatible = "denx,u-boot-test-bus";
519 dma-ranges = <0x10000000 0x00000000 0x00040000>;
520
521 subnode@0 {
522 compatible = "denx,u-boot-fdt-test";
523 };
524 };
525
526 mmio-bus@1 {
527 #address-cells = <1>;
528 #size-cells = <1>;
529 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100530
531 subnode@0 {
532 compatible = "denx,u-boot-fdt-test";
533 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100534 };
535
Simon Glass0f7b1112020-07-07 13:12:06 -0600536 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600537 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600538 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600539 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600540 child {
541 compatible = "denx,u-boot-acpi-test";
542 };
Simon Glassf50cc952020-04-08 16:57:34 -0600543 };
544
Simon Glass0f7b1112020-07-07 13:12:06 -0600545 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600546 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600547 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600548 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600549 };
550
Patrice Chotardee87a092017-09-04 14:55:57 +0200551 clocks {
552 clk_fixed: clk-fixed {
553 compatible = "fixed-clock";
554 #clock-cells = <0>;
555 clock-frequency = <1234>;
556 };
Anup Patelb630d572019-02-25 08:14:55 +0000557
558 clk_fixed_factor: clk-fixed-factor {
559 compatible = "fixed-factor-clock";
560 #clock-cells = <0>;
561 clock-div = <3>;
562 clock-mult = <2>;
563 clocks = <&clk_fixed>;
564 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200565
566 osc {
567 compatible = "fixed-clock";
568 #clock-cells = <0>;
569 clock-frequency = <20000000>;
570 };
Stephen Warren135aa952016-06-17 09:44:00 -0600571 };
572
573 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600574 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600575 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200576 assigned-clocks = <&clk_sandbox 3>;
577 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600578 };
579
580 clk-test {
581 compatible = "sandbox,clk-test";
582 clocks = <&clk_fixed>,
583 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200584 <&clk_sandbox 0>,
585 <&clk_sandbox 3>,
586 <&clk_sandbox 2>;
587 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600588 };
589
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200590 ccf: clk-ccf {
591 compatible = "sandbox,clk-ccf";
592 };
593
Simon Glass42b7f422021-12-04 08:56:31 -0700594 efi-media {
595 compatible = "sandbox,efi-media";
596 };
597
Simon Glass171e9912015-05-22 15:42:15 -0600598 eth@10002000 {
599 compatible = "sandbox,eth";
600 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600601 };
602
603 eth_5: eth@10003000 {
604 compatible = "sandbox,eth";
605 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400606 nvmem-cells = <&eth5_addr>;
607 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600608 };
609
Bin Meng71d79712015-08-27 22:25:53 -0700610 eth_3: sbe5 {
611 compatible = "sandbox,eth";
612 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400613 nvmem-cells = <&eth3_addr>;
614 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700615 };
616
Simon Glass171e9912015-05-22 15:42:15 -0600617 eth@10004000 {
618 compatible = "sandbox,eth";
619 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600620 };
621
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200622 phy_eth0: phy-test-eth {
623 compatible = "sandbox,eth";
624 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400625 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200626 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200627 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200628 };
629
Claudiu Manoilff98da02021-03-14 20:14:57 +0800630 dsa_eth0: dsa-test-eth {
631 compatible = "sandbox,eth";
632 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400633 nvmem-cells = <&eth4_addr>;
634 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800635 };
636
637 dsa-test {
638 compatible = "sandbox,dsa";
639
640 ports {
641 #address-cells = <1>;
642 #size-cells = <0>;
643 swp_0: port@0 {
644 reg = <0>;
645 label = "lan0";
646 phy-mode = "rgmii-rxid";
647
648 fixed-link {
649 speed = <100>;
650 full-duplex;
651 };
652 };
653
654 swp_1: port@1 {
655 reg = <1>;
656 label = "lan1";
657 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800658 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800659 };
660
661 port@2 {
662 reg = <2>;
663 ethernet = <&dsa_eth0>;
664
665 fixed-link {
666 speed = <1000>;
667 full-duplex;
668 };
669 };
670 };
671 };
672
Rajan Vaja31b82172018-09-19 03:43:46 -0700673 firmware {
674 sandbox_firmware: sandbox-firmware {
675 compatible = "sandbox,firmware";
676 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200677
Etienne Carriere41d62e22022-02-21 09:22:39 +0100678 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200679 compatible = "sandbox,scmi-agent";
680 #address-cells = <1>;
681 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200682
Etienne Carriere41d62e22022-02-21 09:22:39 +0100683 protocol@10 {
684 reg = <0x10>;
685 };
686
687 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200688 reg = <0x14>;
689 #clock-cells = <1>;
690 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200691
Etienne Carriere41d62e22022-02-21 09:22:39 +0100692 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200693 reg = <0x16>;
694 #reset-cells = <1>;
695 };
Etienne Carriere01242182021-03-08 22:38:07 +0100696
697 protocol@17 {
698 reg = <0x17>;
699
700 regulators {
701 #address-cells = <1>;
702 #size-cells = <0>;
703
Etienne Carriere41d62e22022-02-21 09:22:39 +0100704 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100705 reg = <0>;
706 regulator-name = "sandbox-voltd0";
707 regulator-min-microvolt = <1100000>;
708 regulator-max-microvolt = <3300000>;
709 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100710 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100711 reg = <0x1>;
712 regulator-name = "sandbox-voltd1";
713 regulator-min-microvolt = <1800000>;
714 };
715 };
716 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200717 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700718 };
719
Alexander Dahl1323d082022-09-30 14:04:30 +0200720 fpga {
721 compatible = "sandbox,fpga";
722 };
723
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100724 pinctrl-gpio {
725 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700726
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100727 gpio_a: base-gpios {
728 compatible = "sandbox,gpio";
729 gpio-controller;
730 #gpio-cells = <1>;
731 gpio-bank-name = "a";
732 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200733 hog_input_active_low {
734 gpio-hog;
735 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200736 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200737 };
738 hog_input_active_high {
739 gpio-hog;
740 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200741 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200742 };
743 hog_output_low {
744 gpio-hog;
745 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200746 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200747 };
748 hog_output_high {
749 gpio-hog;
750 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200751 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200752 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100753 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600754
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100755 gpio_b: extra-gpios {
756 compatible = "sandbox,gpio";
757 gpio-controller;
758 #gpio-cells = <5>;
759 gpio-bank-name = "b";
760 sandbox,gpio-count = <10>;
761 };
762
763 gpio_c: pinmux-gpios {
764 compatible = "sandbox,gpio";
765 gpio-controller;
766 #gpio-cells = <2>;
767 gpio-bank-name = "c";
768 sandbox,gpio-count = <10>;
769 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100770 };
771
Simon Glassecc2ed52014-12-10 08:55:55 -0700772 i2c@0 {
773 #address-cells = <1>;
774 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600775 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700776 compatible = "sandbox,i2c";
777 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200778 pinctrl-names = "default";
779 pinctrl-0 = <&pinmux_i2c0_pins>;
780
Simon Glassecc2ed52014-12-10 08:55:55 -0700781 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400782 #address-cells = <1>;
783 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700784 reg = <0x2c>;
785 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700786 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200787 partitions {
788 compatible = "fixed-partitions";
789 #address-cells = <1>;
790 #size-cells = <1>;
791 bootcount_i2c: bootcount@10 {
792 reg = <10 2>;
793 };
794 };
Sean Anderson472caa62022-05-05 13:11:42 -0400795
796 eth3_addr: mac-address@24 {
797 reg = <24 6>;
798 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700799 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200800
Simon Glass52d3bc52015-05-22 15:42:17 -0600801 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400802 #address-cells = <1>;
803 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600804 reg = <0x43>;
805 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700806 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400807
808 eth4_addr: mac-address@40 {
809 reg = <0x40 6>;
810 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600811 };
812
813 rtc_1: rtc@61 {
814 reg = <0x61>;
815 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700816 sandbox,emul = <&emul1>;
817 };
818
819 i2c_emul: emul {
820 reg = <0xff>;
821 compatible = "sandbox,i2c-emul-parent";
822 emul_eeprom: emul-eeprom {
823 compatible = "sandbox,i2c-eeprom";
824 sandbox,filename = "i2c.bin";
825 sandbox,size = <256>;
826 };
827 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700828 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700829 };
830 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700831 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600832 };
833 };
834
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200835 sandbox_pmic: sandbox_pmic {
836 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700837 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200838 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200839
840 mc34708: pmic@41 {
841 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700842 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200843 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700844 };
845
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100846 bootcount@0 {
847 compatible = "u-boot,bootcount-rtc";
848 rtc = <&rtc_1>;
849 offset = <0x13>;
850 };
851
Michal Simekf692b472020-05-28 11:48:55 +0200852 bootcount {
853 compatible = "u-boot,bootcount-i2c-eeprom";
854 i2c-eeprom = <&bootcount_i2c>;
855 };
856
Nandor Hanc50b21b2021-06-10 15:40:38 +0300857 bootcount_4@0 {
858 compatible = "u-boot,bootcount-syscon";
859 syscon = <&syscon0>;
860 reg = <0x0 0x04>, <0x0 0x04>;
861 reg-names = "syscon_reg", "offset";
862 };
863
864 bootcount_2@0 {
865 compatible = "u-boot,bootcount-syscon";
866 syscon = <&syscon0>;
867 reg = <0x0 0x04>, <0x0 0x02> ;
868 reg-names = "syscon_reg", "offset";
869 };
870
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100871 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100872 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100873 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100874 vdd-supply = <&buck2>;
875 vss-microvolts = <0>;
876 };
877
Mark Kettenisfb574622021-10-23 16:58:02 +0200878 iommu: iommu@0 {
879 compatible = "sandbox,iommu";
880 #iommu-cells = <0>;
881 };
882
Simon Glass02554352020-02-06 09:55:00 -0700883 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700884 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700885 interrupt-controller;
886 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700887 };
888
Simon Glass3c97c4f2016-01-18 19:52:26 -0700889 lcd {
890 u-boot,dm-pre-reloc;
891 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200892 pinctrl-names = "default";
893 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700894 xres = <1366>;
895 yres = <768>;
896 };
897
Simon Glass3c43fba2015-07-06 12:54:34 -0600898 leds {
899 compatible = "gpio-leds";
900
901 iracibble {
902 gpios = <&gpio_a 1 0>;
903 label = "sandbox:red";
904 };
905
906 martinet {
907 gpios = <&gpio_a 2 0>;
908 label = "sandbox:green";
909 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200910
911 default_on {
912 gpios = <&gpio_a 5 0>;
913 label = "sandbox:default_on";
914 default-state = "on";
915 };
916
917 default_off {
918 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400919 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200920 default-state = "off";
921 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600922 };
923
Paul Doelle1fc45d62022-07-04 09:00:25 +0000924 wdt-gpio-toggle {
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200925 gpios = <&gpio_a 7 0>;
926 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200927 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000928 hw_algo = "toggle";
929 always-running;
930 };
931
932 wdt-gpio-level {
933 gpios = <&gpio_a 7 0>;
934 compatible = "linux,wdt-gpio";
935 hw_margin_ms = <100>;
936 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200937 always-running;
938 };
939
Stephen Warren8961b522016-05-16 17:41:37 -0600940 mbox: mbox {
941 compatible = "sandbox,mbox";
942 #mbox-cells = <1>;
943 };
944
945 mbox-test {
946 compatible = "sandbox,mbox-test";
947 mboxes = <&mbox 100>, <&mbox 1>;
948 mbox-names = "other", "test";
949 };
950
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900951 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200952 #address-cells = <1>;
953 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400954 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200955 cpu1: cpu@1 {
956 device_type = "cpu";
957 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400958 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900959 compatible = "sandbox,cpu_sandbox";
960 u-boot,dm-pre-reloc;
961 };
Mario Sixfa44b532018-08-06 10:23:44 +0200962
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200963 cpu2: cpu@2 {
964 device_type = "cpu";
965 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900966 compatible = "sandbox,cpu_sandbox";
967 u-boot,dm-pre-reloc;
968 };
Mario Sixfa44b532018-08-06 10:23:44 +0200969
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200970 cpu3: cpu@3 {
971 device_type = "cpu";
972 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900973 compatible = "sandbox,cpu_sandbox";
974 u-boot,dm-pre-reloc;
975 };
Mario Sixfa44b532018-08-06 10:23:44 +0200976 };
977
Dave Gerlach21e3c212020-07-15 23:39:58 -0500978 chipid: chipid {
979 compatible = "sandbox,soc";
980 };
981
Simon Glasse96fa6c2018-12-10 10:37:34 -0700982 i2s: i2s {
983 compatible = "sandbox,i2s";
984 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700985 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700986 };
987
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200988 nop-test_0 {
989 compatible = "sandbox,nop_sandbox1";
990 nop-test_1 {
991 compatible = "sandbox,nop_sandbox2";
992 bind = "True";
993 };
994 nop-test_2 {
995 compatible = "sandbox,nop_sandbox2";
996 bind = "False";
997 };
998 };
999
Roger Quadros2c120372022-10-20 16:30:46 +03001000 memory-controller {
1001 compatible = "sandbox,memory";
1002 };
1003
Mario Six004e67c2018-07-31 14:24:14 +02001004 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -04001005 #address-cells = <1>;
1006 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +02001007 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -04001008
1009 eth5_addr: mac-address@10 {
1010 reg = <0x10 6>;
1011 };
Mario Six004e67c2018-07-31 14:24:14 +02001012 };
1013
Simon Glasse48eeb92017-04-23 20:02:07 -06001014 mmc2 {
1015 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -06001016 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -06001017 };
1018
Simon Glassfb1451b2022-04-24 23:31:24 -06001019 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001020 mmc1 {
1021 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001022 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001023 };
1024
Simon Glassfb1451b2022-04-24 23:31:24 -06001025 /* This is used for the fastboot tests */
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301026 mmc0: mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001027 compatible = "sandbox,mmc";
1028 };
1029
Simon Glass77bec9e2022-10-20 18:23:20 -06001030 /* This is used for VBE VPL tests */
1031 mmc3 {
1032 status = "disabled";
1033 compatible = "sandbox,mmc";
1034 filename = "image.bin";
1035 non-removable;
1036 };
1037
Simon Glassd985f1d2023-01-06 08:52:41 -06001038 /* This is used for bootstd bootmenu tests */
1039 mmc4 {
1040 status = "disabled";
1041 compatible = "sandbox,mmc";
1042 filename = "mmc4.img";
1043 };
1044
Simon Glassb45c8332019-02-16 20:24:50 -07001045 pch {
1046 compatible = "sandbox,pch";
1047 };
1048
Tom Rini42c64d12020-02-11 12:41:23 -05001049 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001050 compatible = "sandbox,pci";
1051 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001052 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001053 #address-cells = <3>;
1054 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001055 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001056 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis08386da2023-01-21 20:27:57 +01001057 iommu-map = <0x0010 &iommu 0 1>;
1058 iommu-map-mask = <0xfffffff8>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001059 pci@0,0 {
1060 compatible = "pci-generic";
1061 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001062 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001063 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001064 pci@1,0 {
1065 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001066 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1067 reg = <0x02000814 0 0 0 0
1068 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001069 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001070 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001071 p2sb-pci@2,0 {
1072 compatible = "sandbox,p2sb";
1073 reg = <0x02001010 0 0 0 0>;
1074 sandbox,emul = <&p2sb_emul>;
1075
1076 adder {
1077 intel,p2sb-port-id = <3>;
1078 compatible = "sandbox,adder";
1079 };
1080 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001081 pci@1e,0 {
1082 compatible = "sandbox,pmc";
1083 reg = <0xf000 0 0 0 0>;
1084 sandbox,emul = <&pmc_emul1e>;
1085 acpi-base = <0x400>;
1086 gpe0-dwx-mask = <0xf>;
1087 gpe0-dwx-shift-base = <4>;
1088 gpe0-dw = <6 7 9>;
1089 gpe0-sts = <0x20>;
1090 gpe0-en = <0x30>;
1091 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001092 pci@1f,0 {
1093 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001094 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1095 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001096 sandbox,emul = <&swap_case_emul0_1f>;
1097 };
1098 };
1099
1100 pci-emul0 {
1101 compatible = "sandbox,pci-emul-parent";
1102 swap_case_emul0_0: emul0@0,0 {
1103 compatible = "sandbox,swap-case";
1104 };
1105 swap_case_emul0_1: emul0@1,0 {
1106 compatible = "sandbox,swap-case";
1107 use-ea;
1108 };
1109 swap_case_emul0_1f: emul0@1f,0 {
1110 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001111 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001112 p2sb_emul: emul@2,0 {
1113 compatible = "sandbox,p2sb-emul";
1114 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001115 pmc_emul1e: emul@1e,0 {
1116 compatible = "sandbox,pmc-emul";
1117 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001118 };
1119
Tom Rini42c64d12020-02-11 12:41:23 -05001120 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001121 compatible = "sandbox,pci";
1122 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001123 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001124 #address-cells = <3>;
1125 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001126 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001127 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001128 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001129 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001130 0x0c 0x00 0x1234 0x5678
1131 0x10 0x00 0x1234 0x5678>;
1132 pci@10,0 {
1133 reg = <0x8000 0 0 0 0>;
1134 };
Bin Mengdee4d752018-08-03 01:14:41 -07001135 };
1136
Tom Rini42c64d12020-02-11 12:41:23 -05001137 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001138 compatible = "sandbox,pci";
1139 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001140 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001141 #address-cells = <3>;
1142 #size-cells = <2>;
1143 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1144 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1145 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1146 pci@1f,0 {
1147 compatible = "pci-generic";
1148 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001149 sandbox,emul = <&swap_case_emul2_1f>;
1150 };
1151 };
1152
1153 pci-emul2 {
1154 compatible = "sandbox,pci-emul-parent";
1155 swap_case_emul2_1f: emul2@1f,0 {
1156 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001157 };
1158 };
1159
Ramon Friedbb413332019-04-27 11:15:23 +03001160 pci_ep: pci_ep {
1161 compatible = "sandbox,pci_ep";
1162 };
1163
Simon Glass98561572017-04-23 20:10:44 -06001164 probing {
1165 compatible = "simple-bus";
1166 test1 {
1167 compatible = "denx,u-boot-probe-test";
1168 };
1169
1170 test2 {
1171 compatible = "denx,u-boot-probe-test";
1172 };
1173
1174 test3 {
1175 compatible = "denx,u-boot-probe-test";
1176 };
1177
1178 test4 {
1179 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001180 first-syscon = <&syscon0>;
1181 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001182 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001183 };
1184 };
1185
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001186 pwrdom: power-domain {
1187 compatible = "sandbox,power-domain";
1188 #power-domain-cells = <1>;
1189 };
1190
1191 power-domain-test {
1192 compatible = "sandbox,power-domain-test";
1193 power-domains = <&pwrdom 2>;
1194 };
1195
Simon Glass5d9a88f2018-10-01 12:22:40 -06001196 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001197 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001198 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001199 pinctrl-names = "default";
1200 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001201 };
1202
1203 pwm2 {
1204 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001205 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001206 };
1207
Simon Glass64ce0ca2015-07-06 12:54:31 -06001208 ram {
1209 compatible = "sandbox,ram";
1210 };
1211
Simon Glass5010d982015-07-06 12:54:29 -06001212 reset@0 {
1213 compatible = "sandbox,warm-reset";
Michal Suchanek5b2f49c2022-10-10 20:29:39 +02001214 u-boot,dm-pre-proper;
Simon Glass5010d982015-07-06 12:54:29 -06001215 };
1216
1217 reset@1 {
1218 compatible = "sandbox,reset";
Michal Suchanek5b2f49c2022-10-10 20:29:39 +02001219 u-boot,dm-pre-proper;
Simon Glass5010d982015-07-06 12:54:29 -06001220 };
1221
Stephen Warren4581b712016-06-17 09:43:59 -06001222 resetc: reset-ctl {
1223 compatible = "sandbox,reset-ctl";
1224 #reset-cells = <1>;
1225 };
1226
1227 reset-ctl-test {
1228 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001229 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1230 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001231 };
1232
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301233 rng {
1234 compatible = "sandbox,sandbox-rng";
1235 };
1236
Nishanth Menon52159402015-09-17 15:42:41 -05001237 rproc_1: rproc@1 {
1238 compatible = "sandbox,test-processor";
1239 remoteproc-name = "remoteproc-test-dev1";
1240 };
1241
1242 rproc_2: rproc@2 {
1243 compatible = "sandbox,test-processor";
1244 internal-memory-mapped;
1245 remoteproc-name = "remoteproc-test-dev2";
1246 };
1247
Simon Glass5d9a88f2018-10-01 12:22:40 -06001248 panel {
1249 compatible = "simple-panel";
1250 backlight = <&backlight 0 100>;
1251 };
1252
Simon Glass22c80d52022-09-21 16:21:47 +02001253 scsi {
1254 compatible = "sandbox,scsi";
1255 sandbox,filepath = "scsi.img";
1256 };
1257
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001258 smem@0 {
1259 compatible = "sandbox,smem";
1260 };
1261
Simon Glassd4901892018-12-10 10:37:36 -07001262 sound {
1263 compatible = "sandbox,sound";
1264 cpu {
1265 sound-dai = <&i2s 0>;
1266 };
1267
1268 codec {
1269 sound-dai = <&audio 0>;
1270 };
1271 };
1272
Simon Glass0ae0cb72014-10-13 23:42:11 -06001273 spi@0 {
1274 #address-cells = <1>;
1275 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001276 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001277 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001278 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001279 pinctrl-names = "default";
1280 pinctrl-0 = <&pinmux_spi0_pins>;
1281
Simon Glass0ae0cb72014-10-13 23:42:11 -06001282 spi.bin@0 {
1283 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001284 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001285 spi-max-frequency = <40000000>;
1286 sandbox,filename = "spi.bin";
1287 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001288 spi.bin@1 {
1289 reg = <1>;
1290 compatible = "spansion,m25p16", "jedec,spi-nor";
1291 spi-max-frequency = <50000000>;
1292 sandbox,filename = "spi.bin";
1293 spi-cpol;
1294 spi-cpha;
1295 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001296 };
1297
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001298 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001299 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001300 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001301 };
1302
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001303 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001304 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001305 reg = <0x20 5
1306 0x28 6
1307 0x30 7
1308 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001309 };
1310
Patrick Delaunaya442e612019-03-07 09:57:13 +01001311 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001312 compatible = "simple-mfd", "syscon";
1313 reg = <0x40 5
1314 0x48 6
1315 0x50 7
1316 0x58 8>;
1317 };
1318
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301319 syscon3: syscon@3 {
1320 compatible = "simple-mfd", "syscon";
1321 reg = <0x000100 0x10>;
1322
1323 muxcontroller0: a-mux-controller {
1324 compatible = "mmio-mux";
1325 #mux-control-cells = <1>;
1326
1327 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1328 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1329 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1330 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1331 u-boot,mux-autoprobe;
1332 };
1333 };
1334
1335 muxcontroller1: emul-mux-controller {
1336 compatible = "mux-emul";
1337 #mux-control-cells = <0>;
1338 u-boot,mux-autoprobe;
1339 idle-state = <0xabcd>;
1340 };
1341
Simon Glass93f44e82020-12-16 21:20:27 -07001342 testfdtm0 {
1343 compatible = "denx,u-boot-fdtm-test";
1344 };
1345
1346 testfdtm1: testfdtm1 {
1347 compatible = "denx,u-boot-fdtm-test";
1348 };
1349
1350 testfdtm2 {
1351 compatible = "denx,u-boot-fdtm-test";
1352 };
1353
Sean Anderson7616e362020-09-28 10:52:23 -04001354 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001355 compatible = "sandbox,timer";
1356 clock-frequency = <1000000>;
1357 };
1358
Sean Anderson7616e362020-09-28 10:52:23 -04001359 timer@1 {
1360 compatible = "sandbox,timer";
1361 sandbox,timebase-frequency-fallback;
1362 };
1363
Miquel Raynalb91ad162018-05-15 11:57:27 +02001364 tpm2 {
1365 compatible = "sandbox,tpm2";
1366 };
1367
Simon Glass171e9912015-05-22 15:42:15 -06001368 uart0: serial {
1369 compatible = "sandbox,serial";
1370 u-boot,dm-pre-reloc;
Dario Binacchi55322622021-04-11 09:39:50 +02001371 pinctrl-names = "default";
1372 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001373 };
1374
Simon Glasse00cb222015-03-25 12:23:05 -06001375 usb_0: usb@0 {
1376 compatible = "sandbox,usb";
1377 status = "disabled";
1378 hub {
1379 compatible = "sandbox,usb-hub";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1382 flash-stick {
1383 reg = <0>;
1384 compatible = "sandbox,usb-flash";
1385 };
1386 };
1387 };
1388
1389 usb_1: usb@1 {
1390 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001391 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001392 hub {
1393 compatible = "usb-hub";
1394 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001395 #address-cells = <1>;
1396 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001397 hub-emul {
1398 compatible = "sandbox,usb-hub";
1399 #address-cells = <1>;
1400 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001401 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001402 reg = <0>;
1403 compatible = "sandbox,usb-flash";
1404 sandbox,filepath = "testflash.bin";
1405 };
1406
Simon Glass431cbd62015-11-08 23:48:01 -07001407 flash-stick@1 {
1408 reg = <1>;
1409 compatible = "sandbox,usb-flash";
1410 sandbox,filepath = "testflash1.bin";
1411 };
1412
1413 flash-stick@2 {
1414 reg = <2>;
1415 compatible = "sandbox,usb-flash";
1416 sandbox,filepath = "testflash2.bin";
1417 };
1418
Simon Glassbff1a712015-11-08 23:48:08 -07001419 keyb@3 {
1420 reg = <3>;
1421 compatible = "sandbox,usb-keyb";
1422 };
1423
Simon Glasse00cb222015-03-25 12:23:05 -06001424 };
Michael Wallec03b7612020-06-02 01:47:07 +02001425
1426 usbstor@1 {
1427 reg = <1>;
1428 };
1429 usbstor@3 {
1430 reg = <3>;
1431 };
Simon Glasse00cb222015-03-25 12:23:05 -06001432 };
1433 };
1434
1435 usb_2: usb@2 {
1436 compatible = "sandbox,usb";
1437 status = "disabled";
1438 };
1439
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001440 spmi: spmi@0 {
1441 compatible = "sandbox,spmi";
1442 #address-cells = <0x1>;
1443 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001444 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001445 pm8916@0 {
1446 compatible = "qcom,spmi-pmic";
1447 reg = <0x0 0x1>;
1448 #address-cells = <0x1>;
1449 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001450 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001451
1452 spmi_gpios: gpios@c000 {
1453 compatible = "qcom,pm8916-gpio";
1454 reg = <0xc000 0x400>;
1455 gpio-controller;
1456 gpio-count = <4>;
1457 #gpio-cells = <2>;
1458 gpio-bank-name="spmi";
1459 };
1460 };
1461 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001462
1463 wdt0: wdt@0 {
1464 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001465 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001466 };
Rob Clarkf2006802018-01-10 11:33:30 +01001467
Mario Six957983e2018-08-09 14:51:19 +02001468 axi: axi@0 {
1469 compatible = "sandbox,axi";
1470 #address-cells = <0x1>;
1471 #size-cells = <0x1>;
1472 store@0 {
1473 compatible = "sandbox,sandbox_store";
1474 reg = <0x0 0x400>;
1475 };
1476 };
1477
Rob Clarkf2006802018-01-10 11:33:30 +01001478 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001479 #address-cells = <1>;
1480 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001481 setting = "sunrise ohoka";
1482 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001483 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001484 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001485 chosen-test {
1486 compatible = "denx,u-boot-fdt-test";
1487 reg = <9 1>;
1488 };
1489 };
Mario Sixe8d52912018-03-12 14:53:33 +01001490
1491 translation-test@8000 {
1492 compatible = "simple-bus";
1493 reg = <0x8000 0x4000>;
1494
1495 #address-cells = <0x2>;
1496 #size-cells = <0x1>;
1497
1498 ranges = <0 0x0 0x8000 0x1000
1499 1 0x100 0x9000 0x1000
1500 2 0x200 0xA000 0x1000
1501 3 0x300 0xB000 0x1000
1502 >;
1503
Fabien Dessenne641067f2019-05-31 15:11:30 +02001504 dma-ranges = <0 0x000 0x10000000 0x1000
1505 1 0x100 0x20000000 0x1000
1506 >;
1507
Mario Sixe8d52912018-03-12 14:53:33 +01001508 dev@0,0 {
1509 compatible = "denx,u-boot-fdt-dummy";
1510 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001511 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001512 };
1513
1514 dev@1,100 {
1515 compatible = "denx,u-boot-fdt-dummy";
1516 reg = <1 0x100 0x1000>;
1517
1518 };
1519
1520 dev@2,200 {
1521 compatible = "denx,u-boot-fdt-dummy";
1522 reg = <2 0x200 0x1000>;
1523 };
1524
1525
1526 noxlatebus@3,300 {
1527 compatible = "simple-bus";
1528 reg = <3 0x300 0x1000>;
1529
1530 #address-cells = <0x1>;
1531 #size-cells = <0x0>;
1532
1533 dev@42 {
1534 compatible = "denx,u-boot-fdt-dummy";
1535 reg = <0x42>;
1536 };
1537 };
1538 };
Mario Six4eea5312018-09-27 09:19:31 +02001539
Dzmitry Sankouski298ffdd2023-01-22 18:21:23 +03001540 ofnode-foreach {
1541 compatible = "foreach";
1542
1543 first {
1544 prop1 = <1>;
1545 prop2 = <2>;
1546 };
1547
1548 second {
1549 prop1 = <1>;
1550 prop2 = <2>;
1551 };
1552 };
1553
Mario Six4eea5312018-09-27 09:19:31 +02001554 osd {
1555 compatible = "sandbox,sandbox_osd";
1556 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001557
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001558 sandbox_tee {
1559 compatible = "sandbox,tee";
1560 };
Bin Meng4f89d492018-10-15 02:21:26 -07001561
1562 sandbox_virtio1 {
1563 compatible = "sandbox,virtio1";
Simon Glass00fc8ca2023-01-17 10:47:51 -07001564 virtio-type = <4>; /* rng */
Bin Meng4f89d492018-10-15 02:21:26 -07001565 };
1566
1567 sandbox_virtio2 {
1568 compatible = "sandbox,virtio2";
1569 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001570
Simon Glass00fc8ca2023-01-17 10:47:51 -07001571 sandbox-virtio-blk {
1572 compatible = "sandbox,virtio1";
1573 virtio-type = <2>; /* block */
1574 };
1575
Etienne Carriere87d4f272020-09-09 18:44:05 +02001576 sandbox_scmi {
1577 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001578 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001579 resets = <&reset_scmi 3>;
1580 regul0-supply = <&regul0_scmi>;
1581 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001582 };
1583
Patrice Chotardf41a8242018-10-24 14:10:23 +02001584 pinctrl {
1585 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001586
Sean Anderson7f0f1802020-09-14 11:01:57 -04001587 pinctrl-names = "default", "alternate";
1588 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1589 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001590
Sean Anderson7f0f1802020-09-14 11:01:57 -04001591 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001592 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001593 pins = "P5";
1594 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001595 bias-pull-up;
1596 input-disable;
1597 };
1598 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001599 pins = "P6";
1600 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001601 output-high;
1602 drive-open-drain;
1603 };
1604 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001605 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001606 bias-pull-down;
1607 input-enable;
1608 };
1609 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001610 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001611 bias-disable;
1612 };
1613 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001614
1615 pinctrl_i2c: i2c {
1616 groups {
1617 groups = "I2C_UART";
1618 function = "I2C";
1619 };
1620
1621 pins {
1622 pins = "P0", "P1";
1623 drive-open-drain;
1624 };
1625 };
1626
1627 pinctrl_i2s: i2s {
1628 groups = "SPI_I2S";
1629 function = "I2S";
1630 };
1631
1632 pinctrl_spi: spi {
1633 groups = "SPI_I2S";
1634 function = "SPI";
1635
1636 cs {
1637 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1638 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1639 };
1640 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001641 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001642
Dario Binacchi55322622021-04-11 09:39:50 +02001643 pinctrl-single-no-width {
1644 compatible = "pinctrl-single";
1645 reg = <0x0000 0x238>;
1646 #pinctrl-cells = <1>;
1647 pinctrl-single,function-mask = <0x7f>;
1648 };
1649
1650 pinctrl-single-pins {
1651 compatible = "pinctrl-single";
1652 reg = <0x0000 0x238>;
1653 #pinctrl-cells = <1>;
1654 pinctrl-single,register-width = <32>;
1655 pinctrl-single,function-mask = <0x7f>;
1656
1657 pinmux_pwm_pins: pinmux_pwm_pins {
1658 pinctrl-single,pins = < 0x48 0x06 >;
1659 };
1660
1661 pinmux_spi0_pins: pinmux_spi0_pins {
1662 pinctrl-single,pins = <
1663 0x190 0x0c
1664 0x194 0x0c
1665 0x198 0x23
1666 0x19c 0x0c
1667 >;
1668 };
1669
1670 pinmux_uart0_pins: pinmux_uart0_pins {
1671 pinctrl-single,pins = <
1672 0x70 0x30
1673 0x74 0x00
1674 >;
1675 };
1676 };
1677
1678 pinctrl-single-bits {
1679 compatible = "pinctrl-single";
1680 reg = <0x0000 0x50>;
1681 #pinctrl-cells = <2>;
1682 pinctrl-single,bit-per-mux;
1683 pinctrl-single,register-width = <32>;
1684 pinctrl-single,function-mask = <0xf>;
1685
1686 pinmux_i2c0_pins: pinmux_i2c0_pins {
1687 pinctrl-single,bits = <
1688 0x10 0x00002200 0x0000ff00
1689 >;
1690 };
1691
1692 pinmux_lcd_pins: pinmux_lcd_pins {
1693 pinctrl-single,bits = <
1694 0x40 0x22222200 0xffffff00
1695 0x44 0x22222222 0xffffffff
1696 0x48 0x00000022 0x000000ff
1697 0x48 0x02000000 0x0f000000
1698 0x4c 0x02000022 0x0f0000ff
1699 >;
1700 };
1701 };
1702
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001703 hwspinlock@0 {
1704 compatible = "sandbox,hwspinlock";
1705 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001706
1707 dma: dma {
1708 compatible = "sandbox,dma";
1709 #dma-cells = <1>;
1710
1711 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1712 dma-names = "m2m", "tx0", "rx0";
1713 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001714
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001715 /*
1716 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1717 * end of the test. If parent mdio is removed first, clean-up of the
1718 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1719 * active at the end of the test. That it turn doesn't allow the mdio
1720 * class to be destroyed, triggering an error.
1721 */
1722 mdio-mux-test {
1723 compatible = "sandbox,mdio-mux";
1724 #address-cells = <1>;
1725 #size-cells = <0>;
1726 mdio-parent-bus = <&mdio>;
1727
1728 mdio-ch-test@0 {
1729 reg = <0>;
1730 };
1731 mdio-ch-test@1 {
1732 reg = <1>;
1733 };
1734 };
1735
1736 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001737 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001738 #address-cells = <1>;
1739 #size-cells = <0>;
1740
1741 ethphy1: ethernet-phy@1 {
1742 reg = <1>;
1743 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001744 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001745
1746 pm-bus-test {
1747 compatible = "simple-pm-bus";
1748 clocks = <&clk_sandbox 4>;
1749 power-domains = <&pwrdom 1>;
1750 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001751
1752 resetc2: syscon-reset {
1753 compatible = "syscon-reset";
1754 #reset-cells = <1>;
1755 regmap = <&syscon0>;
1756 offset = <1>;
1757 mask = <0x27FFFFFF>;
1758 assert-high = <0>;
1759 };
1760
1761 syscon-reset-test {
1762 compatible = "sandbox,misc_sandbox";
1763 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1764 reset-names = "valid", "no_mask", "out_of_range";
1765 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301766
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001767 sysinfo {
1768 compatible = "sandbox,sysinfo-sandbox";
1769 };
1770
Sean Anderson1cbfed82021-04-20 10:50:58 -04001771 sysinfo-gpio {
1772 compatible = "gpio-sysinfo";
1773 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1774 revisions = <19>, <5>;
1775 names = "rev_a", "foo";
1776 };
1777
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301778 some_regmapped-bus {
1779 #address-cells = <0x1>;
1780 #size-cells = <0x1>;
1781
1782 ranges = <0x0 0x0 0x10>;
1783 compatible = "simple-bus";
1784
1785 regmap-test_0 {
1786 reg = <0 0x10>;
1787 compatible = "sandbox,regmap_test";
1788 };
1789 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001790
1791 thermal {
1792 compatible = "sandbox,thermal";
1793 };
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301794
1795 fwu-mdata {
1796 compatible = "u-boot,fwu-mdata-gpt";
1797 fwu-mdata-store = <&mmc0>;
1798 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001799};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001800
1801#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001802#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001803
1804#ifdef CONFIG_SANDBOX_VPL
1805#include "sandbox_vpl.dtsi"
1806#endif