blob: 38d5739421f6928aedb9db8ae7ba7d03f931030a [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Bin Mengdee4d752018-08-03 01:14:41 -070042 pci0 = &pci0;
43 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070044 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020045 remoteproc0 = &rproc_1;
46 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060047 rtc0 = &rtc_0;
48 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060049 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020050 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070051 testbus3 = "/some-bus";
52 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070053 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070054 testfdt3 = "/b-test";
55 testfdt5 = "/some-bus/c-test@5";
56 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070057 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020058 fdt-dummy0 = "/translation-test@8000/dev@0,0";
59 fdt-dummy1 = "/translation-test@8000/dev@1,100";
60 fdt-dummy2 = "/translation-test@8000/dev@2,200";
61 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060062 usb0 = &usb_0;
63 usb1 = &usb_1;
64 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020065 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020066 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060067 };
68
Simon Glass8de98962022-10-20 18:23:15 -060069 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020070 };
71
Rasmus Villemoes8c728422021-04-21 11:06:55 +020072 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060073 testing-bool;
74 testing-int = <123>;
75 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020076 environment {
77 from_fdt = "yes";
78 fdt_env_path = "";
79 };
80 };
81
Simon Glassfb1451b2022-04-24 23:31:24 -060082 bootstd {
Simon Glass8c103c32023-02-13 08:56:33 -070083 bootph-verify;
Simon Glassfb1451b2022-04-24 23:31:24 -060084 compatible = "u-boot,boot-std";
85
86 filename-prefixes = "/", "/boot/";
87 bootdev-order = "mmc2", "mmc1";
88
Simon Glass79f66352023-05-10 16:34:46 -060089 extlinux {
90 compatible = "u-boot,extlinux";
Simon Glassfb1451b2022-04-24 23:31:24 -060091 };
92
93 efi {
94 compatible = "u-boot,distro-efi";
95 };
Simon Glassa56f6632022-10-20 18:23:14 -060096
Simon Glassd985f1d2023-01-06 08:52:41 -060097 theme {
98 font-size = <30>;
Simon Glass7230fdb2023-06-01 10:23:00 -060099 menu-inset = <3>;
100 menuitem-gap-y = <1>;
Simon Glassd985f1d2023-01-06 08:52:41 -0600101 };
102
Simon Glass77bec9e2022-10-20 18:23:20 -0600103 /*
104 * This is used for the VBE OS-request tests. A FAT filesystem
105 * created in a partition with the VBE information appearing
106 * before the parititon starts
107 */
Simon Glassa56f6632022-10-20 18:23:14 -0600108 firmware0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700109 bootph-verify;
Simon Glassa56f6632022-10-20 18:23:14 -0600110 compatible = "fwupd,vbe-simple";
111 storage = "mmc1";
112 skip-offset = <0x200>;
113 area-start = <0x400>;
114 area-size = <0x1000>;
115 state-offset = <0x400>;
116 state-size = <0x40>;
117 version-offset = <0x800>;
118 version-size = <0x100>;
119 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600120
121 /*
122 * This is used for the VBE VPL tests. The MMC device holds the
123 * binman image.bin file. The test progresses through each phase
124 * of U-Boot, loading each in turn from MMC.
125 *
126 * Note that the test enables this node (and mmc3) before
127 * running U-Boot
128 */
129 firmware1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700130 bootph-verify;
Simon Glass77bec9e2022-10-20 18:23:20 -0600131 status = "disabled";
132 compatible = "fwupd,vbe-simple";
133 storage = "mmc3";
Simon Glass74b75aa2023-04-02 14:01:24 +1200134 skip-offset = <0x800000>;
Simon Glass77bec9e2022-10-20 18:23:20 -0600135 area-start = <0>;
136 area-size = <0xe00000>;
137 state-offset = <0xdffc00>;
138 state-size = <0x40>;
139 version-offset = <0xdffe00>;
140 version-size = <0x100>;
141 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600142 };
143
Andrew Scull0518e7a2022-05-30 10:00:12 +0000144 fuzzing-engine {
145 compatible = "sandbox,fuzzing-engine";
146 };
147
Nandor Hanf9db2f12021-06-10 16:56:44 +0300148 reboot-mode0 {
149 compatible = "reboot-mode-gpio";
150 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
151 u-boot,env-variable = "bootstatus";
152 mode-test = <0x01>;
153 mode-download = <0x03>;
154 };
155
Nandor Hanc74675b2021-06-10 16:56:45 +0300156 reboot_mode1: reboot-mode@14 {
157 compatible = "reboot-mode-rtc";
158 rtc = <&rtc_0>;
159 reg = <0x30 4>;
160 u-boot,env-variable = "bootstatus";
161 big-endian;
162 mode-test = <0x21969147>;
163 mode-download = <0x51939147>;
164 };
165
Simon Glassce6d99a2018-12-10 10:37:33 -0700166 audio: audio-codec {
167 compatible = "sandbox,audio-codec";
168 #sound-dai-cells = <1>;
169 };
170
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200171 buttons {
172 compatible = "gpio-keys";
173
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200174 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200175 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200176 label = "button1";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300177 linux,code = <BTN_1>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200178 };
179
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200180 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200181 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200182 label = "button2";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300183 linux,code = <BTN_2>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200184 };
185 };
186
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100187 buttons2 {
188 compatible = "adc-keys";
189 io-channels = <&adc 3>;
190 keyup-threshold-microvolt = <3000000>;
191
192 button-up {
193 label = "button3";
194 linux,code = <KEY_F3>;
195 press-threshold-microvolt = <1500000>;
196 };
197
198 button-down {
199 label = "button4";
200 linux,code = <KEY_F4>;
201 press-threshold-microvolt = <1000000>;
202 };
203
204 button-enter {
205 label = "button5";
206 linux,code = <KEY_F5>;
207 press-threshold-microvolt = <500000>;
208 };
209 };
210
Simon Glasse96fa6c2018-12-10 10:37:34 -0700211 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600212 reg = <0 0>;
213 compatible = "google,cros-ec-sandbox";
214
215 /*
216 * This describes the flash memory within the EC. Note
217 * that the STM32L flash erases to 0, not 0xff.
218 */
219 flash {
220 image-pos = <0x08000000>;
221 size = <0x20000>;
222 erase-value = <0>;
223
224 /* Information for sandbox */
225 ro {
226 image-pos = <0>;
227 size = <0xf000>;
228 };
229 wp-ro {
230 image-pos = <0xf000>;
231 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700232 used = <0x884>;
233 compress = "lz4";
234 uncomp-size = <0xcf8>;
235 hash {
236 algo = "sha256";
237 value = [00 01 02 03 04 05 06 07
238 08 09 0a 0b 0c 0d 0e 0f
239 10 11 12 13 14 15 16 17
240 18 19 1a 1b 1c 1d 1e 1f];
241 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600242 };
243 rw {
244 image-pos = <0x10000>;
245 size = <0x10000>;
246 };
247 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300248
249 cros_ec_pwm: cros-ec-pwm {
250 compatible = "google,cros-ec-pwm";
251 #pwm-cells = <1>;
252 };
253
Simon Glasse6c5c942018-10-01 12:22:08 -0600254 };
255
Yannick Fertré23f965a2019-10-07 15:29:05 +0200256 dsi_host: dsi_host {
257 compatible = "sandbox,dsi-host";
258 };
259
Simon Glass2e7d35d2014-02-26 15:59:21 -0700260 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600261 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700262 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600263 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700264 ping-add = <0>;
Simon Glass8c103c32023-02-13 08:56:33 -0700265 bootph-all;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100266 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
267 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700268 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100269 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
270 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
271 <&gpio_b 7 GPIO_IN 3 2 1>,
272 <&gpio_b 8 GPIO_OUT 3 2 1>,
273 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100274 test3-gpios =
275 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
276 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
277 <&gpio_c 2 GPIO_OUT>,
278 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
279 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200280 <&gpio_c 5 GPIO_IN>,
281 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
282 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530283 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
284 test5-gpios = <&gpio_a 19>;
285
Simon Glassfb933d02021-10-23 17:26:04 -0600286 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200287 int8-value = /bits/ 8 <0x12>;
288 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700289 int-value = <1234>;
290 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200291 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200292 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600293 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700294 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600295 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200296 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530297
298 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
299 <&muxcontroller0 2>, <&muxcontroller0 3>,
300 <&muxcontroller1>;
301 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
302 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100303 display-timings {
304 timing0: 240x320 {
305 clock-frequency = <6500000>;
306 hactive = <240>;
307 vactive = <320>;
308 hfront-porch = <6>;
309 hback-porch = <7>;
310 hsync-len = <1>;
311 vback-porch = <5>;
312 vfront-porch = <8>;
313 vsync-len = <2>;
314 hsync-active = <1>;
315 vsync-active = <0>;
316 de-active = <1>;
317 pixelclk-active = <1>;
318 interlaced;
319 doublescan;
320 doubleclk;
321 };
322 timing1: 480x800 {
323 clock-frequency = <9000000>;
324 hactive = <480>;
325 vactive = <800>;
326 hfront-porch = <10>;
327 hback-porch = <59>;
328 hsync-len = <12>;
329 vback-porch = <15>;
330 vfront-porch = <17>;
331 vsync-len = <16>;
332 hsync-active = <0>;
333 vsync-active = <1>;
334 de-active = <0>;
335 pixelclk-active = <0>;
336 };
337 timing2: 800x480 {
338 clock-frequency = <33500000>;
339 hactive = <800>;
340 vactive = <480>;
341 hback-porch = <89>;
342 hfront-porch = <164>;
343 vback-porch = <23>;
344 vfront-porch = <10>;
345 hsync-len = <11>;
346 vsync-len = <13>;
347 };
348 };
Raphael Gallais-Poucd880582023-05-11 16:36:52 +0200349 panel-timing {
Nikhil M Jain2f3d6a42023-01-31 15:35:15 +0530350 clock-frequency = <6500000>;
351 hactive = <240>;
352 vactive = <320>;
353 hfront-porch = <6>;
354 hback-porch = <7>;
355 hsync-len = <1>;
356 vback-porch = <5>;
357 vfront-porch = <8>;
358 vsync-len = <2>;
359 hsync-active = <1>;
360 vsync-active = <0>;
361 de-active = <1>;
362 pixelclk-active = <1>;
363 interlaced;
364 doublescan;
365 doubleclk;
366 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700367 };
368
369 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600370 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700371 compatible = "not,compatible";
372 };
373
374 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600375 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700376 };
377
Simon Glass5d9a88f2018-10-01 12:22:40 -0600378 backlight: backlight {
379 compatible = "pwm-backlight";
380 enable-gpios = <&gpio_a 1>;
381 power-supply = <&ldo_1>;
382 pwms = <&pwm 0 1000>;
383 default-brightness-level = <5>;
384 brightness-levels = <0 16 32 64 128 170 202 234 255>;
385 };
386
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200387 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200388 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200389 bind-test-child1 {
390 compatible = "sandbox,phy";
391 #phy-cells = <1>;
392 };
393
394 bind-test-child2 {
395 compatible = "simple-bus";
396 };
397 };
398
Simon Glass2e7d35d2014-02-26 15:59:21 -0700399 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600400 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700401 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600402 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700403 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530404
405 mux-controls = <&muxcontroller0 0>;
406 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700407 };
408
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200409 phy_provider0: gen_phy@0 {
410 compatible = "sandbox,phy";
411 #phy-cells = <1>;
412 };
413
414 phy_provider1: gen_phy@1 {
415 compatible = "sandbox,phy";
416 #phy-cells = <0>;
417 broken;
418 };
419
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200420 phy_provider2: gen_phy@2 {
421 compatible = "sandbox,phy";
422 #phy-cells = <0>;
423 };
424
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200425 gen_phy_user: gen_phy_user {
426 compatible = "simple-bus";
427 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
428 phy-names = "phy1", "phy2", "phy3";
429 };
430
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200431 gen_phy_user1: gen_phy_user1 {
432 compatible = "simple-bus";
433 phys = <&phy_provider0 0>, <&phy_provider2>;
434 phy-names = "phy1", "phy2";
435 };
436
Simon Glass2e7d35d2014-02-26 15:59:21 -0700437 some-bus {
438 #address-cells = <1>;
439 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600440 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600441 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600442 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700443 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600444 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700445 compatible = "denx,u-boot-fdt-test";
446 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600447 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700448 ping-add = <5>;
449 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600450 c-test@0 {
451 compatible = "denx,u-boot-fdt-test";
452 reg = <0>;
453 ping-expect = <6>;
454 ping-add = <6>;
455 };
456 c-test@1 {
457 compatible = "denx,u-boot-fdt-test";
458 reg = <1>;
459 ping-expect = <7>;
460 ping-add = <7>;
461 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700462 };
463
464 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600465 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600466 ping-expect = <6>;
467 ping-add = <6>;
468 compatible = "google,another-fdt-test";
469 };
470
471 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600472 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600473 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700474 ping-add = <6>;
475 compatible = "google,another-fdt-test";
476 };
477
Simon Glass9cc36a22015-01-25 08:27:05 -0700478 f-test {
479 compatible = "denx,u-boot-fdt-test";
480 };
481
482 g-test {
483 compatible = "denx,u-boot-fdt-test";
484 };
485
Bin Meng2786cd72018-10-10 22:07:01 -0700486 h-test {
487 compatible = "denx,u-boot-fdt-test1";
488 };
489
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200490 i-test {
491 compatible = "mediatek,u-boot-fdt-test";
492 #address-cells = <1>;
493 #size-cells = <0>;
494
495 subnode@0 {
496 reg = <0>;
497 };
498
499 subnode@1 {
500 reg = <1>;
501 };
502
503 subnode@2 {
504 reg = <2>;
505 };
506 };
507
Simon Glassdc12ebb2019-12-29 21:19:25 -0700508 devres-test {
509 compatible = "denx,u-boot-devres-test";
510 };
511
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530512 another-test {
513 reg = <0 2>;
514 compatible = "denx,u-boot-fdt-test";
515 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
516 test5-gpios = <&gpio_a 19>;
517 };
518
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100519 mmio-bus@0 {
520 #address-cells = <1>;
521 #size-cells = <1>;
522 compatible = "denx,u-boot-test-bus";
523 dma-ranges = <0x10000000 0x00000000 0x00040000>;
524
525 subnode@0 {
526 compatible = "denx,u-boot-fdt-test";
527 };
528 };
529
530 mmio-bus@1 {
531 #address-cells = <1>;
532 #size-cells = <1>;
533 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100534
535 subnode@0 {
536 compatible = "denx,u-boot-fdt-test";
537 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100538 };
539
Simon Glass0f7b1112020-07-07 13:12:06 -0600540 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600541 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600542 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600543 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600544 child {
545 compatible = "denx,u-boot-acpi-test";
546 };
Simon Glassf50cc952020-04-08 16:57:34 -0600547 };
548
Simon Glass0f7b1112020-07-07 13:12:06 -0600549 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600550 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600551 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600552 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600553 };
554
Patrice Chotardee87a092017-09-04 14:55:57 +0200555 clocks {
556 clk_fixed: clk-fixed {
557 compatible = "fixed-clock";
558 #clock-cells = <0>;
559 clock-frequency = <1234>;
560 };
Anup Patelb630d572019-02-25 08:14:55 +0000561
562 clk_fixed_factor: clk-fixed-factor {
563 compatible = "fixed-factor-clock";
564 #clock-cells = <0>;
565 clock-div = <3>;
566 clock-mult = <2>;
567 clocks = <&clk_fixed>;
568 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200569
570 osc {
571 compatible = "fixed-clock";
572 #clock-cells = <0>;
573 clock-frequency = <20000000>;
574 };
Stephen Warren135aa952016-06-17 09:44:00 -0600575 };
576
577 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600578 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600579 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200580 assigned-clocks = <&clk_sandbox 3>;
581 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600582 };
583
584 clk-test {
585 compatible = "sandbox,clk-test";
586 clocks = <&clk_fixed>,
587 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200588 <&clk_sandbox 0>,
589 <&clk_sandbox 3>,
590 <&clk_sandbox 2>;
591 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600592 };
593
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200594 ccf: clk-ccf {
595 compatible = "sandbox,clk-ccf";
596 };
597
Simon Glass42b7f422021-12-04 08:56:31 -0700598 efi-media {
599 compatible = "sandbox,efi-media";
600 };
601
Simon Glass171e9912015-05-22 15:42:15 -0600602 eth@10002000 {
603 compatible = "sandbox,eth";
604 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600605 };
606
607 eth_5: eth@10003000 {
608 compatible = "sandbox,eth";
609 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400610 nvmem-cells = <&eth5_addr>;
611 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600612 };
613
Bin Meng71d79712015-08-27 22:25:53 -0700614 eth_3: sbe5 {
615 compatible = "sandbox,eth";
616 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400617 nvmem-cells = <&eth3_addr>;
618 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700619 };
620
Simon Glass171e9912015-05-22 15:42:15 -0600621 eth@10004000 {
622 compatible = "sandbox,eth";
623 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600624 };
625
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200626 phy_eth0: phy-test-eth {
627 compatible = "sandbox,eth";
628 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400629 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200630 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200631 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200632 };
633
Claudiu Manoilff98da02021-03-14 20:14:57 +0800634 dsa_eth0: dsa-test-eth {
635 compatible = "sandbox,eth";
636 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400637 nvmem-cells = <&eth4_addr>;
638 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800639 };
640
641 dsa-test {
642 compatible = "sandbox,dsa";
643
644 ports {
645 #address-cells = <1>;
646 #size-cells = <0>;
647 swp_0: port@0 {
648 reg = <0>;
649 label = "lan0";
650 phy-mode = "rgmii-rxid";
651
652 fixed-link {
653 speed = <100>;
654 full-duplex;
655 };
656 };
657
658 swp_1: port@1 {
659 reg = <1>;
660 label = "lan1";
661 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800662 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800663 };
664
665 port@2 {
666 reg = <2>;
667 ethernet = <&dsa_eth0>;
668
669 fixed-link {
670 speed = <1000>;
671 full-duplex;
672 };
673 };
674 };
675 };
676
Rajan Vaja31b82172018-09-19 03:43:46 -0700677 firmware {
678 sandbox_firmware: sandbox-firmware {
679 compatible = "sandbox,firmware";
680 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200681
Etienne Carriere41d62e22022-02-21 09:22:39 +0100682 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200683 compatible = "sandbox,scmi-agent";
684 #address-cells = <1>;
685 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200686
Etienne Carriere41d62e22022-02-21 09:22:39 +0100687 protocol@10 {
688 reg = <0x10>;
689 };
690
691 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200692 reg = <0x14>;
693 #clock-cells = <1>;
694 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200695
Etienne Carriere41d62e22022-02-21 09:22:39 +0100696 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200697 reg = <0x16>;
698 #reset-cells = <1>;
699 };
Etienne Carriere01242182021-03-08 22:38:07 +0100700
701 protocol@17 {
702 reg = <0x17>;
703
704 regulators {
705 #address-cells = <1>;
706 #size-cells = <0>;
707
Etienne Carriere41d62e22022-02-21 09:22:39 +0100708 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100709 reg = <0>;
710 regulator-name = "sandbox-voltd0";
711 regulator-min-microvolt = <1100000>;
712 regulator-max-microvolt = <3300000>;
713 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100714 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100715 reg = <0x1>;
716 regulator-name = "sandbox-voltd1";
717 regulator-min-microvolt = <1800000>;
718 };
719 };
720 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200721 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700722 };
723
Alexander Dahl1323d082022-09-30 14:04:30 +0200724 fpga {
725 compatible = "sandbox,fpga";
726 };
727
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100728 pinctrl-gpio {
729 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700730
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100731 gpio_a: base-gpios {
732 compatible = "sandbox,gpio";
733 gpio-controller;
734 #gpio-cells = <1>;
735 gpio-bank-name = "a";
736 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200737 hog_input_active_low {
738 gpio-hog;
739 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200740 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200741 };
742 hog_input_active_high {
743 gpio-hog;
744 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200745 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200746 };
747 hog_output_low {
748 gpio-hog;
749 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200750 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200751 };
752 hog_output_high {
753 gpio-hog;
754 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200755 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200756 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100757 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600758
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100759 gpio_b: extra-gpios {
760 compatible = "sandbox,gpio";
761 gpio-controller;
762 #gpio-cells = <5>;
763 gpio-bank-name = "b";
764 sandbox,gpio-count = <10>;
765 };
766
767 gpio_c: pinmux-gpios {
768 compatible = "sandbox,gpio";
769 gpio-controller;
770 #gpio-cells = <2>;
771 gpio-bank-name = "c";
772 sandbox,gpio-count = <10>;
773 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100774 };
775
Simon Glassecc2ed52014-12-10 08:55:55 -0700776 i2c@0 {
777 #address-cells = <1>;
778 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600779 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700780 compatible = "sandbox,i2c";
781 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200782 pinctrl-names = "default";
783 pinctrl-0 = <&pinmux_i2c0_pins>;
784
Simon Glassecc2ed52014-12-10 08:55:55 -0700785 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400786 #address-cells = <1>;
787 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700788 reg = <0x2c>;
789 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700790 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200791 partitions {
792 compatible = "fixed-partitions";
793 #address-cells = <1>;
794 #size-cells = <1>;
795 bootcount_i2c: bootcount@10 {
796 reg = <10 2>;
797 };
798 };
Sean Anderson472caa62022-05-05 13:11:42 -0400799
800 eth3_addr: mac-address@24 {
801 reg = <24 6>;
802 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700803 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200804
Simon Glass52d3bc52015-05-22 15:42:17 -0600805 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400806 #address-cells = <1>;
807 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600808 reg = <0x43>;
809 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700810 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400811
812 eth4_addr: mac-address@40 {
813 reg = <0x40 6>;
814 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600815 };
816
817 rtc_1: rtc@61 {
818 reg = <0x61>;
819 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700820 sandbox,emul = <&emul1>;
821 };
822
823 i2c_emul: emul {
824 reg = <0xff>;
825 compatible = "sandbox,i2c-emul-parent";
826 emul_eeprom: emul-eeprom {
827 compatible = "sandbox,i2c-eeprom";
828 sandbox,filename = "i2c.bin";
829 sandbox,size = <256>;
830 };
831 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700832 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700833 };
834 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700835 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600836 };
837 };
838
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200839 sandbox_pmic: sandbox_pmic {
840 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700841 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200842 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200843
844 mc34708: pmic@41 {
845 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700846 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200847 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700848 };
849
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100850 bootcount@0 {
851 compatible = "u-boot,bootcount-rtc";
852 rtc = <&rtc_1>;
853 offset = <0x13>;
854 };
855
Michal Simekf692b472020-05-28 11:48:55 +0200856 bootcount {
857 compatible = "u-boot,bootcount-i2c-eeprom";
858 i2c-eeprom = <&bootcount_i2c>;
859 };
860
Nandor Hanc50b21b2021-06-10 15:40:38 +0300861 bootcount_4@0 {
862 compatible = "u-boot,bootcount-syscon";
863 syscon = <&syscon0>;
864 reg = <0x0 0x04>, <0x0 0x04>;
865 reg-names = "syscon_reg", "offset";
866 };
867
868 bootcount_2@0 {
869 compatible = "u-boot,bootcount-syscon";
870 syscon = <&syscon0>;
871 reg = <0x0 0x04>, <0x0 0x02> ;
872 reg-names = "syscon_reg", "offset";
873 };
874
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100875 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100876 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100877 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100878 vdd-supply = <&buck2>;
879 vss-microvolts = <0>;
880 };
881
Mark Kettenisfb574622021-10-23 16:58:02 +0200882 iommu: iommu@0 {
883 compatible = "sandbox,iommu";
884 #iommu-cells = <0>;
885 };
886
Simon Glass02554352020-02-06 09:55:00 -0700887 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700888 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700889 interrupt-controller;
890 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700891 };
892
Simon Glass3c97c4f2016-01-18 19:52:26 -0700893 lcd {
Simon Glass8c103c32023-02-13 08:56:33 -0700894 bootph-all;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700895 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200896 pinctrl-names = "default";
897 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700898 xres = <1366>;
899 yres = <768>;
900 };
901
Simon Glass3c43fba2015-07-06 12:54:34 -0600902 leds {
903 compatible = "gpio-leds";
904
905 iracibble {
906 gpios = <&gpio_a 1 0>;
907 label = "sandbox:red";
908 };
909
910 martinet {
911 gpios = <&gpio_a 2 0>;
912 label = "sandbox:green";
913 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200914
915 default_on {
916 gpios = <&gpio_a 5 0>;
917 label = "sandbox:default_on";
918 default-state = "on";
919 };
920
921 default_off {
922 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400923 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200924 default-state = "off";
925 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600926 };
927
Paul Doelle1fc45d62022-07-04 09:00:25 +0000928 wdt-gpio-toggle {
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200929 gpios = <&gpio_a 7 0>;
930 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200931 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000932 hw_algo = "toggle";
933 always-running;
934 };
935
936 wdt-gpio-level {
937 gpios = <&gpio_a 7 0>;
938 compatible = "linux,wdt-gpio";
939 hw_margin_ms = <100>;
940 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200941 always-running;
942 };
943
Stephen Warren8961b522016-05-16 17:41:37 -0600944 mbox: mbox {
945 compatible = "sandbox,mbox";
946 #mbox-cells = <1>;
947 };
948
949 mbox-test {
950 compatible = "sandbox,mbox-test";
951 mboxes = <&mbox 100>, <&mbox 1>;
952 mbox-names = "other", "test";
953 };
954
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900955 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200956 #address-cells = <1>;
957 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400958 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200959 cpu1: cpu@1 {
960 device_type = "cpu";
961 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400962 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900963 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700964 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900965 };
Mario Sixfa44b532018-08-06 10:23:44 +0200966
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200967 cpu2: cpu@2 {
968 device_type = "cpu";
969 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900970 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700971 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900972 };
Mario Sixfa44b532018-08-06 10:23:44 +0200973
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200974 cpu3: cpu@3 {
975 device_type = "cpu";
976 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900977 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700978 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900979 };
Mario Sixfa44b532018-08-06 10:23:44 +0200980 };
981
Dave Gerlach21e3c212020-07-15 23:39:58 -0500982 chipid: chipid {
983 compatible = "sandbox,soc";
984 };
985
Simon Glasse96fa6c2018-12-10 10:37:34 -0700986 i2s: i2s {
987 compatible = "sandbox,i2s";
988 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700989 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700990 };
991
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200992 nop-test_0 {
993 compatible = "sandbox,nop_sandbox1";
994 nop-test_1 {
995 compatible = "sandbox,nop_sandbox2";
996 bind = "True";
997 };
998 nop-test_2 {
999 compatible = "sandbox,nop_sandbox2";
1000 bind = "False";
1001 };
1002 };
1003
Roger Quadros2c120372022-10-20 16:30:46 +03001004 memory-controller {
1005 compatible = "sandbox,memory";
1006 };
1007
Mario Six004e67c2018-07-31 14:24:14 +02001008 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -04001009 #address-cells = <1>;
1010 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +02001011 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -04001012
1013 eth5_addr: mac-address@10 {
1014 reg = <0x10 6>;
1015 };
Mario Six004e67c2018-07-31 14:24:14 +02001016 };
1017
Simon Glasse48eeb92017-04-23 20:02:07 -06001018 mmc2 {
1019 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -06001020 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -06001021 };
1022
Simon Glassfb1451b2022-04-24 23:31:24 -06001023 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001024 mmc1 {
1025 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001026 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001027 };
1028
Simon Glassfb1451b2022-04-24 23:31:24 -06001029 /* This is used for the fastboot tests */
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301030 mmc0: mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001031 compatible = "sandbox,mmc";
1032 };
1033
Simon Glass77bec9e2022-10-20 18:23:20 -06001034 /* This is used for VBE VPL tests */
1035 mmc3 {
1036 status = "disabled";
1037 compatible = "sandbox,mmc";
1038 filename = "image.bin";
1039 non-removable;
1040 };
1041
Simon Glassd985f1d2023-01-06 08:52:41 -06001042 /* This is used for bootstd bootmenu tests */
1043 mmc4 {
1044 status = "disabled";
1045 compatible = "sandbox,mmc";
1046 filename = "mmc4.img";
1047 };
1048
Simon Glassb45c8332019-02-16 20:24:50 -07001049 pch {
1050 compatible = "sandbox,pch";
1051 };
1052
Tom Rini42c64d12020-02-11 12:41:23 -05001053 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001054 compatible = "sandbox,pci";
1055 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001056 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001057 #address-cells = <3>;
1058 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001059 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001060 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis08386da2023-01-21 20:27:57 +01001061 iommu-map = <0x0010 &iommu 0 1>;
1062 iommu-map-mask = <0xfffffff8>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001063 pci@0,0 {
1064 compatible = "pci-generic";
1065 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001066 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001067 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001068 pci@1,0 {
1069 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001070 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1071 reg = <0x02000814 0 0 0 0
1072 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001073 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001074 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001075 p2sb-pci@2,0 {
1076 compatible = "sandbox,p2sb";
1077 reg = <0x02001010 0 0 0 0>;
1078 sandbox,emul = <&p2sb_emul>;
1079
1080 adder {
1081 intel,p2sb-port-id = <3>;
1082 compatible = "sandbox,adder";
1083 };
1084 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001085 pci@1e,0 {
1086 compatible = "sandbox,pmc";
1087 reg = <0xf000 0 0 0 0>;
1088 sandbox,emul = <&pmc_emul1e>;
1089 acpi-base = <0x400>;
1090 gpe0-dwx-mask = <0xf>;
1091 gpe0-dwx-shift-base = <4>;
1092 gpe0-dw = <6 7 9>;
1093 gpe0-sts = <0x20>;
1094 gpe0-en = <0x30>;
1095 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001096 pci@1f,0 {
1097 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001098 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1099 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001100 sandbox,emul = <&swap_case_emul0_1f>;
1101 };
1102 };
1103
1104 pci-emul0 {
1105 compatible = "sandbox,pci-emul-parent";
1106 swap_case_emul0_0: emul0@0,0 {
1107 compatible = "sandbox,swap-case";
1108 };
1109 swap_case_emul0_1: emul0@1,0 {
1110 compatible = "sandbox,swap-case";
1111 use-ea;
1112 };
1113 swap_case_emul0_1f: emul0@1f,0 {
1114 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001115 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001116 p2sb_emul: emul@2,0 {
1117 compatible = "sandbox,p2sb-emul";
1118 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001119 pmc_emul1e: emul@1e,0 {
1120 compatible = "sandbox,pmc-emul";
1121 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001122 };
1123
Tom Rini42c64d12020-02-11 12:41:23 -05001124 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001125 compatible = "sandbox,pci";
1126 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001127 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001128 #address-cells = <3>;
1129 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001130 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001131 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001132 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001133 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001134 0x0c 0x00 0x1234 0x5678
1135 0x10 0x00 0x1234 0x5678>;
1136 pci@10,0 {
1137 reg = <0x8000 0 0 0 0>;
1138 };
Bin Mengdee4d752018-08-03 01:14:41 -07001139 };
1140
Tom Rini42c64d12020-02-11 12:41:23 -05001141 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001142 compatible = "sandbox,pci";
1143 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001144 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001145 #address-cells = <3>;
1146 #size-cells = <2>;
1147 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1148 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1149 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1150 pci@1f,0 {
1151 compatible = "pci-generic";
1152 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001153 sandbox,emul = <&swap_case_emul2_1f>;
1154 };
1155 };
1156
1157 pci-emul2 {
1158 compatible = "sandbox,pci-emul-parent";
1159 swap_case_emul2_1f: emul2@1f,0 {
1160 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001161 };
1162 };
1163
Ramon Friedbb413332019-04-27 11:15:23 +03001164 pci_ep: pci_ep {
1165 compatible = "sandbox,pci_ep";
1166 };
1167
Simon Glass98561572017-04-23 20:10:44 -06001168 probing {
1169 compatible = "simple-bus";
1170 test1 {
1171 compatible = "denx,u-boot-probe-test";
1172 };
1173
1174 test2 {
1175 compatible = "denx,u-boot-probe-test";
1176 };
1177
1178 test3 {
1179 compatible = "denx,u-boot-probe-test";
1180 };
1181
1182 test4 {
1183 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001184 first-syscon = <&syscon0>;
1185 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001186 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001187 };
1188 };
1189
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001190 pwrdom: power-domain {
1191 compatible = "sandbox,power-domain";
1192 #power-domain-cells = <1>;
1193 };
1194
1195 power-domain-test {
1196 compatible = "sandbox,power-domain-test";
1197 power-domains = <&pwrdom 2>;
1198 };
1199
Simon Glass5d9a88f2018-10-01 12:22:40 -06001200 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001201 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001202 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001203 pinctrl-names = "default";
1204 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001205 };
1206
1207 pwm2 {
1208 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001209 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001210 };
1211
Simon Glass64ce0ca2015-07-06 12:54:31 -06001212 ram {
1213 compatible = "sandbox,ram";
1214 };
1215
Simon Glass5010d982015-07-06 12:54:29 -06001216 reset@0 {
1217 compatible = "sandbox,warm-reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001218 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001219 };
1220
1221 reset@1 {
1222 compatible = "sandbox,reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001223 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001224 };
1225
Stephen Warren4581b712016-06-17 09:43:59 -06001226 resetc: reset-ctl {
1227 compatible = "sandbox,reset-ctl";
1228 #reset-cells = <1>;
1229 };
1230
1231 reset-ctl-test {
1232 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001233 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1234 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001235 };
1236
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301237 rng {
1238 compatible = "sandbox,sandbox-rng";
1239 };
1240
Nishanth Menon52159402015-09-17 15:42:41 -05001241 rproc_1: rproc@1 {
1242 compatible = "sandbox,test-processor";
1243 remoteproc-name = "remoteproc-test-dev1";
1244 };
1245
1246 rproc_2: rproc@2 {
1247 compatible = "sandbox,test-processor";
1248 internal-memory-mapped;
1249 remoteproc-name = "remoteproc-test-dev2";
1250 };
1251
Simon Glass5d9a88f2018-10-01 12:22:40 -06001252 panel {
1253 compatible = "simple-panel";
1254 backlight = <&backlight 0 100>;
1255 };
1256
Simon Glass22c80d52022-09-21 16:21:47 +02001257 scsi {
1258 compatible = "sandbox,scsi";
1259 sandbox,filepath = "scsi.img";
1260 };
1261
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001262 smem@0 {
1263 compatible = "sandbox,smem";
1264 };
1265
Simon Glassd4901892018-12-10 10:37:36 -07001266 sound {
1267 compatible = "sandbox,sound";
1268 cpu {
1269 sound-dai = <&i2s 0>;
1270 };
1271
1272 codec {
1273 sound-dai = <&audio 0>;
1274 };
1275 };
1276
Simon Glass0ae0cb72014-10-13 23:42:11 -06001277 spi@0 {
1278 #address-cells = <1>;
1279 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001280 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001281 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001282 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001283 pinctrl-names = "default";
1284 pinctrl-0 = <&pinmux_spi0_pins>;
1285
Simon Glass0ae0cb72014-10-13 23:42:11 -06001286 spi.bin@0 {
1287 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001288 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001289 spi-max-frequency = <40000000>;
1290 sandbox,filename = "spi.bin";
1291 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001292 spi.bin@1 {
1293 reg = <1>;
1294 compatible = "spansion,m25p16", "jedec,spi-nor";
1295 spi-max-frequency = <50000000>;
1296 sandbox,filename = "spi.bin";
1297 spi-cpol;
1298 spi-cpha;
1299 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001300 };
1301
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001302 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001303 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001304 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001305 };
1306
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001307 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001308 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001309 reg = <0x20 5
1310 0x28 6
1311 0x30 7
1312 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001313 };
1314
Patrick Delaunaya442e612019-03-07 09:57:13 +01001315 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001316 compatible = "simple-mfd", "syscon";
1317 reg = <0x40 5
1318 0x48 6
1319 0x50 7
1320 0x58 8>;
1321 };
1322
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301323 syscon3: syscon@3 {
1324 compatible = "simple-mfd", "syscon";
1325 reg = <0x000100 0x10>;
1326
1327 muxcontroller0: a-mux-controller {
1328 compatible = "mmio-mux";
1329 #mux-control-cells = <1>;
1330
1331 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1332 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1333 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1334 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1335 u-boot,mux-autoprobe;
1336 };
1337 };
1338
1339 muxcontroller1: emul-mux-controller {
1340 compatible = "mux-emul";
1341 #mux-control-cells = <0>;
1342 u-boot,mux-autoprobe;
1343 idle-state = <0xabcd>;
1344 };
1345
Simon Glass93f44e82020-12-16 21:20:27 -07001346 testfdtm0 {
1347 compatible = "denx,u-boot-fdtm-test";
1348 };
1349
1350 testfdtm1: testfdtm1 {
1351 compatible = "denx,u-boot-fdtm-test";
1352 };
1353
1354 testfdtm2 {
1355 compatible = "denx,u-boot-fdtm-test";
1356 };
1357
Sean Anderson7616e362020-09-28 10:52:23 -04001358 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001359 compatible = "sandbox,timer";
1360 clock-frequency = <1000000>;
1361 };
1362
Sean Anderson7616e362020-09-28 10:52:23 -04001363 timer@1 {
1364 compatible = "sandbox,timer";
1365 sandbox,timebase-frequency-fallback;
1366 };
1367
Miquel Raynalb91ad162018-05-15 11:57:27 +02001368 tpm2 {
1369 compatible = "sandbox,tpm2";
1370 };
1371
Simon Glass4fef6572023-02-21 06:24:51 -07001372 tpm {
1373 compatible = "google,sandbox-tpm";
1374 };
1375
Simon Glass171e9912015-05-22 15:42:15 -06001376 uart0: serial {
1377 compatible = "sandbox,serial";
Simon Glass8c103c32023-02-13 08:56:33 -07001378 bootph-all;
Dario Binacchi55322622021-04-11 09:39:50 +02001379 pinctrl-names = "default";
1380 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001381 };
1382
Simon Glasse00cb222015-03-25 12:23:05 -06001383 usb_0: usb@0 {
1384 compatible = "sandbox,usb";
1385 status = "disabled";
1386 hub {
1387 compatible = "sandbox,usb-hub";
1388 #address-cells = <1>;
1389 #size-cells = <0>;
1390 flash-stick {
1391 reg = <0>;
1392 compatible = "sandbox,usb-flash";
1393 };
1394 };
1395 };
1396
1397 usb_1: usb@1 {
1398 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001399 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001400 hub {
1401 compatible = "usb-hub";
1402 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001403 #address-cells = <1>;
1404 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001405 hub-emul {
1406 compatible = "sandbox,usb-hub";
1407 #address-cells = <1>;
1408 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001409 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001410 reg = <0>;
1411 compatible = "sandbox,usb-flash";
1412 sandbox,filepath = "testflash.bin";
1413 };
1414
Simon Glass431cbd62015-11-08 23:48:01 -07001415 flash-stick@1 {
1416 reg = <1>;
1417 compatible = "sandbox,usb-flash";
1418 sandbox,filepath = "testflash1.bin";
1419 };
1420
1421 flash-stick@2 {
1422 reg = <2>;
1423 compatible = "sandbox,usb-flash";
1424 sandbox,filepath = "testflash2.bin";
1425 };
1426
Simon Glassbff1a712015-11-08 23:48:08 -07001427 keyb@3 {
1428 reg = <3>;
1429 compatible = "sandbox,usb-keyb";
1430 };
1431
Simon Glasse00cb222015-03-25 12:23:05 -06001432 };
Michael Wallec03b7612020-06-02 01:47:07 +02001433
1434 usbstor@1 {
1435 reg = <1>;
1436 };
1437 usbstor@3 {
1438 reg = <3>;
1439 };
Simon Glasse00cb222015-03-25 12:23:05 -06001440 };
1441 };
1442
1443 usb_2: usb@2 {
1444 compatible = "sandbox,usb";
1445 status = "disabled";
1446 };
1447
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001448 spmi: spmi@0 {
1449 compatible = "sandbox,spmi";
1450 #address-cells = <0x1>;
1451 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001452 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001453 pm8916@0 {
1454 compatible = "qcom,spmi-pmic";
1455 reg = <0x0 0x1>;
1456 #address-cells = <0x1>;
1457 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001458 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001459
1460 spmi_gpios: gpios@c000 {
1461 compatible = "qcom,pm8916-gpio";
1462 reg = <0xc000 0x400>;
1463 gpio-controller;
1464 gpio-count = <4>;
1465 #gpio-cells = <2>;
1466 gpio-bank-name="spmi";
1467 };
1468 };
1469 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001470
1471 wdt0: wdt@0 {
1472 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001473 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001474 };
Rob Clarkf2006802018-01-10 11:33:30 +01001475
Mario Six957983e2018-08-09 14:51:19 +02001476 axi: axi@0 {
1477 compatible = "sandbox,axi";
1478 #address-cells = <0x1>;
1479 #size-cells = <0x1>;
1480 store@0 {
1481 compatible = "sandbox,sandbox_store";
1482 reg = <0x0 0x400>;
1483 };
1484 };
1485
Rob Clarkf2006802018-01-10 11:33:30 +01001486 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001487 #address-cells = <1>;
1488 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001489 setting = "sunrise ohoka";
1490 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001491 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001492 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001493 chosen-test {
1494 compatible = "denx,u-boot-fdt-test";
1495 reg = <9 1>;
1496 };
1497 };
Mario Sixe8d52912018-03-12 14:53:33 +01001498
1499 translation-test@8000 {
1500 compatible = "simple-bus";
1501 reg = <0x8000 0x4000>;
1502
1503 #address-cells = <0x2>;
1504 #size-cells = <0x1>;
1505
1506 ranges = <0 0x0 0x8000 0x1000
1507 1 0x100 0x9000 0x1000
1508 2 0x200 0xA000 0x1000
1509 3 0x300 0xB000 0x1000
1510 >;
1511
Fabien Dessenne641067f2019-05-31 15:11:30 +02001512 dma-ranges = <0 0x000 0x10000000 0x1000
1513 1 0x100 0x20000000 0x1000
1514 >;
1515
Mario Sixe8d52912018-03-12 14:53:33 +01001516 dev@0,0 {
1517 compatible = "denx,u-boot-fdt-dummy";
1518 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001519 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001520 };
1521
1522 dev@1,100 {
1523 compatible = "denx,u-boot-fdt-dummy";
1524 reg = <1 0x100 0x1000>;
1525
1526 };
1527
1528 dev@2,200 {
1529 compatible = "denx,u-boot-fdt-dummy";
1530 reg = <2 0x200 0x1000>;
1531 };
1532
1533
1534 noxlatebus@3,300 {
1535 compatible = "simple-bus";
1536 reg = <3 0x300 0x1000>;
1537
1538 #address-cells = <0x1>;
1539 #size-cells = <0x0>;
1540
1541 dev@42 {
1542 compatible = "denx,u-boot-fdt-dummy";
1543 reg = <0x42>;
1544 };
1545 };
1546 };
Mario Six4eea5312018-09-27 09:19:31 +02001547
Dzmitry Sankouski298ffdd2023-01-22 18:21:23 +03001548 ofnode-foreach {
1549 compatible = "foreach";
1550
1551 first {
1552 prop1 = <1>;
1553 prop2 = <2>;
1554 };
1555
1556 second {
1557 prop1 = <1>;
1558 prop2 = <2>;
1559 };
1560 };
1561
Mario Six4eea5312018-09-27 09:19:31 +02001562 osd {
1563 compatible = "sandbox,sandbox_osd";
1564 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001565
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001566 sandbox_tee {
1567 compatible = "sandbox,tee";
1568 };
Bin Meng4f89d492018-10-15 02:21:26 -07001569
1570 sandbox_virtio1 {
1571 compatible = "sandbox,virtio1";
Simon Glass00fc8ca2023-01-17 10:47:51 -07001572 virtio-type = <4>; /* rng */
Bin Meng4f89d492018-10-15 02:21:26 -07001573 };
1574
1575 sandbox_virtio2 {
1576 compatible = "sandbox,virtio2";
1577 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001578
Simon Glass00fc8ca2023-01-17 10:47:51 -07001579 sandbox-virtio-blk {
1580 compatible = "sandbox,virtio1";
1581 virtio-type = <2>; /* block */
1582 };
1583
Etienne Carriere87d4f272020-09-09 18:44:05 +02001584 sandbox_scmi {
1585 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001586 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001587 resets = <&reset_scmi 3>;
1588 regul0-supply = <&regul0_scmi>;
1589 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001590 };
1591
Patrice Chotardf41a8242018-10-24 14:10:23 +02001592 pinctrl {
1593 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001594
Sean Anderson7f0f1802020-09-14 11:01:57 -04001595 pinctrl-names = "default", "alternate";
1596 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1597 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001598
Sean Anderson7f0f1802020-09-14 11:01:57 -04001599 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001600 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001601 pins = "P5";
1602 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001603 bias-pull-up;
1604 input-disable;
1605 };
1606 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001607 pins = "P6";
1608 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001609 output-high;
1610 drive-open-drain;
1611 };
1612 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001613 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001614 bias-pull-down;
1615 input-enable;
1616 };
1617 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001618 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001619 bias-disable;
1620 };
1621 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001622
1623 pinctrl_i2c: i2c {
1624 groups {
1625 groups = "I2C_UART";
1626 function = "I2C";
1627 };
1628
1629 pins {
1630 pins = "P0", "P1";
1631 drive-open-drain;
1632 };
1633 };
1634
1635 pinctrl_i2s: i2s {
1636 groups = "SPI_I2S";
1637 function = "I2S";
1638 };
1639
1640 pinctrl_spi: spi {
1641 groups = "SPI_I2S";
1642 function = "SPI";
1643
1644 cs {
1645 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1646 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1647 };
1648 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001649 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001650
Dario Binacchi55322622021-04-11 09:39:50 +02001651 pinctrl-single-no-width {
1652 compatible = "pinctrl-single";
1653 reg = <0x0000 0x238>;
1654 #pinctrl-cells = <1>;
1655 pinctrl-single,function-mask = <0x7f>;
1656 };
1657
1658 pinctrl-single-pins {
1659 compatible = "pinctrl-single";
1660 reg = <0x0000 0x238>;
1661 #pinctrl-cells = <1>;
1662 pinctrl-single,register-width = <32>;
1663 pinctrl-single,function-mask = <0x7f>;
1664
1665 pinmux_pwm_pins: pinmux_pwm_pins {
1666 pinctrl-single,pins = < 0x48 0x06 >;
1667 };
1668
1669 pinmux_spi0_pins: pinmux_spi0_pins {
1670 pinctrl-single,pins = <
1671 0x190 0x0c
1672 0x194 0x0c
1673 0x198 0x23
1674 0x19c 0x0c
1675 >;
1676 };
1677
1678 pinmux_uart0_pins: pinmux_uart0_pins {
1679 pinctrl-single,pins = <
1680 0x70 0x30
1681 0x74 0x00
1682 >;
1683 };
1684 };
1685
1686 pinctrl-single-bits {
1687 compatible = "pinctrl-single";
1688 reg = <0x0000 0x50>;
1689 #pinctrl-cells = <2>;
1690 pinctrl-single,bit-per-mux;
1691 pinctrl-single,register-width = <32>;
1692 pinctrl-single,function-mask = <0xf>;
1693
1694 pinmux_i2c0_pins: pinmux_i2c0_pins {
1695 pinctrl-single,bits = <
1696 0x10 0x00002200 0x0000ff00
1697 >;
1698 };
1699
1700 pinmux_lcd_pins: pinmux_lcd_pins {
1701 pinctrl-single,bits = <
1702 0x40 0x22222200 0xffffff00
1703 0x44 0x22222222 0xffffffff
1704 0x48 0x00000022 0x000000ff
1705 0x48 0x02000000 0x0f000000
1706 0x4c 0x02000022 0x0f0000ff
1707 >;
1708 };
1709 };
1710
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001711 hwspinlock@0 {
1712 compatible = "sandbox,hwspinlock";
1713 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001714
1715 dma: dma {
1716 compatible = "sandbox,dma";
1717 #dma-cells = <1>;
1718
1719 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1720 dma-names = "m2m", "tx0", "rx0";
1721 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001722
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001723 /*
1724 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1725 * end of the test. If parent mdio is removed first, clean-up of the
1726 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1727 * active at the end of the test. That it turn doesn't allow the mdio
1728 * class to be destroyed, triggering an error.
1729 */
1730 mdio-mux-test {
1731 compatible = "sandbox,mdio-mux";
1732 #address-cells = <1>;
1733 #size-cells = <0>;
1734 mdio-parent-bus = <&mdio>;
1735
1736 mdio-ch-test@0 {
1737 reg = <0>;
1738 };
1739 mdio-ch-test@1 {
1740 reg = <1>;
1741 };
1742 };
1743
1744 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001745 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001746 #address-cells = <1>;
1747 #size-cells = <0>;
1748
1749 ethphy1: ethernet-phy@1 {
1750 reg = <1>;
1751 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001752 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001753
1754 pm-bus-test {
1755 compatible = "simple-pm-bus";
1756 clocks = <&clk_sandbox 4>;
1757 power-domains = <&pwrdom 1>;
1758 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001759
1760 resetc2: syscon-reset {
1761 compatible = "syscon-reset";
1762 #reset-cells = <1>;
1763 regmap = <&syscon0>;
1764 offset = <1>;
1765 mask = <0x27FFFFFF>;
1766 assert-high = <0>;
1767 };
1768
1769 syscon-reset-test {
1770 compatible = "sandbox,misc_sandbox";
1771 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1772 reset-names = "valid", "no_mask", "out_of_range";
1773 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301774
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001775 sysinfo {
1776 compatible = "sandbox,sysinfo-sandbox";
1777 };
1778
Sean Anderson1cbfed82021-04-20 10:50:58 -04001779 sysinfo-gpio {
1780 compatible = "gpio-sysinfo";
1781 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1782 revisions = <19>, <5>;
1783 names = "rev_a", "foo";
1784 };
1785
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301786 some_regmapped-bus {
1787 #address-cells = <0x1>;
1788 #size-cells = <0x1>;
1789
1790 ranges = <0x0 0x0 0x10>;
1791 compatible = "simple-bus";
1792
1793 regmap-test_0 {
1794 reg = <0 0x10>;
1795 compatible = "sandbox,regmap_test";
1796 };
1797 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001798
1799 thermal {
1800 compatible = "sandbox,thermal";
1801 };
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301802
1803 fwu-mdata {
1804 compatible = "u-boot,fwu-mdata-gpt";
1805 fwu-mdata-store = <&mmc0>;
1806 };
Abdellatif El Khlificc89b7c2023-04-17 10:11:55 +01001807
1808 nvmxip-qspi1@08000000 {
1809 compatible = "nvmxip,qspi";
1810 reg = <0x08000000 0x00200000>;
1811 lba_shift = <9>;
1812 lba = <4096>;
1813 };
1814
1815 nvmxip-qspi2@08200000 {
1816 compatible = "nvmxip,qspi";
1817 reg = <0x08200000 0x00100000>;
1818 lba_shift = <9>;
1819 lba = <2048>;
1820 };
Svyatoslav Ryhel8b215e12023-04-25 10:57:21 +03001821
1822 extcon {
1823 compatible = "sandbox,extcon";
1824 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001825};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001826
1827#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001828#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001829
1830#ifdef CONFIG_SANDBOX_VPL
1831#include "sandbox_vpl.dtsi"
1832#endif