blob: 442222e4b995f6c7fc997035a233170d476a11e2 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Bin Mengdee4d752018-08-03 01:14:41 -070042 pci0 = &pci0;
43 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070044 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020045 remoteproc0 = &rproc_1;
46 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060047 rtc0 = &rtc_0;
48 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060049 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020050 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070051 testbus3 = "/some-bus";
52 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070053 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070054 testfdt3 = "/b-test";
55 testfdt5 = "/some-bus/c-test@5";
56 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070057 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020058 fdt-dummy0 = "/translation-test@8000/dev@0,0";
59 fdt-dummy1 = "/translation-test@8000/dev@1,100";
60 fdt-dummy2 = "/translation-test@8000/dev@2,200";
61 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060062 usb0 = &usb_0;
63 usb1 = &usb_1;
64 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020065 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020066 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060067 };
68
Simon Glass8de98962022-10-20 18:23:15 -060069 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020070 };
71
Rasmus Villemoes8c728422021-04-21 11:06:55 +020072 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060073 testing-bool;
74 testing-int = <123>;
75 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020076 environment {
77 from_fdt = "yes";
78 fdt_env_path = "";
79 };
80 };
81
Simon Glassfb1451b2022-04-24 23:31:24 -060082 bootstd {
Simon Glass8c103c32023-02-13 08:56:33 -070083 bootph-verify;
Simon Glassfb1451b2022-04-24 23:31:24 -060084 compatible = "u-boot,boot-std";
85
86 filename-prefixes = "/", "/boot/";
87 bootdev-order = "mmc2", "mmc1";
88
Simon Glass79f66352023-05-10 16:34:46 -060089 extlinux {
90 compatible = "u-boot,extlinux";
Simon Glassfb1451b2022-04-24 23:31:24 -060091 };
92
93 efi {
94 compatible = "u-boot,distro-efi";
95 };
Simon Glassa56f6632022-10-20 18:23:14 -060096
Simon Glassd985f1d2023-01-06 08:52:41 -060097 theme {
98 font-size = <30>;
Simon Glass7230fdb2023-06-01 10:23:00 -060099 menu-inset = <3>;
100 menuitem-gap-y = <1>;
Simon Glassd985f1d2023-01-06 08:52:41 -0600101 };
102
Simon Glass77bec9e2022-10-20 18:23:20 -0600103 /*
104 * This is used for the VBE OS-request tests. A FAT filesystem
105 * created in a partition with the VBE information appearing
106 * before the parititon starts
107 */
Simon Glassa56f6632022-10-20 18:23:14 -0600108 firmware0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700109 bootph-verify;
Simon Glassa56f6632022-10-20 18:23:14 -0600110 compatible = "fwupd,vbe-simple";
111 storage = "mmc1";
112 skip-offset = <0x200>;
113 area-start = <0x400>;
114 area-size = <0x1000>;
115 state-offset = <0x400>;
116 state-size = <0x40>;
117 version-offset = <0x800>;
118 version-size = <0x100>;
119 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600120
121 /*
122 * This is used for the VBE VPL tests. The MMC device holds the
123 * binman image.bin file. The test progresses through each phase
124 * of U-Boot, loading each in turn from MMC.
125 *
126 * Note that the test enables this node (and mmc3) before
127 * running U-Boot
128 */
129 firmware1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700130 bootph-verify;
Simon Glass77bec9e2022-10-20 18:23:20 -0600131 status = "disabled";
132 compatible = "fwupd,vbe-simple";
133 storage = "mmc3";
Simon Glass74b75aa2023-04-02 14:01:24 +1200134 skip-offset = <0x800000>;
Simon Glass77bec9e2022-10-20 18:23:20 -0600135 area-start = <0>;
136 area-size = <0xe00000>;
137 state-offset = <0xdffc00>;
138 state-size = <0x40>;
139 version-offset = <0xdffe00>;
140 version-size = <0x100>;
141 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600142 };
143
Simon Glass82cafee2023-06-01 10:23:01 -0600144 cedit: cedit {
145 };
146
Andrew Scull0518e7a2022-05-30 10:00:12 +0000147 fuzzing-engine {
148 compatible = "sandbox,fuzzing-engine";
149 };
150
Nandor Hanf9db2f12021-06-10 16:56:44 +0300151 reboot-mode0 {
152 compatible = "reboot-mode-gpio";
153 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
154 u-boot,env-variable = "bootstatus";
155 mode-test = <0x01>;
156 mode-download = <0x03>;
157 };
158
Nandor Hanc74675b2021-06-10 16:56:45 +0300159 reboot_mode1: reboot-mode@14 {
160 compatible = "reboot-mode-rtc";
161 rtc = <&rtc_0>;
162 reg = <0x30 4>;
163 u-boot,env-variable = "bootstatus";
164 big-endian;
165 mode-test = <0x21969147>;
166 mode-download = <0x51939147>;
167 };
168
Simon Glassce6d99a2018-12-10 10:37:33 -0700169 audio: audio-codec {
170 compatible = "sandbox,audio-codec";
171 #sound-dai-cells = <1>;
172 };
173
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200174 buttons {
175 compatible = "gpio-keys";
176
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200177 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200178 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200179 label = "button1";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300180 linux,code = <BTN_1>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200181 };
182
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200183 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200184 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200185 label = "button2";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300186 linux,code = <BTN_2>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200187 };
188 };
189
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100190 buttons2 {
191 compatible = "adc-keys";
192 io-channels = <&adc 3>;
193 keyup-threshold-microvolt = <3000000>;
194
195 button-up {
196 label = "button3";
197 linux,code = <KEY_F3>;
198 press-threshold-microvolt = <1500000>;
199 };
200
201 button-down {
202 label = "button4";
203 linux,code = <KEY_F4>;
204 press-threshold-microvolt = <1000000>;
205 };
206
207 button-enter {
208 label = "button5";
209 linux,code = <KEY_F5>;
210 press-threshold-microvolt = <500000>;
211 };
212 };
213
Simon Glasse96fa6c2018-12-10 10:37:34 -0700214 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600215 reg = <0 0>;
216 compatible = "google,cros-ec-sandbox";
217
218 /*
219 * This describes the flash memory within the EC. Note
220 * that the STM32L flash erases to 0, not 0xff.
221 */
222 flash {
223 image-pos = <0x08000000>;
224 size = <0x20000>;
225 erase-value = <0>;
226
227 /* Information for sandbox */
228 ro {
229 image-pos = <0>;
230 size = <0xf000>;
231 };
232 wp-ro {
233 image-pos = <0xf000>;
234 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700235 used = <0x884>;
236 compress = "lz4";
237 uncomp-size = <0xcf8>;
238 hash {
239 algo = "sha256";
240 value = [00 01 02 03 04 05 06 07
241 08 09 0a 0b 0c 0d 0e 0f
242 10 11 12 13 14 15 16 17
243 18 19 1a 1b 1c 1d 1e 1f];
244 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600245 };
246 rw {
247 image-pos = <0x10000>;
248 size = <0x10000>;
249 };
250 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300251
252 cros_ec_pwm: cros-ec-pwm {
253 compatible = "google,cros-ec-pwm";
254 #pwm-cells = <1>;
255 };
256
Simon Glasse6c5c942018-10-01 12:22:08 -0600257 };
258
Yannick Fertré23f965a2019-10-07 15:29:05 +0200259 dsi_host: dsi_host {
260 compatible = "sandbox,dsi-host";
261 };
262
Simon Glass2e7d35d2014-02-26 15:59:21 -0700263 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600264 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700265 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600266 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700267 ping-add = <0>;
Simon Glass8c103c32023-02-13 08:56:33 -0700268 bootph-all;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100269 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
270 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700271 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100272 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
273 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
274 <&gpio_b 7 GPIO_IN 3 2 1>,
275 <&gpio_b 8 GPIO_OUT 3 2 1>,
276 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100277 test3-gpios =
278 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
279 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
280 <&gpio_c 2 GPIO_OUT>,
281 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
282 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200283 <&gpio_c 5 GPIO_IN>,
284 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
285 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530286 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
287 test5-gpios = <&gpio_a 19>;
288
Simon Glassfb933d02021-10-23 17:26:04 -0600289 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200290 int8-value = /bits/ 8 <0x12>;
291 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700292 int-value = <1234>;
293 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200294 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200295 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600296 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700297 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600298 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200299 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530300
301 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
302 <&muxcontroller0 2>, <&muxcontroller0 3>,
303 <&muxcontroller1>;
304 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
305 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100306 display-timings {
307 timing0: 240x320 {
308 clock-frequency = <6500000>;
309 hactive = <240>;
310 vactive = <320>;
311 hfront-porch = <6>;
312 hback-porch = <7>;
313 hsync-len = <1>;
314 vback-porch = <5>;
315 vfront-porch = <8>;
316 vsync-len = <2>;
317 hsync-active = <1>;
318 vsync-active = <0>;
319 de-active = <1>;
320 pixelclk-active = <1>;
321 interlaced;
322 doublescan;
323 doubleclk;
324 };
325 timing1: 480x800 {
326 clock-frequency = <9000000>;
327 hactive = <480>;
328 vactive = <800>;
329 hfront-porch = <10>;
330 hback-porch = <59>;
331 hsync-len = <12>;
332 vback-porch = <15>;
333 vfront-porch = <17>;
334 vsync-len = <16>;
335 hsync-active = <0>;
336 vsync-active = <1>;
337 de-active = <0>;
338 pixelclk-active = <0>;
339 };
340 timing2: 800x480 {
341 clock-frequency = <33500000>;
342 hactive = <800>;
343 vactive = <480>;
344 hback-porch = <89>;
345 hfront-porch = <164>;
346 vback-porch = <23>;
347 vfront-porch = <10>;
348 hsync-len = <11>;
349 vsync-len = <13>;
350 };
351 };
Raphael Gallais-Poucd880582023-05-11 16:36:52 +0200352 panel-timing {
Nikhil M Jain2f3d6a42023-01-31 15:35:15 +0530353 clock-frequency = <6500000>;
354 hactive = <240>;
355 vactive = <320>;
356 hfront-porch = <6>;
357 hback-porch = <7>;
358 hsync-len = <1>;
359 vback-porch = <5>;
360 vfront-porch = <8>;
361 vsync-len = <2>;
362 hsync-active = <1>;
363 vsync-active = <0>;
364 de-active = <1>;
365 pixelclk-active = <1>;
366 interlaced;
367 doublescan;
368 doubleclk;
369 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700370 };
371
372 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600373 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700374 compatible = "not,compatible";
375 };
376
377 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600378 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700379 };
380
Simon Glass5d9a88f2018-10-01 12:22:40 -0600381 backlight: backlight {
382 compatible = "pwm-backlight";
383 enable-gpios = <&gpio_a 1>;
384 power-supply = <&ldo_1>;
385 pwms = <&pwm 0 1000>;
386 default-brightness-level = <5>;
387 brightness-levels = <0 16 32 64 128 170 202 234 255>;
388 };
389
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200390 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200391 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200392 bind-test-child1 {
393 compatible = "sandbox,phy";
394 #phy-cells = <1>;
395 };
396
397 bind-test-child2 {
398 compatible = "simple-bus";
399 };
400 };
401
Simon Glass2e7d35d2014-02-26 15:59:21 -0700402 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600403 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700404 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600405 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700406 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530407
408 mux-controls = <&muxcontroller0 0>;
409 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700410 };
411
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200412 phy_provider0: gen_phy@0 {
413 compatible = "sandbox,phy";
414 #phy-cells = <1>;
415 };
416
417 phy_provider1: gen_phy@1 {
418 compatible = "sandbox,phy";
419 #phy-cells = <0>;
420 broken;
421 };
422
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200423 phy_provider2: gen_phy@2 {
424 compatible = "sandbox,phy";
425 #phy-cells = <0>;
426 };
427
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200428 gen_phy_user: gen_phy_user {
429 compatible = "simple-bus";
430 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
431 phy-names = "phy1", "phy2", "phy3";
432 };
433
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200434 gen_phy_user1: gen_phy_user1 {
435 compatible = "simple-bus";
436 phys = <&phy_provider0 0>, <&phy_provider2>;
437 phy-names = "phy1", "phy2";
438 };
439
Simon Glass2e7d35d2014-02-26 15:59:21 -0700440 some-bus {
441 #address-cells = <1>;
442 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600443 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600444 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600445 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700446 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600447 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700448 compatible = "denx,u-boot-fdt-test";
449 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600450 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700451 ping-add = <5>;
452 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600453 c-test@0 {
454 compatible = "denx,u-boot-fdt-test";
455 reg = <0>;
456 ping-expect = <6>;
457 ping-add = <6>;
458 };
459 c-test@1 {
460 compatible = "denx,u-boot-fdt-test";
461 reg = <1>;
462 ping-expect = <7>;
463 ping-add = <7>;
464 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700465 };
466
467 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600468 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600469 ping-expect = <6>;
470 ping-add = <6>;
471 compatible = "google,another-fdt-test";
472 };
473
474 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600475 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600476 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700477 ping-add = <6>;
478 compatible = "google,another-fdt-test";
479 };
480
Simon Glass9cc36a22015-01-25 08:27:05 -0700481 f-test {
482 compatible = "denx,u-boot-fdt-test";
483 };
484
485 g-test {
486 compatible = "denx,u-boot-fdt-test";
487 };
488
Bin Meng2786cd72018-10-10 22:07:01 -0700489 h-test {
490 compatible = "denx,u-boot-fdt-test1";
491 };
492
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200493 i-test {
494 compatible = "mediatek,u-boot-fdt-test";
495 #address-cells = <1>;
496 #size-cells = <0>;
497
498 subnode@0 {
499 reg = <0>;
500 };
501
502 subnode@1 {
503 reg = <1>;
504 };
505
506 subnode@2 {
507 reg = <2>;
508 };
509 };
510
Simon Glassdc12ebb2019-12-29 21:19:25 -0700511 devres-test {
512 compatible = "denx,u-boot-devres-test";
513 };
514
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530515 another-test {
516 reg = <0 2>;
517 compatible = "denx,u-boot-fdt-test";
518 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
519 test5-gpios = <&gpio_a 19>;
520 };
521
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100522 mmio-bus@0 {
523 #address-cells = <1>;
524 #size-cells = <1>;
525 compatible = "denx,u-boot-test-bus";
526 dma-ranges = <0x10000000 0x00000000 0x00040000>;
527
528 subnode@0 {
529 compatible = "denx,u-boot-fdt-test";
530 };
531 };
532
533 mmio-bus@1 {
534 #address-cells = <1>;
535 #size-cells = <1>;
536 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100537
538 subnode@0 {
539 compatible = "denx,u-boot-fdt-test";
540 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100541 };
542
Simon Glass0f7b1112020-07-07 13:12:06 -0600543 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600544 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600545 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600546 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600547 child {
548 compatible = "denx,u-boot-acpi-test";
549 };
Simon Glassf50cc952020-04-08 16:57:34 -0600550 };
551
Simon Glass0f7b1112020-07-07 13:12:06 -0600552 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600553 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600554 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600555 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600556 };
557
Patrice Chotardee87a092017-09-04 14:55:57 +0200558 clocks {
559 clk_fixed: clk-fixed {
560 compatible = "fixed-clock";
561 #clock-cells = <0>;
562 clock-frequency = <1234>;
563 };
Anup Patelb630d572019-02-25 08:14:55 +0000564
565 clk_fixed_factor: clk-fixed-factor {
566 compatible = "fixed-factor-clock";
567 #clock-cells = <0>;
568 clock-div = <3>;
569 clock-mult = <2>;
570 clocks = <&clk_fixed>;
571 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200572
573 osc {
574 compatible = "fixed-clock";
575 #clock-cells = <0>;
576 clock-frequency = <20000000>;
577 };
Stephen Warren135aa952016-06-17 09:44:00 -0600578 };
579
580 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600581 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600582 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200583 assigned-clocks = <&clk_sandbox 3>;
584 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600585 };
586
587 clk-test {
588 compatible = "sandbox,clk-test";
589 clocks = <&clk_fixed>,
590 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200591 <&clk_sandbox 0>,
592 <&clk_sandbox 3>,
593 <&clk_sandbox 2>;
594 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600595 };
596
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200597 ccf: clk-ccf {
598 compatible = "sandbox,clk-ccf";
599 };
600
Simon Glass42b7f422021-12-04 08:56:31 -0700601 efi-media {
602 compatible = "sandbox,efi-media";
603 };
604
Simon Glass171e9912015-05-22 15:42:15 -0600605 eth@10002000 {
606 compatible = "sandbox,eth";
607 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600608 };
609
610 eth_5: eth@10003000 {
611 compatible = "sandbox,eth";
612 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400613 nvmem-cells = <&eth5_addr>;
614 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600615 };
616
Bin Meng71d79712015-08-27 22:25:53 -0700617 eth_3: sbe5 {
618 compatible = "sandbox,eth";
619 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400620 nvmem-cells = <&eth3_addr>;
621 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700622 };
623
Simon Glass171e9912015-05-22 15:42:15 -0600624 eth@10004000 {
625 compatible = "sandbox,eth";
626 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600627 };
628
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200629 phy_eth0: phy-test-eth {
630 compatible = "sandbox,eth";
631 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400632 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200633 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200634 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200635 };
636
Claudiu Manoilff98da02021-03-14 20:14:57 +0800637 dsa_eth0: dsa-test-eth {
638 compatible = "sandbox,eth";
639 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400640 nvmem-cells = <&eth4_addr>;
641 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800642 };
643
644 dsa-test {
645 compatible = "sandbox,dsa";
646
647 ports {
648 #address-cells = <1>;
649 #size-cells = <0>;
650 swp_0: port@0 {
651 reg = <0>;
652 label = "lan0";
653 phy-mode = "rgmii-rxid";
654
655 fixed-link {
656 speed = <100>;
657 full-duplex;
658 };
659 };
660
661 swp_1: port@1 {
662 reg = <1>;
663 label = "lan1";
664 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800665 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800666 };
667
668 port@2 {
669 reg = <2>;
670 ethernet = <&dsa_eth0>;
671
672 fixed-link {
673 speed = <1000>;
674 full-duplex;
675 };
676 };
677 };
678 };
679
Rajan Vaja31b82172018-09-19 03:43:46 -0700680 firmware {
681 sandbox_firmware: sandbox-firmware {
682 compatible = "sandbox,firmware";
683 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200684
Etienne Carriere41d62e22022-02-21 09:22:39 +0100685 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200686 compatible = "sandbox,scmi-agent";
687 #address-cells = <1>;
688 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200689
Etienne Carriere41d62e22022-02-21 09:22:39 +0100690 protocol@10 {
691 reg = <0x10>;
692 };
693
694 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200695 reg = <0x14>;
696 #clock-cells = <1>;
697 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200698
Etienne Carriere41d62e22022-02-21 09:22:39 +0100699 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200700 reg = <0x16>;
701 #reset-cells = <1>;
702 };
Etienne Carriere01242182021-03-08 22:38:07 +0100703
704 protocol@17 {
705 reg = <0x17>;
706
707 regulators {
708 #address-cells = <1>;
709 #size-cells = <0>;
710
Etienne Carriere41d62e22022-02-21 09:22:39 +0100711 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100712 reg = <0>;
713 regulator-name = "sandbox-voltd0";
714 regulator-min-microvolt = <1100000>;
715 regulator-max-microvolt = <3300000>;
716 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100717 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100718 reg = <0x1>;
719 regulator-name = "sandbox-voltd1";
720 regulator-min-microvolt = <1800000>;
721 };
722 };
723 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200724 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700725 };
726
Alexander Dahl1323d082022-09-30 14:04:30 +0200727 fpga {
728 compatible = "sandbox,fpga";
729 };
730
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100731 pinctrl-gpio {
732 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700733
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100734 gpio_a: base-gpios {
735 compatible = "sandbox,gpio";
736 gpio-controller;
737 #gpio-cells = <1>;
738 gpio-bank-name = "a";
739 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200740 hog_input_active_low {
741 gpio-hog;
742 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200743 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200744 };
745 hog_input_active_high {
746 gpio-hog;
747 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200748 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200749 };
750 hog_output_low {
751 gpio-hog;
752 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200753 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200754 };
755 hog_output_high {
756 gpio-hog;
757 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200758 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200759 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100760 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600761
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100762 gpio_b: extra-gpios {
763 compatible = "sandbox,gpio";
764 gpio-controller;
765 #gpio-cells = <5>;
766 gpio-bank-name = "b";
767 sandbox,gpio-count = <10>;
768 };
769
770 gpio_c: pinmux-gpios {
771 compatible = "sandbox,gpio";
772 gpio-controller;
773 #gpio-cells = <2>;
774 gpio-bank-name = "c";
775 sandbox,gpio-count = <10>;
776 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100777 };
778
Simon Glassecc2ed52014-12-10 08:55:55 -0700779 i2c@0 {
780 #address-cells = <1>;
781 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600782 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700783 compatible = "sandbox,i2c";
784 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200785 pinctrl-names = "default";
786 pinctrl-0 = <&pinmux_i2c0_pins>;
787
Simon Glassecc2ed52014-12-10 08:55:55 -0700788 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400789 #address-cells = <1>;
790 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700791 reg = <0x2c>;
792 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700793 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200794 partitions {
795 compatible = "fixed-partitions";
796 #address-cells = <1>;
797 #size-cells = <1>;
798 bootcount_i2c: bootcount@10 {
799 reg = <10 2>;
800 };
801 };
Sean Anderson472caa62022-05-05 13:11:42 -0400802
803 eth3_addr: mac-address@24 {
804 reg = <24 6>;
805 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700806 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200807
Simon Glass52d3bc52015-05-22 15:42:17 -0600808 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400809 #address-cells = <1>;
810 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600811 reg = <0x43>;
812 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700813 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400814
815 eth4_addr: mac-address@40 {
816 reg = <0x40 6>;
817 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600818 };
819
820 rtc_1: rtc@61 {
821 reg = <0x61>;
822 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700823 sandbox,emul = <&emul1>;
824 };
825
826 i2c_emul: emul {
827 reg = <0xff>;
828 compatible = "sandbox,i2c-emul-parent";
829 emul_eeprom: emul-eeprom {
830 compatible = "sandbox,i2c-eeprom";
831 sandbox,filename = "i2c.bin";
832 sandbox,size = <256>;
833 };
834 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700835 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700836 };
837 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700838 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600839 };
840 };
841
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200842 sandbox_pmic: sandbox_pmic {
843 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700844 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200845 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200846
847 mc34708: pmic@41 {
848 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700849 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200850 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700851 };
852
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100853 bootcount@0 {
854 compatible = "u-boot,bootcount-rtc";
855 rtc = <&rtc_1>;
856 offset = <0x13>;
857 };
858
Michal Simekf692b472020-05-28 11:48:55 +0200859 bootcount {
860 compatible = "u-boot,bootcount-i2c-eeprom";
861 i2c-eeprom = <&bootcount_i2c>;
862 };
863
Nandor Hanc50b21b2021-06-10 15:40:38 +0300864 bootcount_4@0 {
865 compatible = "u-boot,bootcount-syscon";
866 syscon = <&syscon0>;
867 reg = <0x0 0x04>, <0x0 0x04>;
868 reg-names = "syscon_reg", "offset";
869 };
870
871 bootcount_2@0 {
872 compatible = "u-boot,bootcount-syscon";
873 syscon = <&syscon0>;
874 reg = <0x0 0x04>, <0x0 0x02> ;
875 reg-names = "syscon_reg", "offset";
876 };
877
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100878 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100879 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100880 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100881 vdd-supply = <&buck2>;
882 vss-microvolts = <0>;
883 };
884
Mark Kettenisfb574622021-10-23 16:58:02 +0200885 iommu: iommu@0 {
886 compatible = "sandbox,iommu";
887 #iommu-cells = <0>;
888 };
889
Simon Glass02554352020-02-06 09:55:00 -0700890 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700891 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700892 interrupt-controller;
893 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700894 };
895
Simon Glass3c97c4f2016-01-18 19:52:26 -0700896 lcd {
Simon Glass8c103c32023-02-13 08:56:33 -0700897 bootph-all;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700898 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200899 pinctrl-names = "default";
900 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700901 xres = <1366>;
902 yres = <768>;
903 };
904
Simon Glass3c43fba2015-07-06 12:54:34 -0600905 leds {
906 compatible = "gpio-leds";
907
908 iracibble {
909 gpios = <&gpio_a 1 0>;
910 label = "sandbox:red";
911 };
912
913 martinet {
914 gpios = <&gpio_a 2 0>;
915 label = "sandbox:green";
916 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200917
918 default_on {
919 gpios = <&gpio_a 5 0>;
920 label = "sandbox:default_on";
921 default-state = "on";
922 };
923
924 default_off {
925 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400926 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200927 default-state = "off";
928 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600929 };
930
Paul Doelle1fc45d62022-07-04 09:00:25 +0000931 wdt-gpio-toggle {
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200932 gpios = <&gpio_a 7 0>;
933 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200934 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000935 hw_algo = "toggle";
936 always-running;
937 };
938
939 wdt-gpio-level {
940 gpios = <&gpio_a 7 0>;
941 compatible = "linux,wdt-gpio";
942 hw_margin_ms = <100>;
943 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200944 always-running;
945 };
946
Stephen Warren8961b522016-05-16 17:41:37 -0600947 mbox: mbox {
948 compatible = "sandbox,mbox";
949 #mbox-cells = <1>;
950 };
951
952 mbox-test {
953 compatible = "sandbox,mbox-test";
954 mboxes = <&mbox 100>, <&mbox 1>;
955 mbox-names = "other", "test";
956 };
957
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900958 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200959 #address-cells = <1>;
960 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400961 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200962 cpu1: cpu@1 {
963 device_type = "cpu";
964 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400965 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900966 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700967 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900968 };
Mario Sixfa44b532018-08-06 10:23:44 +0200969
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200970 cpu2: cpu@2 {
971 device_type = "cpu";
972 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900973 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700974 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900975 };
Mario Sixfa44b532018-08-06 10:23:44 +0200976
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200977 cpu3: cpu@3 {
978 device_type = "cpu";
979 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900980 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700981 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900982 };
Mario Sixfa44b532018-08-06 10:23:44 +0200983 };
984
Dave Gerlach21e3c212020-07-15 23:39:58 -0500985 chipid: chipid {
986 compatible = "sandbox,soc";
987 };
988
Simon Glasse96fa6c2018-12-10 10:37:34 -0700989 i2s: i2s {
990 compatible = "sandbox,i2s";
991 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -0700992 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -0700993 };
994
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +0200995 nop-test_0 {
996 compatible = "sandbox,nop_sandbox1";
997 nop-test_1 {
998 compatible = "sandbox,nop_sandbox2";
999 bind = "True";
1000 };
1001 nop-test_2 {
1002 compatible = "sandbox,nop_sandbox2";
1003 bind = "False";
1004 };
1005 };
1006
Roger Quadros2c120372022-10-20 16:30:46 +03001007 memory-controller {
1008 compatible = "sandbox,memory";
1009 };
1010
Mario Six004e67c2018-07-31 14:24:14 +02001011 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -04001012 #address-cells = <1>;
1013 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +02001014 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -04001015
1016 eth5_addr: mac-address@10 {
1017 reg = <0x10 6>;
1018 };
Mario Six004e67c2018-07-31 14:24:14 +02001019 };
1020
Simon Glasse48eeb92017-04-23 20:02:07 -06001021 mmc2 {
1022 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -06001023 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -06001024 };
1025
Simon Glassfb1451b2022-04-24 23:31:24 -06001026 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001027 mmc1 {
1028 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001029 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001030 };
1031
Simon Glassfb1451b2022-04-24 23:31:24 -06001032 /* This is used for the fastboot tests */
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301033 mmc0: mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001034 compatible = "sandbox,mmc";
1035 };
1036
Simon Glass77bec9e2022-10-20 18:23:20 -06001037 /* This is used for VBE VPL tests */
1038 mmc3 {
1039 status = "disabled";
1040 compatible = "sandbox,mmc";
1041 filename = "image.bin";
1042 non-removable;
1043 };
1044
Simon Glassd985f1d2023-01-06 08:52:41 -06001045 /* This is used for bootstd bootmenu tests */
1046 mmc4 {
1047 status = "disabled";
1048 compatible = "sandbox,mmc";
1049 filename = "mmc4.img";
1050 };
1051
Simon Glassb45c8332019-02-16 20:24:50 -07001052 pch {
1053 compatible = "sandbox,pch";
1054 };
1055
Tom Rini42c64d12020-02-11 12:41:23 -05001056 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001057 compatible = "sandbox,pci";
1058 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001059 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001060 #address-cells = <3>;
1061 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001062 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001063 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis08386da2023-01-21 20:27:57 +01001064 iommu-map = <0x0010 &iommu 0 1>;
1065 iommu-map-mask = <0xfffffff8>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001066 pci@0,0 {
1067 compatible = "pci-generic";
1068 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001069 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001070 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001071 pci@1,0 {
1072 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001073 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1074 reg = <0x02000814 0 0 0 0
1075 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001076 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001077 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001078 p2sb-pci@2,0 {
1079 compatible = "sandbox,p2sb";
1080 reg = <0x02001010 0 0 0 0>;
1081 sandbox,emul = <&p2sb_emul>;
1082
1083 adder {
1084 intel,p2sb-port-id = <3>;
1085 compatible = "sandbox,adder";
1086 };
1087 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001088 pci@1e,0 {
1089 compatible = "sandbox,pmc";
1090 reg = <0xf000 0 0 0 0>;
1091 sandbox,emul = <&pmc_emul1e>;
1092 acpi-base = <0x400>;
1093 gpe0-dwx-mask = <0xf>;
1094 gpe0-dwx-shift-base = <4>;
1095 gpe0-dw = <6 7 9>;
1096 gpe0-sts = <0x20>;
1097 gpe0-en = <0x30>;
1098 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001099 pci@1f,0 {
1100 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001101 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1102 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001103 sandbox,emul = <&swap_case_emul0_1f>;
1104 };
1105 };
1106
1107 pci-emul0 {
1108 compatible = "sandbox,pci-emul-parent";
1109 swap_case_emul0_0: emul0@0,0 {
1110 compatible = "sandbox,swap-case";
1111 };
1112 swap_case_emul0_1: emul0@1,0 {
1113 compatible = "sandbox,swap-case";
1114 use-ea;
1115 };
1116 swap_case_emul0_1f: emul0@1f,0 {
1117 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001118 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001119 p2sb_emul: emul@2,0 {
1120 compatible = "sandbox,p2sb-emul";
1121 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001122 pmc_emul1e: emul@1e,0 {
1123 compatible = "sandbox,pmc-emul";
1124 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001125 };
1126
Tom Rini42c64d12020-02-11 12:41:23 -05001127 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001128 compatible = "sandbox,pci";
1129 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001130 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001131 #address-cells = <3>;
1132 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001133 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001134 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001135 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001136 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001137 0x0c 0x00 0x1234 0x5678
1138 0x10 0x00 0x1234 0x5678>;
1139 pci@10,0 {
1140 reg = <0x8000 0 0 0 0>;
1141 };
Bin Mengdee4d752018-08-03 01:14:41 -07001142 };
1143
Tom Rini42c64d12020-02-11 12:41:23 -05001144 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001145 compatible = "sandbox,pci";
1146 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001147 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001148 #address-cells = <3>;
1149 #size-cells = <2>;
1150 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1151 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1152 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1153 pci@1f,0 {
1154 compatible = "pci-generic";
1155 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001156 sandbox,emul = <&swap_case_emul2_1f>;
1157 };
1158 };
1159
1160 pci-emul2 {
1161 compatible = "sandbox,pci-emul-parent";
1162 swap_case_emul2_1f: emul2@1f,0 {
1163 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001164 };
1165 };
1166
Ramon Friedbb413332019-04-27 11:15:23 +03001167 pci_ep: pci_ep {
1168 compatible = "sandbox,pci_ep";
1169 };
1170
Simon Glass98561572017-04-23 20:10:44 -06001171 probing {
1172 compatible = "simple-bus";
1173 test1 {
1174 compatible = "denx,u-boot-probe-test";
1175 };
1176
1177 test2 {
1178 compatible = "denx,u-boot-probe-test";
1179 };
1180
1181 test3 {
1182 compatible = "denx,u-boot-probe-test";
1183 };
1184
1185 test4 {
1186 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001187 first-syscon = <&syscon0>;
1188 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001189 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001190 };
1191 };
1192
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001193 pwrdom: power-domain {
1194 compatible = "sandbox,power-domain";
1195 #power-domain-cells = <1>;
1196 };
1197
1198 power-domain-test {
1199 compatible = "sandbox,power-domain-test";
1200 power-domains = <&pwrdom 2>;
1201 };
1202
Simon Glass5d9a88f2018-10-01 12:22:40 -06001203 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001204 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001205 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001206 pinctrl-names = "default";
1207 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001208 };
1209
1210 pwm2 {
1211 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001212 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001213 };
1214
Simon Glass64ce0ca2015-07-06 12:54:31 -06001215 ram {
1216 compatible = "sandbox,ram";
1217 };
1218
Simon Glass5010d982015-07-06 12:54:29 -06001219 reset@0 {
1220 compatible = "sandbox,warm-reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001221 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001222 };
1223
1224 reset@1 {
1225 compatible = "sandbox,reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001226 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001227 };
1228
Stephen Warren4581b712016-06-17 09:43:59 -06001229 resetc: reset-ctl {
1230 compatible = "sandbox,reset-ctl";
1231 #reset-cells = <1>;
1232 };
1233
1234 reset-ctl-test {
1235 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001236 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1237 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001238 };
1239
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301240 rng {
1241 compatible = "sandbox,sandbox-rng";
1242 };
1243
Nishanth Menon52159402015-09-17 15:42:41 -05001244 rproc_1: rproc@1 {
1245 compatible = "sandbox,test-processor";
1246 remoteproc-name = "remoteproc-test-dev1";
1247 };
1248
1249 rproc_2: rproc@2 {
1250 compatible = "sandbox,test-processor";
1251 internal-memory-mapped;
1252 remoteproc-name = "remoteproc-test-dev2";
1253 };
1254
Simon Glass5d9a88f2018-10-01 12:22:40 -06001255 panel {
1256 compatible = "simple-panel";
1257 backlight = <&backlight 0 100>;
1258 };
1259
Simon Glass22c80d52022-09-21 16:21:47 +02001260 scsi {
1261 compatible = "sandbox,scsi";
1262 sandbox,filepath = "scsi.img";
1263 };
1264
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001265 smem@0 {
1266 compatible = "sandbox,smem";
1267 };
1268
Simon Glassd4901892018-12-10 10:37:36 -07001269 sound {
1270 compatible = "sandbox,sound";
1271 cpu {
1272 sound-dai = <&i2s 0>;
1273 };
1274
1275 codec {
1276 sound-dai = <&audio 0>;
1277 };
1278 };
1279
Simon Glass0ae0cb72014-10-13 23:42:11 -06001280 spi@0 {
1281 #address-cells = <1>;
1282 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001283 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001284 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001285 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001286 pinctrl-names = "default";
1287 pinctrl-0 = <&pinmux_spi0_pins>;
1288
Simon Glass0ae0cb72014-10-13 23:42:11 -06001289 spi.bin@0 {
1290 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001291 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001292 spi-max-frequency = <40000000>;
1293 sandbox,filename = "spi.bin";
1294 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001295 spi.bin@1 {
1296 reg = <1>;
1297 compatible = "spansion,m25p16", "jedec,spi-nor";
1298 spi-max-frequency = <50000000>;
1299 sandbox,filename = "spi.bin";
1300 spi-cpol;
1301 spi-cpha;
1302 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001303 };
1304
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001305 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001306 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001307 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001308 };
1309
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001310 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001311 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001312 reg = <0x20 5
1313 0x28 6
1314 0x30 7
1315 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001316 };
1317
Patrick Delaunaya442e612019-03-07 09:57:13 +01001318 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001319 compatible = "simple-mfd", "syscon";
1320 reg = <0x40 5
1321 0x48 6
1322 0x50 7
1323 0x58 8>;
1324 };
1325
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301326 syscon3: syscon@3 {
1327 compatible = "simple-mfd", "syscon";
1328 reg = <0x000100 0x10>;
1329
1330 muxcontroller0: a-mux-controller {
1331 compatible = "mmio-mux";
1332 #mux-control-cells = <1>;
1333
1334 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1335 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1336 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1337 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1338 u-boot,mux-autoprobe;
1339 };
1340 };
1341
1342 muxcontroller1: emul-mux-controller {
1343 compatible = "mux-emul";
1344 #mux-control-cells = <0>;
1345 u-boot,mux-autoprobe;
1346 idle-state = <0xabcd>;
1347 };
1348
Simon Glass93f44e82020-12-16 21:20:27 -07001349 testfdtm0 {
1350 compatible = "denx,u-boot-fdtm-test";
1351 };
1352
1353 testfdtm1: testfdtm1 {
1354 compatible = "denx,u-boot-fdtm-test";
1355 };
1356
1357 testfdtm2 {
1358 compatible = "denx,u-boot-fdtm-test";
1359 };
1360
Sean Anderson7616e362020-09-28 10:52:23 -04001361 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001362 compatible = "sandbox,timer";
1363 clock-frequency = <1000000>;
1364 };
1365
Sean Anderson7616e362020-09-28 10:52:23 -04001366 timer@1 {
1367 compatible = "sandbox,timer";
1368 sandbox,timebase-frequency-fallback;
1369 };
1370
Miquel Raynalb91ad162018-05-15 11:57:27 +02001371 tpm2 {
1372 compatible = "sandbox,tpm2";
1373 };
1374
Simon Glass4fef6572023-02-21 06:24:51 -07001375 tpm {
1376 compatible = "google,sandbox-tpm";
1377 };
1378
Simon Glass171e9912015-05-22 15:42:15 -06001379 uart0: serial {
1380 compatible = "sandbox,serial";
Simon Glass8c103c32023-02-13 08:56:33 -07001381 bootph-all;
Dario Binacchi55322622021-04-11 09:39:50 +02001382 pinctrl-names = "default";
1383 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001384 };
1385
Simon Glasse00cb222015-03-25 12:23:05 -06001386 usb_0: usb@0 {
1387 compatible = "sandbox,usb";
1388 status = "disabled";
1389 hub {
1390 compatible = "sandbox,usb-hub";
1391 #address-cells = <1>;
1392 #size-cells = <0>;
1393 flash-stick {
1394 reg = <0>;
1395 compatible = "sandbox,usb-flash";
1396 };
1397 };
1398 };
1399
1400 usb_1: usb@1 {
1401 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001402 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001403 hub {
1404 compatible = "usb-hub";
1405 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001406 #address-cells = <1>;
1407 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001408 hub-emul {
1409 compatible = "sandbox,usb-hub";
1410 #address-cells = <1>;
1411 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001412 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001413 reg = <0>;
1414 compatible = "sandbox,usb-flash";
1415 sandbox,filepath = "testflash.bin";
1416 };
1417
Simon Glass431cbd62015-11-08 23:48:01 -07001418 flash-stick@1 {
1419 reg = <1>;
1420 compatible = "sandbox,usb-flash";
1421 sandbox,filepath = "testflash1.bin";
1422 };
1423
1424 flash-stick@2 {
1425 reg = <2>;
1426 compatible = "sandbox,usb-flash";
1427 sandbox,filepath = "testflash2.bin";
1428 };
1429
Simon Glassbff1a712015-11-08 23:48:08 -07001430 keyb@3 {
1431 reg = <3>;
1432 compatible = "sandbox,usb-keyb";
1433 };
1434
Simon Glasse00cb222015-03-25 12:23:05 -06001435 };
Michael Wallec03b7612020-06-02 01:47:07 +02001436
1437 usbstor@1 {
1438 reg = <1>;
1439 };
1440 usbstor@3 {
1441 reg = <3>;
1442 };
Simon Glasse00cb222015-03-25 12:23:05 -06001443 };
1444 };
1445
1446 usb_2: usb@2 {
1447 compatible = "sandbox,usb";
1448 status = "disabled";
1449 };
1450
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001451 spmi: spmi@0 {
1452 compatible = "sandbox,spmi";
1453 #address-cells = <0x1>;
1454 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001455 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001456 pm8916@0 {
1457 compatible = "qcom,spmi-pmic";
1458 reg = <0x0 0x1>;
1459 #address-cells = <0x1>;
1460 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001461 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001462
1463 spmi_gpios: gpios@c000 {
1464 compatible = "qcom,pm8916-gpio";
1465 reg = <0xc000 0x400>;
1466 gpio-controller;
1467 gpio-count = <4>;
1468 #gpio-cells = <2>;
1469 gpio-bank-name="spmi";
1470 };
1471 };
1472 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001473
1474 wdt0: wdt@0 {
1475 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001476 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001477 };
Rob Clarkf2006802018-01-10 11:33:30 +01001478
Mario Six957983e2018-08-09 14:51:19 +02001479 axi: axi@0 {
1480 compatible = "sandbox,axi";
1481 #address-cells = <0x1>;
1482 #size-cells = <0x1>;
1483 store@0 {
1484 compatible = "sandbox,sandbox_store";
1485 reg = <0x0 0x400>;
1486 };
1487 };
1488
Rob Clarkf2006802018-01-10 11:33:30 +01001489 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001490 #address-cells = <1>;
1491 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001492 setting = "sunrise ohoka";
1493 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001494 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001495 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001496 chosen-test {
1497 compatible = "denx,u-boot-fdt-test";
1498 reg = <9 1>;
1499 };
1500 };
Mario Sixe8d52912018-03-12 14:53:33 +01001501
1502 translation-test@8000 {
1503 compatible = "simple-bus";
1504 reg = <0x8000 0x4000>;
1505
1506 #address-cells = <0x2>;
1507 #size-cells = <0x1>;
1508
1509 ranges = <0 0x0 0x8000 0x1000
1510 1 0x100 0x9000 0x1000
1511 2 0x200 0xA000 0x1000
1512 3 0x300 0xB000 0x1000
1513 >;
1514
Fabien Dessenne641067f2019-05-31 15:11:30 +02001515 dma-ranges = <0 0x000 0x10000000 0x1000
1516 1 0x100 0x20000000 0x1000
1517 >;
1518
Mario Sixe8d52912018-03-12 14:53:33 +01001519 dev@0,0 {
1520 compatible = "denx,u-boot-fdt-dummy";
1521 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001522 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001523 };
1524
1525 dev@1,100 {
1526 compatible = "denx,u-boot-fdt-dummy";
1527 reg = <1 0x100 0x1000>;
1528
1529 };
1530
1531 dev@2,200 {
1532 compatible = "denx,u-boot-fdt-dummy";
1533 reg = <2 0x200 0x1000>;
1534 };
1535
1536
1537 noxlatebus@3,300 {
1538 compatible = "simple-bus";
1539 reg = <3 0x300 0x1000>;
1540
1541 #address-cells = <0x1>;
1542 #size-cells = <0x0>;
1543
1544 dev@42 {
1545 compatible = "denx,u-boot-fdt-dummy";
1546 reg = <0x42>;
1547 };
1548 };
1549 };
Mario Six4eea5312018-09-27 09:19:31 +02001550
Dzmitry Sankouski298ffdd2023-01-22 18:21:23 +03001551 ofnode-foreach {
1552 compatible = "foreach";
1553
1554 first {
1555 prop1 = <1>;
1556 prop2 = <2>;
1557 };
1558
1559 second {
1560 prop1 = <1>;
1561 prop2 = <2>;
1562 };
1563 };
1564
Mario Six4eea5312018-09-27 09:19:31 +02001565 osd {
1566 compatible = "sandbox,sandbox_osd";
1567 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001568
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001569 sandbox_tee {
1570 compatible = "sandbox,tee";
1571 };
Bin Meng4f89d492018-10-15 02:21:26 -07001572
1573 sandbox_virtio1 {
1574 compatible = "sandbox,virtio1";
Simon Glass00fc8ca2023-01-17 10:47:51 -07001575 virtio-type = <4>; /* rng */
Bin Meng4f89d492018-10-15 02:21:26 -07001576 };
1577
1578 sandbox_virtio2 {
1579 compatible = "sandbox,virtio2";
1580 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001581
Simon Glass00fc8ca2023-01-17 10:47:51 -07001582 sandbox-virtio-blk {
1583 compatible = "sandbox,virtio1";
1584 virtio-type = <2>; /* block */
1585 };
1586
Etienne Carriere87d4f272020-09-09 18:44:05 +02001587 sandbox_scmi {
1588 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001589 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001590 resets = <&reset_scmi 3>;
1591 regul0-supply = <&regul0_scmi>;
1592 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001593 };
1594
Patrice Chotardf41a8242018-10-24 14:10:23 +02001595 pinctrl {
1596 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001597
Sean Anderson7f0f1802020-09-14 11:01:57 -04001598 pinctrl-names = "default", "alternate";
1599 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1600 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001601
Sean Anderson7f0f1802020-09-14 11:01:57 -04001602 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001603 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001604 pins = "P5";
1605 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001606 bias-pull-up;
1607 input-disable;
1608 };
1609 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001610 pins = "P6";
1611 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001612 output-high;
1613 drive-open-drain;
1614 };
1615 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001616 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001617 bias-pull-down;
1618 input-enable;
1619 };
1620 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001621 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001622 bias-disable;
1623 };
1624 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001625
1626 pinctrl_i2c: i2c {
1627 groups {
1628 groups = "I2C_UART";
1629 function = "I2C";
1630 };
1631
1632 pins {
1633 pins = "P0", "P1";
1634 drive-open-drain;
1635 };
1636 };
1637
1638 pinctrl_i2s: i2s {
1639 groups = "SPI_I2S";
1640 function = "I2S";
1641 };
1642
1643 pinctrl_spi: spi {
1644 groups = "SPI_I2S";
1645 function = "SPI";
1646
1647 cs {
1648 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1649 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1650 };
1651 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001652 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001653
Dario Binacchi55322622021-04-11 09:39:50 +02001654 pinctrl-single-no-width {
1655 compatible = "pinctrl-single";
1656 reg = <0x0000 0x238>;
1657 #pinctrl-cells = <1>;
1658 pinctrl-single,function-mask = <0x7f>;
1659 };
1660
1661 pinctrl-single-pins {
1662 compatible = "pinctrl-single";
1663 reg = <0x0000 0x238>;
1664 #pinctrl-cells = <1>;
1665 pinctrl-single,register-width = <32>;
1666 pinctrl-single,function-mask = <0x7f>;
1667
1668 pinmux_pwm_pins: pinmux_pwm_pins {
1669 pinctrl-single,pins = < 0x48 0x06 >;
1670 };
1671
1672 pinmux_spi0_pins: pinmux_spi0_pins {
1673 pinctrl-single,pins = <
1674 0x190 0x0c
1675 0x194 0x0c
1676 0x198 0x23
1677 0x19c 0x0c
1678 >;
1679 };
1680
1681 pinmux_uart0_pins: pinmux_uart0_pins {
1682 pinctrl-single,pins = <
1683 0x70 0x30
1684 0x74 0x00
1685 >;
1686 };
1687 };
1688
1689 pinctrl-single-bits {
1690 compatible = "pinctrl-single";
1691 reg = <0x0000 0x50>;
1692 #pinctrl-cells = <2>;
1693 pinctrl-single,bit-per-mux;
1694 pinctrl-single,register-width = <32>;
1695 pinctrl-single,function-mask = <0xf>;
1696
1697 pinmux_i2c0_pins: pinmux_i2c0_pins {
1698 pinctrl-single,bits = <
1699 0x10 0x00002200 0x0000ff00
1700 >;
1701 };
1702
1703 pinmux_lcd_pins: pinmux_lcd_pins {
1704 pinctrl-single,bits = <
1705 0x40 0x22222200 0xffffff00
1706 0x44 0x22222222 0xffffffff
1707 0x48 0x00000022 0x000000ff
1708 0x48 0x02000000 0x0f000000
1709 0x4c 0x02000022 0x0f0000ff
1710 >;
1711 };
1712 };
1713
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001714 hwspinlock@0 {
1715 compatible = "sandbox,hwspinlock";
1716 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001717
1718 dma: dma {
1719 compatible = "sandbox,dma";
1720 #dma-cells = <1>;
1721
1722 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1723 dma-names = "m2m", "tx0", "rx0";
1724 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001725
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001726 /*
1727 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1728 * end of the test. If parent mdio is removed first, clean-up of the
1729 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1730 * active at the end of the test. That it turn doesn't allow the mdio
1731 * class to be destroyed, triggering an error.
1732 */
1733 mdio-mux-test {
1734 compatible = "sandbox,mdio-mux";
1735 #address-cells = <1>;
1736 #size-cells = <0>;
1737 mdio-parent-bus = <&mdio>;
1738
1739 mdio-ch-test@0 {
1740 reg = <0>;
1741 };
1742 mdio-ch-test@1 {
1743 reg = <1>;
1744 };
1745 };
1746
1747 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001748 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001749 #address-cells = <1>;
1750 #size-cells = <0>;
1751
1752 ethphy1: ethernet-phy@1 {
1753 reg = <1>;
1754 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001755 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001756
1757 pm-bus-test {
1758 compatible = "simple-pm-bus";
1759 clocks = <&clk_sandbox 4>;
1760 power-domains = <&pwrdom 1>;
1761 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001762
1763 resetc2: syscon-reset {
1764 compatible = "syscon-reset";
1765 #reset-cells = <1>;
1766 regmap = <&syscon0>;
1767 offset = <1>;
1768 mask = <0x27FFFFFF>;
1769 assert-high = <0>;
1770 };
1771
1772 syscon-reset-test {
1773 compatible = "sandbox,misc_sandbox";
1774 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1775 reset-names = "valid", "no_mask", "out_of_range";
1776 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301777
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001778 sysinfo {
1779 compatible = "sandbox,sysinfo-sandbox";
1780 };
1781
Sean Anderson1cbfed82021-04-20 10:50:58 -04001782 sysinfo-gpio {
1783 compatible = "gpio-sysinfo";
1784 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1785 revisions = <19>, <5>;
1786 names = "rev_a", "foo";
1787 };
1788
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301789 some_regmapped-bus {
1790 #address-cells = <0x1>;
1791 #size-cells = <0x1>;
1792
1793 ranges = <0x0 0x0 0x10>;
1794 compatible = "simple-bus";
1795
1796 regmap-test_0 {
1797 reg = <0 0x10>;
1798 compatible = "sandbox,regmap_test";
1799 };
1800 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001801
1802 thermal {
1803 compatible = "sandbox,thermal";
1804 };
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301805
1806 fwu-mdata {
1807 compatible = "u-boot,fwu-mdata-gpt";
1808 fwu-mdata-store = <&mmc0>;
1809 };
Abdellatif El Khlificc89b7c2023-04-17 10:11:55 +01001810
1811 nvmxip-qspi1@08000000 {
1812 compatible = "nvmxip,qspi";
1813 reg = <0x08000000 0x00200000>;
1814 lba_shift = <9>;
1815 lba = <4096>;
1816 };
1817
1818 nvmxip-qspi2@08200000 {
1819 compatible = "nvmxip,qspi";
1820 reg = <0x08200000 0x00100000>;
1821 lba_shift = <9>;
1822 lba = <2048>;
1823 };
Svyatoslav Ryhel8b215e12023-04-25 10:57:21 +03001824
1825 extcon {
1826 compatible = "sandbox,extcon";
1827 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001828};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001829
1830#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001831#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001832
1833#ifdef CONFIG_SANDBOX_VPL
1834#include "sandbox_vpl.dtsi"
1835#endif
Simon Glass82cafee2023-06-01 10:23:01 -06001836
1837#include "cedit.dtsi"