blob: 577ef346b62407866d0f7a625812a39c406cbb10 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Simon Glassd08db022023-08-24 13:55:41 -060042 mmc4 = "/mmc4";
43 mmc5 = "/mmc5";
Alexander Gendin04291ee2023-10-09 01:24:36 +000044 mmc6 = "/mmc6";
Bin Mengdee4d752018-08-03 01:14:41 -070045 pci0 = &pci0;
46 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070047 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020048 remoteproc0 = &rproc_1;
49 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060050 rtc0 = &rtc_0;
51 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060052 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020053 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070054 testbus3 = "/some-bus";
55 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070056 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070057 testfdt3 = "/b-test";
58 testfdt5 = "/some-bus/c-test@5";
59 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070060 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020061 fdt-dummy0 = "/translation-test@8000/dev@0,0";
62 fdt-dummy1 = "/translation-test@8000/dev@1,100";
63 fdt-dummy2 = "/translation-test@8000/dev@2,200";
64 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060065 usb0 = &usb_0;
66 usb1 = &usb_1;
67 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020068 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020069 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060070 };
71
Simon Glass8de98962022-10-20 18:23:15 -060072 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020073 };
74
Rasmus Villemoes8c728422021-04-21 11:06:55 +020075 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060076 testing-bool;
77 testing-int = <123>;
78 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020079 environment {
80 from_fdt = "yes";
81 fdt_env_path = "";
82 };
83 };
84
Michal Simekdb5e3492023-08-31 08:59:05 +020085 options {
86 u-boot {
87 compatible = "u-boot,config";
88 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek44f35e12023-08-31 09:04:27 +020089 bootscr-flash-offset = /bits/ 64 <0>;
90 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simekdb5e3492023-08-31 08:59:05 +020091 };
92 };
93
Simon Glassfb1451b2022-04-24 23:31:24 -060094 bootstd {
Simon Glass8c103c32023-02-13 08:56:33 -070095 bootph-verify;
Simon Glassfb1451b2022-04-24 23:31:24 -060096 compatible = "u-boot,boot-std";
97
98 filename-prefixes = "/", "/boot/";
99 bootdev-order = "mmc2", "mmc1";
100
Simon Glass79f66352023-05-10 16:34:46 -0600101 extlinux {
102 compatible = "u-boot,extlinux";
Simon Glassfb1451b2022-04-24 23:31:24 -0600103 };
104
105 efi {
106 compatible = "u-boot,distro-efi";
107 };
Simon Glassa56f6632022-10-20 18:23:14 -0600108
Simon Glassd985f1d2023-01-06 08:52:41 -0600109 theme {
110 font-size = <30>;
Simon Glass7230fdb2023-06-01 10:23:00 -0600111 menu-inset = <3>;
112 menuitem-gap-y = <1>;
Simon Glassd985f1d2023-01-06 08:52:41 -0600113 };
114
Simon Glass2045ca52023-08-14 16:40:30 -0600115 cedit-theme {
116 font-size = <30>;
117 menu-inset = <3>;
118 menuitem-gap-y = <1>;
119 };
120
Simon Glass77bec9e2022-10-20 18:23:20 -0600121 /*
122 * This is used for the VBE OS-request tests. A FAT filesystem
123 * created in a partition with the VBE information appearing
Michal Simek92271d62023-09-07 14:55:48 +0200124 * before the partition starts
Simon Glass77bec9e2022-10-20 18:23:20 -0600125 */
Simon Glassa56f6632022-10-20 18:23:14 -0600126 firmware0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700127 bootph-verify;
Simon Glassa56f6632022-10-20 18:23:14 -0600128 compatible = "fwupd,vbe-simple";
129 storage = "mmc1";
130 skip-offset = <0x200>;
131 area-start = <0x400>;
132 area-size = <0x1000>;
133 state-offset = <0x400>;
134 state-size = <0x40>;
135 version-offset = <0x800>;
136 version-size = <0x100>;
137 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600138
139 /*
140 * This is used for the VBE VPL tests. The MMC device holds the
141 * binman image.bin file. The test progresses through each phase
142 * of U-Boot, loading each in turn from MMC.
143 *
144 * Note that the test enables this node (and mmc3) before
145 * running U-Boot
146 */
147 firmware1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700148 bootph-verify;
Simon Glass77bec9e2022-10-20 18:23:20 -0600149 status = "disabled";
150 compatible = "fwupd,vbe-simple";
151 storage = "mmc3";
Simon Glass74b75aa2023-04-02 14:01:24 +1200152 skip-offset = <0x800000>;
Simon Glass77bec9e2022-10-20 18:23:20 -0600153 area-start = <0>;
154 area-size = <0xe00000>;
155 state-offset = <0xdffc00>;
156 state-size = <0x40>;
157 version-offset = <0xdffe00>;
158 version-size = <0x100>;
159 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600160 };
161
Simon Glass82cafee2023-06-01 10:23:01 -0600162 cedit: cedit {
163 };
164
Andrew Scull0518e7a2022-05-30 10:00:12 +0000165 fuzzing-engine {
166 compatible = "sandbox,fuzzing-engine";
167 };
168
Nandor Hanf9db2f12021-06-10 16:56:44 +0300169 reboot-mode0 {
170 compatible = "reboot-mode-gpio";
171 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
172 u-boot,env-variable = "bootstatus";
173 mode-test = <0x01>;
174 mode-download = <0x03>;
175 };
176
Nandor Hanc74675b2021-06-10 16:56:45 +0300177 reboot_mode1: reboot-mode@14 {
178 compatible = "reboot-mode-rtc";
179 rtc = <&rtc_0>;
180 reg = <0x30 4>;
181 u-boot,env-variable = "bootstatus";
182 big-endian;
183 mode-test = <0x21969147>;
184 mode-download = <0x51939147>;
185 };
186
Simon Glassce6d99a2018-12-10 10:37:33 -0700187 audio: audio-codec {
188 compatible = "sandbox,audio-codec";
189 #sound-dai-cells = <1>;
190 };
191
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200192 buttons {
193 compatible = "gpio-keys";
194
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200195 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200196 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200197 label = "button1";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300198 linux,code = <BTN_1>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200199 };
200
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200201 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200202 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200203 label = "button2";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300204 linux,code = <BTN_2>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200205 };
206 };
207
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100208 buttons2 {
209 compatible = "adc-keys";
210 io-channels = <&adc 3>;
211 keyup-threshold-microvolt = <3000000>;
212
213 button-up {
214 label = "button3";
215 linux,code = <KEY_F3>;
216 press-threshold-microvolt = <1500000>;
217 };
218
219 button-down {
220 label = "button4";
221 linux,code = <KEY_F4>;
222 press-threshold-microvolt = <1000000>;
223 };
224
225 button-enter {
226 label = "button5";
227 linux,code = <KEY_F5>;
228 press-threshold-microvolt = <500000>;
229 };
230 };
231
Simon Glasse96fa6c2018-12-10 10:37:34 -0700232 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600233 reg = <0 0>;
234 compatible = "google,cros-ec-sandbox";
235
236 /*
237 * This describes the flash memory within the EC. Note
238 * that the STM32L flash erases to 0, not 0xff.
239 */
240 flash {
241 image-pos = <0x08000000>;
242 size = <0x20000>;
243 erase-value = <0>;
244
245 /* Information for sandbox */
246 ro {
247 image-pos = <0>;
248 size = <0xf000>;
249 };
250 wp-ro {
251 image-pos = <0xf000>;
252 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700253 used = <0x884>;
254 compress = "lz4";
255 uncomp-size = <0xcf8>;
256 hash {
257 algo = "sha256";
258 value = [00 01 02 03 04 05 06 07
259 08 09 0a 0b 0c 0d 0e 0f
260 10 11 12 13 14 15 16 17
261 18 19 1a 1b 1c 1d 1e 1f];
262 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600263 };
264 rw {
265 image-pos = <0x10000>;
266 size = <0x10000>;
267 };
268 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300269
270 cros_ec_pwm: cros-ec-pwm {
271 compatible = "google,cros-ec-pwm";
272 #pwm-cells = <1>;
273 };
274
Simon Glasse6c5c942018-10-01 12:22:08 -0600275 };
276
Yannick Fertré23f965a2019-10-07 15:29:05 +0200277 dsi_host: dsi_host {
278 compatible = "sandbox,dsi-host";
279 };
280
Simon Glass2e7d35d2014-02-26 15:59:21 -0700281 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600282 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700283 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600284 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700285 ping-add = <0>;
Simon Glass8c103c32023-02-13 08:56:33 -0700286 bootph-all;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100287 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
288 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700289 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100290 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
291 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
292 <&gpio_b 7 GPIO_IN 3 2 1>,
293 <&gpio_b 8 GPIO_OUT 3 2 1>,
294 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100295 test3-gpios =
296 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
297 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
298 <&gpio_c 2 GPIO_OUT>,
299 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
300 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200301 <&gpio_c 5 GPIO_IN>,
302 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
303 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530304 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
305 test5-gpios = <&gpio_a 19>;
306
Simon Glassfb933d02021-10-23 17:26:04 -0600307 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200308 int8-value = /bits/ 8 <0x12>;
309 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700310 int-value = <1234>;
311 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200312 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200313 int-array = <5678 9123 4567>;
Michal Simekfa12dfa2023-08-25 11:37:46 +0200314 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glass06679002020-07-07 13:11:58 -0600315 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700316 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600317 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200318 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530319
320 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
321 <&muxcontroller0 2>, <&muxcontroller0 3>,
322 <&muxcontroller1>;
323 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
324 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100325 display-timings {
326 timing0: 240x320 {
327 clock-frequency = <6500000>;
328 hactive = <240>;
329 vactive = <320>;
330 hfront-porch = <6>;
331 hback-porch = <7>;
332 hsync-len = <1>;
333 vback-porch = <5>;
334 vfront-porch = <8>;
335 vsync-len = <2>;
336 hsync-active = <1>;
337 vsync-active = <0>;
338 de-active = <1>;
339 pixelclk-active = <1>;
340 interlaced;
341 doublescan;
342 doubleclk;
343 };
344 timing1: 480x800 {
345 clock-frequency = <9000000>;
346 hactive = <480>;
347 vactive = <800>;
348 hfront-porch = <10>;
349 hback-porch = <59>;
350 hsync-len = <12>;
351 vback-porch = <15>;
352 vfront-porch = <17>;
353 vsync-len = <16>;
354 hsync-active = <0>;
355 vsync-active = <1>;
356 de-active = <0>;
357 pixelclk-active = <0>;
358 };
359 timing2: 800x480 {
360 clock-frequency = <33500000>;
361 hactive = <800>;
362 vactive = <480>;
363 hback-porch = <89>;
364 hfront-porch = <164>;
365 vback-porch = <23>;
366 vfront-porch = <10>;
367 hsync-len = <11>;
368 vsync-len = <13>;
369 };
370 };
Raphael Gallais-Poucd880582023-05-11 16:36:52 +0200371 panel-timing {
Nikhil M Jain2f3d6a42023-01-31 15:35:15 +0530372 clock-frequency = <6500000>;
373 hactive = <240>;
374 vactive = <320>;
375 hfront-porch = <6>;
376 hback-porch = <7>;
377 hsync-len = <1>;
378 vback-porch = <5>;
379 vfront-porch = <8>;
380 vsync-len = <2>;
381 hsync-active = <1>;
382 vsync-active = <0>;
383 de-active = <1>;
384 pixelclk-active = <1>;
385 interlaced;
386 doublescan;
387 doubleclk;
388 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700389 };
390
391 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600392 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700393 compatible = "not,compatible";
394 };
395
396 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600397 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700398 };
399
Simon Glass5d9a88f2018-10-01 12:22:40 -0600400 backlight: backlight {
401 compatible = "pwm-backlight";
402 enable-gpios = <&gpio_a 1>;
403 power-supply = <&ldo_1>;
404 pwms = <&pwm 0 1000>;
405 default-brightness-level = <5>;
406 brightness-levels = <0 16 32 64 128 170 202 234 255>;
407 };
408
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200409 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200410 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200411 bind-test-child1 {
412 compatible = "sandbox,phy";
413 #phy-cells = <1>;
414 };
415
416 bind-test-child2 {
417 compatible = "simple-bus";
418 };
419 };
420
Simon Glass2e7d35d2014-02-26 15:59:21 -0700421 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600422 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700423 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600424 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700425 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530426
427 mux-controls = <&muxcontroller0 0>;
428 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700429 };
430
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200431 phy_provider0: gen_phy@0 {
432 compatible = "sandbox,phy";
433 #phy-cells = <1>;
434 };
435
436 phy_provider1: gen_phy@1 {
437 compatible = "sandbox,phy";
438 #phy-cells = <0>;
439 broken;
440 };
441
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200442 phy_provider2: gen_phy@2 {
443 compatible = "sandbox,phy";
444 #phy-cells = <0>;
445 };
446
Jonas Karlman14639bf2023-08-31 22:16:35 +0000447 phy_provider3: gen_phy@3 {
448 compatible = "sandbox,phy";
449 #phy-cells = <2>;
450 };
451
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200452 gen_phy_user: gen_phy_user {
453 compatible = "simple-bus";
454 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
455 phy-names = "phy1", "phy2", "phy3";
456 };
457
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200458 gen_phy_user1: gen_phy_user1 {
459 compatible = "simple-bus";
460 phys = <&phy_provider0 0>, <&phy_provider2>;
461 phy-names = "phy1", "phy2";
462 };
463
Jonas Karlman14639bf2023-08-31 22:16:35 +0000464 gen_phy_user2: gen_phy_user2 {
465 compatible = "simple-bus";
466 phys = <&phy_provider3 0 0>;
467 phy-names = "phy1";
468 };
469
Simon Glass2e7d35d2014-02-26 15:59:21 -0700470 some-bus {
471 #address-cells = <1>;
472 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600473 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600474 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600475 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700476 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600477 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700478 compatible = "denx,u-boot-fdt-test";
479 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600480 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700481 ping-add = <5>;
482 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600483 c-test@0 {
484 compatible = "denx,u-boot-fdt-test";
485 reg = <0>;
486 ping-expect = <6>;
487 ping-add = <6>;
488 };
489 c-test@1 {
490 compatible = "denx,u-boot-fdt-test";
491 reg = <1>;
492 ping-expect = <7>;
493 ping-add = <7>;
494 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700495 };
496
497 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600498 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600499 ping-expect = <6>;
500 ping-add = <6>;
501 compatible = "google,another-fdt-test";
502 };
503
504 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600505 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600506 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700507 ping-add = <6>;
508 compatible = "google,another-fdt-test";
509 };
510
Simon Glass9cc36a22015-01-25 08:27:05 -0700511 f-test {
512 compatible = "denx,u-boot-fdt-test";
513 };
514
515 g-test {
516 compatible = "denx,u-boot-fdt-test";
517 };
518
Bin Meng2786cd72018-10-10 22:07:01 -0700519 h-test {
520 compatible = "denx,u-boot-fdt-test1";
521 };
522
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200523 i-test {
524 compatible = "mediatek,u-boot-fdt-test";
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 subnode@0 {
529 reg = <0>;
530 };
531
532 subnode@1 {
533 reg = <1>;
534 };
535
536 subnode@2 {
537 reg = <2>;
538 };
539 };
540
Simon Glassdc12ebb2019-12-29 21:19:25 -0700541 devres-test {
542 compatible = "denx,u-boot-devres-test";
543 };
544
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530545 another-test {
546 reg = <0 2>;
547 compatible = "denx,u-boot-fdt-test";
548 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
549 test5-gpios = <&gpio_a 19>;
550 };
551
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100552 mmio-bus@0 {
553 #address-cells = <1>;
554 #size-cells = <1>;
555 compatible = "denx,u-boot-test-bus";
556 dma-ranges = <0x10000000 0x00000000 0x00040000>;
557
558 subnode@0 {
559 compatible = "denx,u-boot-fdt-test";
560 };
561 };
562
563 mmio-bus@1 {
564 #address-cells = <1>;
565 #size-cells = <1>;
566 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100567
568 subnode@0 {
569 compatible = "denx,u-boot-fdt-test";
570 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100571 };
572
Simon Glass0f7b1112020-07-07 13:12:06 -0600573 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600574 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600575 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600576 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600577 child {
578 compatible = "denx,u-boot-acpi-test";
579 };
Simon Glassf50cc952020-04-08 16:57:34 -0600580 };
581
Simon Glass0f7b1112020-07-07 13:12:06 -0600582 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600583 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600584 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600585 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600586 };
587
Patrice Chotardee87a092017-09-04 14:55:57 +0200588 clocks {
589 clk_fixed: clk-fixed {
590 compatible = "fixed-clock";
591 #clock-cells = <0>;
592 clock-frequency = <1234>;
593 };
Anup Patelb630d572019-02-25 08:14:55 +0000594
595 clk_fixed_factor: clk-fixed-factor {
596 compatible = "fixed-factor-clock";
597 #clock-cells = <0>;
598 clock-div = <3>;
599 clock-mult = <2>;
600 clocks = <&clk_fixed>;
601 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200602
603 osc {
604 compatible = "fixed-clock";
605 #clock-cells = <0>;
606 clock-frequency = <20000000>;
607 };
Stephen Warren135aa952016-06-17 09:44:00 -0600608 };
609
610 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600611 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600612 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200613 assigned-clocks = <&clk_sandbox 3>;
614 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600615 };
616
617 clk-test {
618 compatible = "sandbox,clk-test";
619 clocks = <&clk_fixed>,
620 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200621 <&clk_sandbox 0>,
622 <&clk_sandbox 3>,
623 <&clk_sandbox 2>;
624 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600625 };
626
Ashok Reddy Soma99b46472023-08-30 10:31:42 +0200627 clk-test2 {
628 compatible = "sandbox,clk-test";
629 assigned-clock-rates = <321>;
630 };
631
632 clk-test3 {
633 compatible = "sandbox,clk-test";
634 assigned-clocks = <&clk_sandbox 1>;
635 };
636
637 clk-test4 {
638 compatible = "sandbox,clk-test";
639 assigned-clock-rates = <654>, <321>;
640 assigned-clocks = <&clk_sandbox 1>;
641 };
642
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200643 ccf: clk-ccf {
644 compatible = "sandbox,clk-ccf";
645 };
646
Simon Glass42b7f422021-12-04 08:56:31 -0700647 efi-media {
648 compatible = "sandbox,efi-media";
649 };
650
Simon Glass171e9912015-05-22 15:42:15 -0600651 eth@10002000 {
652 compatible = "sandbox,eth";
653 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600654 };
655
656 eth_5: eth@10003000 {
657 compatible = "sandbox,eth";
658 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400659 nvmem-cells = <&eth5_addr>;
660 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600661 };
662
Bin Meng71d79712015-08-27 22:25:53 -0700663 eth_3: sbe5 {
664 compatible = "sandbox,eth";
665 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400666 nvmem-cells = <&eth3_addr>;
667 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700668 };
669
Simon Glass171e9912015-05-22 15:42:15 -0600670 eth@10004000 {
671 compatible = "sandbox,eth";
672 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600673 };
674
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200675 phy_eth0: phy-test-eth {
676 compatible = "sandbox,eth";
677 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400678 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200679 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200680 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200681 };
682
Claudiu Manoilff98da02021-03-14 20:14:57 +0800683 dsa_eth0: dsa-test-eth {
684 compatible = "sandbox,eth";
685 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400686 nvmem-cells = <&eth4_addr>;
687 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800688 };
689
690 dsa-test {
691 compatible = "sandbox,dsa";
692
693 ports {
694 #address-cells = <1>;
695 #size-cells = <0>;
696 swp_0: port@0 {
697 reg = <0>;
698 label = "lan0";
699 phy-mode = "rgmii-rxid";
700
701 fixed-link {
702 speed = <100>;
703 full-duplex;
704 };
705 };
706
707 swp_1: port@1 {
708 reg = <1>;
709 label = "lan1";
710 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800711 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800712 };
713
714 port@2 {
715 reg = <2>;
716 ethernet = <&dsa_eth0>;
717
718 fixed-link {
719 speed = <1000>;
720 full-duplex;
721 };
722 };
723 };
724 };
725
Rajan Vaja31b82172018-09-19 03:43:46 -0700726 firmware {
727 sandbox_firmware: sandbox-firmware {
728 compatible = "sandbox,firmware";
729 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200730
Etienne Carriere41d62e22022-02-21 09:22:39 +0100731 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200732 compatible = "sandbox,scmi-agent";
733 #address-cells = <1>;
734 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200735
Etienne Carriere41d62e22022-02-21 09:22:39 +0100736 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200737 reg = <0x14>;
738 #clock-cells = <1>;
AKASHI Takahiroa89d9f42023-10-11 19:06:59 +0900739 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200740 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200741
Etienne Carriere41d62e22022-02-21 09:22:39 +0100742 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200743 reg = <0x16>;
744 #reset-cells = <1>;
745 };
Etienne Carriere01242182021-03-08 22:38:07 +0100746
747 protocol@17 {
748 reg = <0x17>;
749
750 regulators {
751 #address-cells = <1>;
752 #size-cells = <0>;
753
Etienne Carriere41d62e22022-02-21 09:22:39 +0100754 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100755 reg = <0>;
756 regulator-name = "sandbox-voltd0";
757 regulator-min-microvolt = <1100000>;
758 regulator-max-microvolt = <3300000>;
759 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100760 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100761 reg = <0x1>;
762 regulator-name = "sandbox-voltd1";
763 regulator-min-microvolt = <1800000>;
764 };
765 };
766 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200767 };
Alexey Romanovc3be2f12023-09-21 11:13:36 +0300768
769 sm: secure-monitor {
770 compatible = "sandbox,sm";
771 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700772 };
773
Alexander Dahl1323d082022-09-30 14:04:30 +0200774 fpga {
775 compatible = "sandbox,fpga";
776 };
777
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100778 pinctrl-gpio {
779 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700780
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100781 gpio_a: base-gpios {
782 compatible = "sandbox,gpio";
783 gpio-controller;
784 #gpio-cells = <1>;
785 gpio-bank-name = "a";
786 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200787 hog_input_active_low {
788 gpio-hog;
789 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200790 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200791 };
792 hog_input_active_high {
793 gpio-hog;
794 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200795 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200796 };
797 hog_output_low {
798 gpio-hog;
799 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200800 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200801 };
802 hog_output_high {
803 gpio-hog;
804 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200805 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200806 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100807 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600808
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100809 gpio_b: extra-gpios {
810 compatible = "sandbox,gpio";
811 gpio-controller;
812 #gpio-cells = <5>;
813 gpio-bank-name = "b";
814 sandbox,gpio-count = <10>;
815 };
816
817 gpio_c: pinmux-gpios {
818 compatible = "sandbox,gpio";
819 gpio-controller;
820 #gpio-cells = <2>;
821 gpio-bank-name = "c";
822 sandbox,gpio-count = <10>;
823 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100824 };
825
Simon Glassecc2ed52014-12-10 08:55:55 -0700826 i2c@0 {
827 #address-cells = <1>;
828 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600829 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700830 compatible = "sandbox,i2c";
831 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200832 pinctrl-names = "default";
833 pinctrl-0 = <&pinmux_i2c0_pins>;
834
Simon Glassecc2ed52014-12-10 08:55:55 -0700835 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400836 #address-cells = <1>;
837 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700838 reg = <0x2c>;
839 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700840 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200841 partitions {
842 compatible = "fixed-partitions";
843 #address-cells = <1>;
844 #size-cells = <1>;
845 bootcount_i2c: bootcount@10 {
846 reg = <10 2>;
847 };
848 };
Sean Anderson472caa62022-05-05 13:11:42 -0400849
850 eth3_addr: mac-address@24 {
851 reg = <24 6>;
852 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700853 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200854
Simon Glass52d3bc52015-05-22 15:42:17 -0600855 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400856 #address-cells = <1>;
857 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600858 reg = <0x43>;
859 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700860 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400861
862 eth4_addr: mac-address@40 {
863 reg = <0x40 6>;
864 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600865 };
866
867 rtc_1: rtc@61 {
868 reg = <0x61>;
869 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700870 sandbox,emul = <&emul1>;
871 };
872
873 i2c_emul: emul {
874 reg = <0xff>;
875 compatible = "sandbox,i2c-emul-parent";
876 emul_eeprom: emul-eeprom {
877 compatible = "sandbox,i2c-eeprom";
878 sandbox,filename = "i2c.bin";
879 sandbox,size = <256>;
880 };
881 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700882 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700883 };
884 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700885 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600886 };
887 };
888
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200889 sandbox_pmic: sandbox_pmic {
890 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700891 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200892 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200893
894 mc34708: pmic@41 {
895 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700896 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200897 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700898 };
899
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100900 bootcount@0 {
901 compatible = "u-boot,bootcount-rtc";
902 rtc = <&rtc_1>;
903 offset = <0x13>;
904 };
905
Michal Simekf692b472020-05-28 11:48:55 +0200906 bootcount {
907 compatible = "u-boot,bootcount-i2c-eeprom";
908 i2c-eeprom = <&bootcount_i2c>;
909 };
910
Nandor Hanc50b21b2021-06-10 15:40:38 +0300911 bootcount_4@0 {
912 compatible = "u-boot,bootcount-syscon";
913 syscon = <&syscon0>;
914 reg = <0x0 0x04>, <0x0 0x04>;
915 reg-names = "syscon_reg", "offset";
916 };
917
918 bootcount_2@0 {
919 compatible = "u-boot,bootcount-syscon";
920 syscon = <&syscon0>;
921 reg = <0x0 0x04>, <0x0 0x02> ;
922 reg-names = "syscon_reg", "offset";
923 };
924
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100925 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100926 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100927 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100928 vdd-supply = <&buck2>;
929 vss-microvolts = <0>;
930 };
931
Mark Kettenisfb574622021-10-23 16:58:02 +0200932 iommu: iommu@0 {
933 compatible = "sandbox,iommu";
934 #iommu-cells = <0>;
935 };
936
Simon Glass02554352020-02-06 09:55:00 -0700937 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700938 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700939 interrupt-controller;
940 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700941 };
942
Simon Glass3c97c4f2016-01-18 19:52:26 -0700943 lcd {
Simon Glass8c103c32023-02-13 08:56:33 -0700944 bootph-all;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700945 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200946 pinctrl-names = "default";
947 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700948 xres = <1366>;
949 yres = <768>;
950 };
951
Simon Glass3c43fba2015-07-06 12:54:34 -0600952 leds {
953 compatible = "gpio-leds";
954
955 iracibble {
956 gpios = <&gpio_a 1 0>;
957 label = "sandbox:red";
958 };
959
960 martinet {
961 gpios = <&gpio_a 2 0>;
962 label = "sandbox:green";
963 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200964
965 default_on {
966 gpios = <&gpio_a 5 0>;
967 label = "sandbox:default_on";
968 default-state = "on";
969 };
970
971 default_off {
972 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400973 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200974 default-state = "off";
975 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600976 };
977
Paul Doelle1fc45d62022-07-04 09:00:25 +0000978 wdt-gpio-toggle {
Simon Glassbc003ca2023-08-10 09:53:13 -0600979 gpios = <&gpio_a 8 0>;
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200980 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200981 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000982 hw_algo = "toggle";
983 always-running;
984 };
985
986 wdt-gpio-level {
987 gpios = <&gpio_a 7 0>;
988 compatible = "linux,wdt-gpio";
989 hw_margin_ms = <100>;
990 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200991 always-running;
992 };
993
Stephen Warren8961b522016-05-16 17:41:37 -0600994 mbox: mbox {
995 compatible = "sandbox,mbox";
996 #mbox-cells = <1>;
997 };
998
999 mbox-test {
1000 compatible = "sandbox,mbox-test";
1001 mboxes = <&mbox 100>, <&mbox 1>;
1002 mbox-names = "other", "test";
1003 };
1004
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001005 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001006 #address-cells = <1>;
1007 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -04001008 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001009 cpu1: cpu@1 {
1010 device_type = "cpu";
1011 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -04001012 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001013 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001014 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001015 };
Mario Sixfa44b532018-08-06 10:23:44 +02001016
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001017 cpu2: cpu@2 {
1018 device_type = "cpu";
1019 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001020 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001021 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001022 };
Mario Sixfa44b532018-08-06 10:23:44 +02001023
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001024 cpu3: cpu@3 {
1025 device_type = "cpu";
1026 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001027 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001028 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001029 };
Mario Sixfa44b532018-08-06 10:23:44 +02001030 };
1031
Dave Gerlach21e3c212020-07-15 23:39:58 -05001032 chipid: chipid {
1033 compatible = "sandbox,soc";
1034 };
1035
Simon Glasse96fa6c2018-12-10 10:37:34 -07001036 i2s: i2s {
1037 compatible = "sandbox,i2s";
1038 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -07001039 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -07001040 };
1041
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +02001042 nop-test_0 {
1043 compatible = "sandbox,nop_sandbox1";
1044 nop-test_1 {
1045 compatible = "sandbox,nop_sandbox2";
1046 bind = "True";
1047 };
1048 nop-test_2 {
1049 compatible = "sandbox,nop_sandbox2";
1050 bind = "False";
1051 };
1052 };
1053
Roger Quadros2c120372022-10-20 16:30:46 +03001054 memory-controller {
1055 compatible = "sandbox,memory";
1056 };
1057
Mario Six004e67c2018-07-31 14:24:14 +02001058 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -04001059 #address-cells = <1>;
1060 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +02001061 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -04001062
1063 eth5_addr: mac-address@10 {
1064 reg = <0x10 6>;
1065 };
Mario Six004e67c2018-07-31 14:24:14 +02001066 };
1067
Simon Glasse48eeb92017-04-23 20:02:07 -06001068 mmc2 {
1069 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -06001070 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -06001071 };
1072
Simon Glassfb1451b2022-04-24 23:31:24 -06001073 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001074 mmc1 {
1075 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001076 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001077 };
1078
Simon Glassfb1451b2022-04-24 23:31:24 -06001079 /* This is used for the fastboot tests */
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301080 mmc0: mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001081 compatible = "sandbox,mmc";
1082 };
1083
Simon Glass77bec9e2022-10-20 18:23:20 -06001084 /* This is used for VBE VPL tests */
1085 mmc3 {
1086 status = "disabled";
1087 compatible = "sandbox,mmc";
1088 filename = "image.bin";
1089 non-removable;
1090 };
1091
Simon Glassd985f1d2023-01-06 08:52:41 -06001092 /* This is used for bootstd bootmenu tests */
1093 mmc4 {
1094 status = "disabled";
1095 compatible = "sandbox,mmc";
1096 filename = "mmc4.img";
1097 };
1098
Simon Glassd08db022023-08-24 13:55:41 -06001099 /* This is used for ChromiumOS tests */
1100 mmc5 {
1101 status = "disabled";
1102 compatible = "sandbox,mmc";
1103 filename = "mmc5.img";
1104 };
1105
Alexander Gendin04291ee2023-10-09 01:24:36 +00001106 /* This is used for mbr tests */
1107 mmc6 {
1108 status = "disabled";
1109 compatible = "sandbox,mmc";
1110 filename = "mmc6.img";
1111 };
1112
Simon Glassb45c8332019-02-16 20:24:50 -07001113 pch {
1114 compatible = "sandbox,pch";
1115 };
1116
Tom Rini42c64d12020-02-11 12:41:23 -05001117 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001118 compatible = "sandbox,pci";
1119 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001120 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001121 #address-cells = <3>;
1122 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001123 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001124 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis08386da2023-01-21 20:27:57 +01001125 iommu-map = <0x0010 &iommu 0 1>;
1126 iommu-map-mask = <0xfffffff8>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001127 pci@0,0 {
1128 compatible = "pci-generic";
1129 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001130 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001131 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001132 pci@1,0 {
1133 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001134 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glassf69d3d62023-09-26 08:14:58 -06001135 reg = <0x02000814 0 0 0x80 0
1136 0x01000810 0 0 0xc0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001137 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001138 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001139 p2sb-pci@2,0 {
1140 compatible = "sandbox,p2sb";
1141 reg = <0x02001010 0 0 0 0>;
1142 sandbox,emul = <&p2sb_emul>;
1143
1144 adder {
1145 intel,p2sb-port-id = <3>;
1146 compatible = "sandbox,adder";
1147 };
1148 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001149 pci@1e,0 {
1150 compatible = "sandbox,pmc";
1151 reg = <0xf000 0 0 0 0>;
1152 sandbox,emul = <&pmc_emul1e>;
1153 acpi-base = <0x400>;
1154 gpe0-dwx-mask = <0xf>;
1155 gpe0-dwx-shift-base = <4>;
1156 gpe0-dw = <6 7 9>;
1157 gpe0-sts = <0x20>;
1158 gpe0-en = <0x30>;
1159 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001160 pci@1f,0 {
1161 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001162 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glassf69d3d62023-09-26 08:14:58 -06001163 reg = <0x0100f810 0 0 0x100 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001164 sandbox,emul = <&swap_case_emul0_1f>;
1165 };
1166 };
1167
1168 pci-emul0 {
1169 compatible = "sandbox,pci-emul-parent";
1170 swap_case_emul0_0: emul0@0,0 {
1171 compatible = "sandbox,swap-case";
1172 };
1173 swap_case_emul0_1: emul0@1,0 {
1174 compatible = "sandbox,swap-case";
1175 use-ea;
1176 };
1177 swap_case_emul0_1f: emul0@1f,0 {
1178 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001179 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001180 p2sb_emul: emul@2,0 {
1181 compatible = "sandbox,p2sb-emul";
1182 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001183 pmc_emul1e: emul@1e,0 {
1184 compatible = "sandbox,pmc-emul";
1185 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001186 };
1187
Tom Rini42c64d12020-02-11 12:41:23 -05001188 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001189 compatible = "sandbox,pci";
1190 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001191 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001192 #address-cells = <3>;
1193 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001194 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001195 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001196 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001197 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001198 0x0c 0x00 0x1234 0x5678
1199 0x10 0x00 0x1234 0x5678>;
1200 pci@10,0 {
1201 reg = <0x8000 0 0 0 0>;
1202 };
Bin Mengdee4d752018-08-03 01:14:41 -07001203 };
1204
Tom Rini42c64d12020-02-11 12:41:23 -05001205 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001206 compatible = "sandbox,pci";
1207 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001208 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001209 #address-cells = <3>;
1210 #size-cells = <2>;
1211 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1212 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1213 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1214 pci@1f,0 {
1215 compatible = "pci-generic";
1216 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001217 sandbox,emul = <&swap_case_emul2_1f>;
1218 };
1219 };
1220
1221 pci-emul2 {
1222 compatible = "sandbox,pci-emul-parent";
1223 swap_case_emul2_1f: emul2@1f,0 {
1224 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001225 };
1226 };
1227
Ramon Friedbb413332019-04-27 11:15:23 +03001228 pci_ep: pci_ep {
1229 compatible = "sandbox,pci_ep";
1230 };
1231
Simon Glass98561572017-04-23 20:10:44 -06001232 probing {
1233 compatible = "simple-bus";
1234 test1 {
1235 compatible = "denx,u-boot-probe-test";
1236 };
1237
1238 test2 {
1239 compatible = "denx,u-boot-probe-test";
1240 };
1241
1242 test3 {
1243 compatible = "denx,u-boot-probe-test";
1244 };
1245
1246 test4 {
1247 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001248 first-syscon = <&syscon0>;
1249 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001250 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001251 };
1252 };
1253
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001254 pwrdom: power-domain {
1255 compatible = "sandbox,power-domain";
1256 #power-domain-cells = <1>;
1257 };
1258
1259 power-domain-test {
1260 compatible = "sandbox,power-domain-test";
1261 power-domains = <&pwrdom 2>;
1262 };
1263
Simon Glass5d9a88f2018-10-01 12:22:40 -06001264 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001265 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001266 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001267 pinctrl-names = "default";
1268 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001269 };
1270
1271 pwm2 {
1272 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001273 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001274 };
1275
Simon Glass64ce0ca2015-07-06 12:54:31 -06001276 ram {
1277 compatible = "sandbox,ram";
1278 };
1279
Simon Glass5010d982015-07-06 12:54:29 -06001280 reset@0 {
1281 compatible = "sandbox,warm-reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001282 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001283 };
1284
1285 reset@1 {
1286 compatible = "sandbox,reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001287 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001288 };
1289
Stephen Warren4581b712016-06-17 09:43:59 -06001290 resetc: reset-ctl {
1291 compatible = "sandbox,reset-ctl";
1292 #reset-cells = <1>;
1293 };
1294
1295 reset-ctl-test {
1296 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001297 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1298 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001299 };
1300
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301301 rng {
1302 compatible = "sandbox,sandbox-rng";
1303 };
1304
Nishanth Menon52159402015-09-17 15:42:41 -05001305 rproc_1: rproc@1 {
1306 compatible = "sandbox,test-processor";
1307 remoteproc-name = "remoteproc-test-dev1";
1308 };
1309
1310 rproc_2: rproc@2 {
1311 compatible = "sandbox,test-processor";
1312 internal-memory-mapped;
1313 remoteproc-name = "remoteproc-test-dev2";
1314 };
1315
Simon Glass5d9a88f2018-10-01 12:22:40 -06001316 panel {
1317 compatible = "simple-panel";
1318 backlight = <&backlight 0 100>;
1319 };
1320
Simon Glass22c80d52022-09-21 16:21:47 +02001321 scsi {
1322 compatible = "sandbox,scsi";
1323 sandbox,filepath = "scsi.img";
1324 };
1325
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001326 smem@0 {
1327 compatible = "sandbox,smem";
1328 };
1329
Simon Glassd4901892018-12-10 10:37:36 -07001330 sound {
1331 compatible = "sandbox,sound";
1332 cpu {
1333 sound-dai = <&i2s 0>;
1334 };
1335
1336 codec {
1337 sound-dai = <&audio 0>;
1338 };
1339 };
1340
Simon Glass0ae0cb72014-10-13 23:42:11 -06001341 spi@0 {
1342 #address-cells = <1>;
1343 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001344 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001345 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001346 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001347 pinctrl-names = "default";
1348 pinctrl-0 = <&pinmux_spi0_pins>;
1349
Simon Glass0ae0cb72014-10-13 23:42:11 -06001350 spi.bin@0 {
1351 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001352 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001353 spi-max-frequency = <40000000>;
1354 sandbox,filename = "spi.bin";
1355 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001356 spi.bin@1 {
1357 reg = <1>;
1358 compatible = "spansion,m25p16", "jedec,spi-nor";
1359 spi-max-frequency = <50000000>;
1360 sandbox,filename = "spi.bin";
1361 spi-cpol;
1362 spi-cpha;
1363 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001364 };
1365
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001366 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001367 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001368 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001369 };
1370
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001371 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001372 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001373 reg = <0x20 5
1374 0x28 6
1375 0x30 7
1376 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001377 };
1378
Patrick Delaunaya442e612019-03-07 09:57:13 +01001379 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001380 compatible = "simple-mfd", "syscon";
1381 reg = <0x40 5
1382 0x48 6
1383 0x50 7
1384 0x58 8>;
1385 };
1386
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301387 syscon3: syscon@3 {
1388 compatible = "simple-mfd", "syscon";
1389 reg = <0x000100 0x10>;
1390
1391 muxcontroller0: a-mux-controller {
1392 compatible = "mmio-mux";
1393 #mux-control-cells = <1>;
1394
1395 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1396 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1397 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1398 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1399 u-boot,mux-autoprobe;
1400 };
1401 };
1402
1403 muxcontroller1: emul-mux-controller {
1404 compatible = "mux-emul";
1405 #mux-control-cells = <0>;
1406 u-boot,mux-autoprobe;
1407 idle-state = <0xabcd>;
1408 };
1409
Simon Glass93f44e82020-12-16 21:20:27 -07001410 testfdtm0 {
1411 compatible = "denx,u-boot-fdtm-test";
1412 };
1413
1414 testfdtm1: testfdtm1 {
1415 compatible = "denx,u-boot-fdtm-test";
1416 };
1417
1418 testfdtm2 {
1419 compatible = "denx,u-boot-fdtm-test";
1420 };
1421
Sean Anderson7616e362020-09-28 10:52:23 -04001422 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001423 compatible = "sandbox,timer";
1424 clock-frequency = <1000000>;
1425 };
1426
Sean Anderson7616e362020-09-28 10:52:23 -04001427 timer@1 {
1428 compatible = "sandbox,timer";
1429 sandbox,timebase-frequency-fallback;
1430 };
1431
Miquel Raynalb91ad162018-05-15 11:57:27 +02001432 tpm2 {
1433 compatible = "sandbox,tpm2";
1434 };
1435
Simon Glass4fef6572023-02-21 06:24:51 -07001436 tpm {
1437 compatible = "google,sandbox-tpm";
1438 };
1439
Simon Glass171e9912015-05-22 15:42:15 -06001440 uart0: serial {
1441 compatible = "sandbox,serial";
Simon Glass8c103c32023-02-13 08:56:33 -07001442 bootph-all;
Dario Binacchi55322622021-04-11 09:39:50 +02001443 pinctrl-names = "default";
1444 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001445 };
1446
Simon Glasse00cb222015-03-25 12:23:05 -06001447 usb_0: usb@0 {
1448 compatible = "sandbox,usb";
1449 status = "disabled";
1450 hub {
1451 compatible = "sandbox,usb-hub";
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1454 flash-stick {
1455 reg = <0>;
1456 compatible = "sandbox,usb-flash";
1457 };
1458 };
1459 };
1460
1461 usb_1: usb@1 {
1462 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001463 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001464 hub {
1465 compatible = "usb-hub";
1466 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001467 #address-cells = <1>;
1468 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001469 hub-emul {
1470 compatible = "sandbox,usb-hub";
1471 #address-cells = <1>;
1472 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001473 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001474 reg = <0>;
1475 compatible = "sandbox,usb-flash";
1476 sandbox,filepath = "testflash.bin";
1477 };
1478
Simon Glass431cbd62015-11-08 23:48:01 -07001479 flash-stick@1 {
1480 reg = <1>;
1481 compatible = "sandbox,usb-flash";
1482 sandbox,filepath = "testflash1.bin";
1483 };
1484
1485 flash-stick@2 {
1486 reg = <2>;
1487 compatible = "sandbox,usb-flash";
1488 sandbox,filepath = "testflash2.bin";
1489 };
1490
Simon Glassbff1a712015-11-08 23:48:08 -07001491 keyb@3 {
1492 reg = <3>;
1493 compatible = "sandbox,usb-keyb";
1494 };
1495
Simon Glasse00cb222015-03-25 12:23:05 -06001496 };
Michael Wallec03b7612020-06-02 01:47:07 +02001497
1498 usbstor@1 {
1499 reg = <1>;
1500 };
1501 usbstor@3 {
1502 reg = <3>;
1503 };
Simon Glasse00cb222015-03-25 12:23:05 -06001504 };
1505 };
1506
1507 usb_2: usb@2 {
1508 compatible = "sandbox,usb";
1509 status = "disabled";
1510 };
1511
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001512 spmi: spmi@0 {
1513 compatible = "sandbox,spmi";
1514 #address-cells = <0x1>;
1515 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001516 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001517 pm8916@0 {
1518 compatible = "qcom,spmi-pmic";
1519 reg = <0x0 0x1>;
1520 #address-cells = <0x1>;
1521 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001522 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001523
1524 spmi_gpios: gpios@c000 {
1525 compatible = "qcom,pm8916-gpio";
1526 reg = <0xc000 0x400>;
1527 gpio-controller;
1528 gpio-count = <4>;
1529 #gpio-cells = <2>;
1530 gpio-bank-name="spmi";
1531 };
1532 };
1533 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001534
1535 wdt0: wdt@0 {
1536 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001537 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001538 };
Rob Clarkf2006802018-01-10 11:33:30 +01001539
Mario Six957983e2018-08-09 14:51:19 +02001540 axi: axi@0 {
1541 compatible = "sandbox,axi";
1542 #address-cells = <0x1>;
1543 #size-cells = <0x1>;
1544 store@0 {
1545 compatible = "sandbox,sandbox_store";
1546 reg = <0x0 0x400>;
1547 };
1548 };
1549
Rob Clarkf2006802018-01-10 11:33:30 +01001550 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001551 #address-cells = <1>;
1552 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001553 setting = "sunrise ohoka";
1554 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001555 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001556 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001557 chosen-test {
1558 compatible = "denx,u-boot-fdt-test";
1559 reg = <9 1>;
1560 };
1561 };
Mario Sixe8d52912018-03-12 14:53:33 +01001562
1563 translation-test@8000 {
1564 compatible = "simple-bus";
1565 reg = <0x8000 0x4000>;
1566
1567 #address-cells = <0x2>;
1568 #size-cells = <0x1>;
1569
1570 ranges = <0 0x0 0x8000 0x1000
1571 1 0x100 0x9000 0x1000
1572 2 0x200 0xA000 0x1000
1573 3 0x300 0xB000 0x1000
1574 >;
1575
Fabien Dessenne641067f2019-05-31 15:11:30 +02001576 dma-ranges = <0 0x000 0x10000000 0x1000
1577 1 0x100 0x20000000 0x1000
1578 >;
1579
Mario Sixe8d52912018-03-12 14:53:33 +01001580 dev@0,0 {
1581 compatible = "denx,u-boot-fdt-dummy";
1582 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001583 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001584 };
1585
1586 dev@1,100 {
1587 compatible = "denx,u-boot-fdt-dummy";
1588 reg = <1 0x100 0x1000>;
1589
1590 };
1591
1592 dev@2,200 {
1593 compatible = "denx,u-boot-fdt-dummy";
1594 reg = <2 0x200 0x1000>;
1595 };
1596
1597
1598 noxlatebus@3,300 {
1599 compatible = "simple-bus";
1600 reg = <3 0x300 0x1000>;
1601
1602 #address-cells = <0x1>;
1603 #size-cells = <0x0>;
1604
1605 dev@42 {
1606 compatible = "denx,u-boot-fdt-dummy";
1607 reg = <0x42>;
1608 };
1609 };
1610 };
Mario Six4eea5312018-09-27 09:19:31 +02001611
Dzmitry Sankouski298ffdd2023-01-22 18:21:23 +03001612 ofnode-foreach {
1613 compatible = "foreach";
1614
1615 first {
1616 prop1 = <1>;
1617 prop2 = <2>;
1618 };
1619
1620 second {
1621 prop1 = <1>;
1622 prop2 = <2>;
1623 };
1624 };
1625
Mario Six4eea5312018-09-27 09:19:31 +02001626 osd {
1627 compatible = "sandbox,sandbox_osd";
1628 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001629
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001630 sandbox_tee {
1631 compatible = "sandbox,tee";
1632 };
Bin Meng4f89d492018-10-15 02:21:26 -07001633
1634 sandbox_virtio1 {
1635 compatible = "sandbox,virtio1";
Simon Glass00fc8ca2023-01-17 10:47:51 -07001636 virtio-type = <4>; /* rng */
Bin Meng4f89d492018-10-15 02:21:26 -07001637 };
1638
1639 sandbox_virtio2 {
1640 compatible = "sandbox,virtio2";
1641 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001642
Simon Glass00fc8ca2023-01-17 10:47:51 -07001643 sandbox-virtio-blk {
1644 compatible = "sandbox,virtio1";
1645 virtio-type = <2>; /* block */
1646 };
1647
Etienne Carriere87d4f272020-09-09 18:44:05 +02001648 sandbox_scmi {
1649 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001650 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001651 resets = <&reset_scmi 3>;
1652 regul0-supply = <&regul0_scmi>;
1653 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001654 };
1655
Patrice Chotardf41a8242018-10-24 14:10:23 +02001656 pinctrl {
1657 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001658
Sean Anderson7f0f1802020-09-14 11:01:57 -04001659 pinctrl-names = "default", "alternate";
1660 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1661 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001662
Sean Anderson7f0f1802020-09-14 11:01:57 -04001663 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001664 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001665 pins = "P5";
1666 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001667 bias-pull-up;
1668 input-disable;
1669 };
1670 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001671 pins = "P6";
1672 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001673 output-high;
1674 drive-open-drain;
1675 };
1676 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001677 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001678 bias-pull-down;
1679 input-enable;
1680 };
1681 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001682 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001683 bias-disable;
1684 };
1685 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001686
1687 pinctrl_i2c: i2c {
1688 groups {
1689 groups = "I2C_UART";
1690 function = "I2C";
1691 };
1692
1693 pins {
1694 pins = "P0", "P1";
1695 drive-open-drain;
1696 };
1697 };
1698
1699 pinctrl_i2s: i2s {
1700 groups = "SPI_I2S";
1701 function = "I2S";
1702 };
1703
1704 pinctrl_spi: spi {
1705 groups = "SPI_I2S";
1706 function = "SPI";
1707
1708 cs {
1709 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1710 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1711 };
1712 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001713 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001714
Dario Binacchi55322622021-04-11 09:39:50 +02001715 pinctrl-single-no-width {
1716 compatible = "pinctrl-single";
1717 reg = <0x0000 0x238>;
1718 #pinctrl-cells = <1>;
1719 pinctrl-single,function-mask = <0x7f>;
1720 };
1721
1722 pinctrl-single-pins {
1723 compatible = "pinctrl-single";
1724 reg = <0x0000 0x238>;
1725 #pinctrl-cells = <1>;
1726 pinctrl-single,register-width = <32>;
1727 pinctrl-single,function-mask = <0x7f>;
1728
1729 pinmux_pwm_pins: pinmux_pwm_pins {
1730 pinctrl-single,pins = < 0x48 0x06 >;
1731 };
1732
1733 pinmux_spi0_pins: pinmux_spi0_pins {
1734 pinctrl-single,pins = <
1735 0x190 0x0c
1736 0x194 0x0c
1737 0x198 0x23
1738 0x19c 0x0c
1739 >;
1740 };
1741
1742 pinmux_uart0_pins: pinmux_uart0_pins {
1743 pinctrl-single,pins = <
1744 0x70 0x30
1745 0x74 0x00
1746 >;
1747 };
1748 };
1749
1750 pinctrl-single-bits {
1751 compatible = "pinctrl-single";
1752 reg = <0x0000 0x50>;
1753 #pinctrl-cells = <2>;
1754 pinctrl-single,bit-per-mux;
1755 pinctrl-single,register-width = <32>;
1756 pinctrl-single,function-mask = <0xf>;
1757
1758 pinmux_i2c0_pins: pinmux_i2c0_pins {
1759 pinctrl-single,bits = <
1760 0x10 0x00002200 0x0000ff00
1761 >;
1762 };
1763
1764 pinmux_lcd_pins: pinmux_lcd_pins {
1765 pinctrl-single,bits = <
1766 0x40 0x22222200 0xffffff00
1767 0x44 0x22222222 0xffffffff
1768 0x48 0x00000022 0x000000ff
1769 0x48 0x02000000 0x0f000000
1770 0x4c 0x02000022 0x0f0000ff
1771 >;
1772 };
1773 };
1774
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001775 hwspinlock@0 {
1776 compatible = "sandbox,hwspinlock";
1777 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001778
1779 dma: dma {
1780 compatible = "sandbox,dma";
1781 #dma-cells = <1>;
1782
1783 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1784 dma-names = "m2m", "tx0", "rx0";
1785 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001786
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001787 /*
1788 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1789 * end of the test. If parent mdio is removed first, clean-up of the
1790 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1791 * active at the end of the test. That it turn doesn't allow the mdio
1792 * class to be destroyed, triggering an error.
1793 */
1794 mdio-mux-test {
1795 compatible = "sandbox,mdio-mux";
1796 #address-cells = <1>;
1797 #size-cells = <0>;
1798 mdio-parent-bus = <&mdio>;
1799
1800 mdio-ch-test@0 {
1801 reg = <0>;
1802 };
1803 mdio-ch-test@1 {
1804 reg = <1>;
1805 };
1806 };
1807
1808 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001809 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001810 #address-cells = <1>;
1811 #size-cells = <0>;
1812
1813 ethphy1: ethernet-phy@1 {
1814 reg = <1>;
1815 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001816 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001817
1818 pm-bus-test {
1819 compatible = "simple-pm-bus";
1820 clocks = <&clk_sandbox 4>;
1821 power-domains = <&pwrdom 1>;
1822 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001823
1824 resetc2: syscon-reset {
1825 compatible = "syscon-reset";
1826 #reset-cells = <1>;
1827 regmap = <&syscon0>;
1828 offset = <1>;
1829 mask = <0x27FFFFFF>;
1830 assert-high = <0>;
1831 };
1832
1833 syscon-reset-test {
1834 compatible = "sandbox,misc_sandbox";
1835 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1836 reset-names = "valid", "no_mask", "out_of_range";
1837 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301838
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001839 sysinfo {
1840 compatible = "sandbox,sysinfo-sandbox";
1841 };
1842
Sean Anderson1cbfed82021-04-20 10:50:58 -04001843 sysinfo-gpio {
1844 compatible = "gpio-sysinfo";
1845 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1846 revisions = <19>, <5>;
1847 names = "rev_a", "foo";
1848 };
1849
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301850 some_regmapped-bus {
1851 #address-cells = <0x1>;
1852 #size-cells = <0x1>;
1853
1854 ranges = <0x0 0x0 0x10>;
1855 compatible = "simple-bus";
1856
1857 regmap-test_0 {
1858 reg = <0 0x10>;
1859 compatible = "sandbox,regmap_test";
1860 };
1861 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001862
1863 thermal {
1864 compatible = "sandbox,thermal";
1865 };
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301866
1867 fwu-mdata {
1868 compatible = "u-boot,fwu-mdata-gpt";
1869 fwu-mdata-store = <&mmc0>;
1870 };
Abdellatif El Khlificc89b7c2023-04-17 10:11:55 +01001871
1872 nvmxip-qspi1@08000000 {
1873 compatible = "nvmxip,qspi";
1874 reg = <0x08000000 0x00200000>;
1875 lba_shift = <9>;
1876 lba = <4096>;
1877 };
1878
1879 nvmxip-qspi2@08200000 {
1880 compatible = "nvmxip,qspi";
1881 reg = <0x08200000 0x00100000>;
1882 lba_shift = <9>;
1883 lba = <2048>;
1884 };
Svyatoslav Ryhel8b215e12023-04-25 10:57:21 +03001885
1886 extcon {
1887 compatible = "sandbox,extcon";
1888 };
Abdellatif El Khlifia09852d2023-08-04 14:33:41 +01001889
1890 arm-ffa-emul {
1891 compatible = "sandbox,arm-ffa-emul";
1892
1893 sandbox-arm-ffa {
1894 compatible = "sandbox,arm-ffa";
1895 };
1896 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001897};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001898
1899#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001900#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001901
1902#ifdef CONFIG_SANDBOX_VPL
1903#include "sandbox_vpl.dtsi"
1904#endif
Simon Glass82cafee2023-06-01 10:23:01 -06001905
1906#include "cedit.dtsi"