blob: bb2ddd9bf29500ba53dd0f5507f553c18852e45a [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James5999ea22023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010018
Simon Glass2e7d35d2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070024
Simon Glass00606d72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassd08db022023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Bin Mengdee4d752018-08-03 01:14:41 -070045 pci0 = &pci0;
46 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070047 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020048 remoteproc0 = &rproc_1;
49 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060050 rtc0 = &rtc_0;
51 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060052 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020053 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070054 testbus3 = "/some-bus";
55 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070056 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070057 testfdt3 = "/b-test";
58 testfdt5 = "/some-bus/c-test@5";
59 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070060 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020061 fdt-dummy0 = "/translation-test@8000/dev@0,0";
62 fdt-dummy1 = "/translation-test@8000/dev@1,100";
63 fdt-dummy2 = "/translation-test@8000/dev@2,200";
64 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060065 usb0 = &usb_0;
66 usb1 = &usb_1;
67 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020068 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020069 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060070 };
71
Eddie James5999ea22023-10-24 10:43:51 -050072 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 event_log: tcg_event_log {
78 no-map;
79 reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
80 };
81 };
82
Simon Glass8de98962022-10-20 18:23:15 -060083 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020084 };
85
Rasmus Villemoes8c728422021-04-21 11:06:55 +020086 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060087 testing-bool;
88 testing-int = <123>;
89 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020090 environment {
91 from_fdt = "yes";
92 fdt_env_path = "";
93 };
94 };
95
Michal Simekdb5e3492023-08-31 08:59:05 +020096 options {
97 u-boot {
98 compatible = "u-boot,config";
99 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek44f35e12023-08-31 09:04:27 +0200100 bootscr-flash-offset = /bits/ 64 <0>;
101 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simekdb5e3492023-08-31 08:59:05 +0200102 };
103 };
104
Simon Glassfb1451b2022-04-24 23:31:24 -0600105 bootstd {
Simon Glass8c103c32023-02-13 08:56:33 -0700106 bootph-verify;
Simon Glassfb1451b2022-04-24 23:31:24 -0600107 compatible = "u-boot,boot-std";
108
109 filename-prefixes = "/", "/boot/";
110 bootdev-order = "mmc2", "mmc1";
111
Simon Glass79f66352023-05-10 16:34:46 -0600112 extlinux {
113 compatible = "u-boot,extlinux";
Simon Glassfb1451b2022-04-24 23:31:24 -0600114 };
115
116 efi {
117 compatible = "u-boot,distro-efi";
118 };
Simon Glassa56f6632022-10-20 18:23:14 -0600119
Simon Glassd985f1d2023-01-06 08:52:41 -0600120 theme {
121 font-size = <30>;
Simon Glass7230fdb2023-06-01 10:23:00 -0600122 menu-inset = <3>;
123 menuitem-gap-y = <1>;
Simon Glassd985f1d2023-01-06 08:52:41 -0600124 };
125
Simon Glass2045ca52023-08-14 16:40:30 -0600126 cedit-theme {
127 font-size = <30>;
128 menu-inset = <3>;
129 menuitem-gap-y = <1>;
130 };
131
Simon Glass77bec9e2022-10-20 18:23:20 -0600132 /*
133 * This is used for the VBE OS-request tests. A FAT filesystem
134 * created in a partition with the VBE information appearing
135 * before the parititon starts
136 */
Simon Glassa56f6632022-10-20 18:23:14 -0600137 firmware0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700138 bootph-verify;
Simon Glassa56f6632022-10-20 18:23:14 -0600139 compatible = "fwupd,vbe-simple";
140 storage = "mmc1";
141 skip-offset = <0x200>;
142 area-start = <0x400>;
143 area-size = <0x1000>;
144 state-offset = <0x400>;
145 state-size = <0x40>;
146 version-offset = <0x800>;
147 version-size = <0x100>;
148 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600149
150 /*
151 * This is used for the VBE VPL tests. The MMC device holds the
152 * binman image.bin file. The test progresses through each phase
153 * of U-Boot, loading each in turn from MMC.
154 *
155 * Note that the test enables this node (and mmc3) before
156 * running U-Boot
157 */
158 firmware1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700159 bootph-verify;
Simon Glass77bec9e2022-10-20 18:23:20 -0600160 status = "disabled";
161 compatible = "fwupd,vbe-simple";
162 storage = "mmc3";
Simon Glass74b75aa2023-04-02 14:01:24 +1200163 skip-offset = <0x800000>;
Simon Glass77bec9e2022-10-20 18:23:20 -0600164 area-start = <0>;
165 area-size = <0xe00000>;
166 state-offset = <0xdffc00>;
167 state-size = <0x40>;
168 version-offset = <0xdffe00>;
169 version-size = <0x100>;
170 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600171 };
172
Simon Glass82cafee2023-06-01 10:23:01 -0600173 cedit: cedit {
174 };
175
Andrew Scull0518e7a2022-05-30 10:00:12 +0000176 fuzzing-engine {
177 compatible = "sandbox,fuzzing-engine";
178 };
179
Nandor Hanf9db2f12021-06-10 16:56:44 +0300180 reboot-mode0 {
181 compatible = "reboot-mode-gpio";
182 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
183 u-boot,env-variable = "bootstatus";
184 mode-test = <0x01>;
185 mode-download = <0x03>;
186 };
187
Nandor Hanc74675b2021-06-10 16:56:45 +0300188 reboot_mode1: reboot-mode@14 {
189 compatible = "reboot-mode-rtc";
190 rtc = <&rtc_0>;
191 reg = <0x30 4>;
192 u-boot,env-variable = "bootstatus";
193 big-endian;
194 mode-test = <0x21969147>;
195 mode-download = <0x51939147>;
196 };
197
Simon Glassce6d99a2018-12-10 10:37:33 -0700198 audio: audio-codec {
199 compatible = "sandbox,audio-codec";
200 #sound-dai-cells = <1>;
201 };
202
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200203 buttons {
204 compatible = "gpio-keys";
205
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200206 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200207 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200208 label = "button1";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300209 linux,code = <BTN_1>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200210 };
211
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200212 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200213 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200214 label = "button2";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300215 linux,code = <BTN_2>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200216 };
217 };
218
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100219 buttons2 {
220 compatible = "adc-keys";
221 io-channels = <&adc 3>;
222 keyup-threshold-microvolt = <3000000>;
223
224 button-up {
225 label = "button3";
226 linux,code = <KEY_F3>;
227 press-threshold-microvolt = <1500000>;
228 };
229
230 button-down {
231 label = "button4";
232 linux,code = <KEY_F4>;
233 press-threshold-microvolt = <1000000>;
234 };
235
236 button-enter {
237 label = "button5";
238 linux,code = <KEY_F5>;
239 press-threshold-microvolt = <500000>;
240 };
241 };
242
Simon Glasse96fa6c2018-12-10 10:37:34 -0700243 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600244 reg = <0 0>;
245 compatible = "google,cros-ec-sandbox";
246
247 /*
248 * This describes the flash memory within the EC. Note
249 * that the STM32L flash erases to 0, not 0xff.
250 */
251 flash {
252 image-pos = <0x08000000>;
253 size = <0x20000>;
254 erase-value = <0>;
255
256 /* Information for sandbox */
257 ro {
258 image-pos = <0>;
259 size = <0xf000>;
260 };
261 wp-ro {
262 image-pos = <0xf000>;
263 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700264 used = <0x884>;
265 compress = "lz4";
266 uncomp-size = <0xcf8>;
267 hash {
268 algo = "sha256";
269 value = [00 01 02 03 04 05 06 07
270 08 09 0a 0b 0c 0d 0e 0f
271 10 11 12 13 14 15 16 17
272 18 19 1a 1b 1c 1d 1e 1f];
273 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600274 };
275 rw {
276 image-pos = <0x10000>;
277 size = <0x10000>;
278 };
279 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300280
281 cros_ec_pwm: cros-ec-pwm {
282 compatible = "google,cros-ec-pwm";
283 #pwm-cells = <1>;
284 };
285
Simon Glasse6c5c942018-10-01 12:22:08 -0600286 };
287
Yannick Fertré23f965a2019-10-07 15:29:05 +0200288 dsi_host: dsi_host {
289 compatible = "sandbox,dsi-host";
290 };
291
Simon Glass2e7d35d2014-02-26 15:59:21 -0700292 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600293 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700294 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600295 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700296 ping-add = <0>;
Simon Glass8c103c32023-02-13 08:56:33 -0700297 bootph-all;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100298 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
299 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700300 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100301 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
302 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
303 <&gpio_b 7 GPIO_IN 3 2 1>,
304 <&gpio_b 8 GPIO_OUT 3 2 1>,
305 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100306 test3-gpios =
307 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
308 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
309 <&gpio_c 2 GPIO_OUT>,
310 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
311 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200312 <&gpio_c 5 GPIO_IN>,
313 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
314 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530315 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
316 test5-gpios = <&gpio_a 19>;
317
Simon Glassfb933d02021-10-23 17:26:04 -0600318 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200319 int8-value = /bits/ 8 <0x12>;
320 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700321 int-value = <1234>;
322 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200323 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200324 int-array = <5678 9123 4567>;
Michal Simekfa12dfa2023-08-25 11:37:46 +0200325 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glass06679002020-07-07 13:11:58 -0600326 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700327 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600328 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200329 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530330
331 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
332 <&muxcontroller0 2>, <&muxcontroller0 3>,
333 <&muxcontroller1>;
334 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
335 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100336 display-timings {
337 timing0: 240x320 {
338 clock-frequency = <6500000>;
339 hactive = <240>;
340 vactive = <320>;
341 hfront-porch = <6>;
342 hback-porch = <7>;
343 hsync-len = <1>;
344 vback-porch = <5>;
345 vfront-porch = <8>;
346 vsync-len = <2>;
347 hsync-active = <1>;
348 vsync-active = <0>;
349 de-active = <1>;
350 pixelclk-active = <1>;
351 interlaced;
352 doublescan;
353 doubleclk;
354 };
355 timing1: 480x800 {
356 clock-frequency = <9000000>;
357 hactive = <480>;
358 vactive = <800>;
359 hfront-porch = <10>;
360 hback-porch = <59>;
361 hsync-len = <12>;
362 vback-porch = <15>;
363 vfront-porch = <17>;
364 vsync-len = <16>;
365 hsync-active = <0>;
366 vsync-active = <1>;
367 de-active = <0>;
368 pixelclk-active = <0>;
369 };
370 timing2: 800x480 {
371 clock-frequency = <33500000>;
372 hactive = <800>;
373 vactive = <480>;
374 hback-porch = <89>;
375 hfront-porch = <164>;
376 vback-porch = <23>;
377 vfront-porch = <10>;
378 hsync-len = <11>;
379 vsync-len = <13>;
380 };
381 };
Raphael Gallais-Poucd880582023-05-11 16:36:52 +0200382 panel-timing {
Nikhil M Jain2f3d6a42023-01-31 15:35:15 +0530383 clock-frequency = <6500000>;
384 hactive = <240>;
385 vactive = <320>;
386 hfront-porch = <6>;
387 hback-porch = <7>;
388 hsync-len = <1>;
389 vback-porch = <5>;
390 vfront-porch = <8>;
391 vsync-len = <2>;
392 hsync-active = <1>;
393 vsync-active = <0>;
394 de-active = <1>;
395 pixelclk-active = <1>;
396 interlaced;
397 doublescan;
398 doubleclk;
399 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700400 };
401
402 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600403 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700404 compatible = "not,compatible";
405 };
406
407 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600408 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700409 };
410
Simon Glass5d9a88f2018-10-01 12:22:40 -0600411 backlight: backlight {
412 compatible = "pwm-backlight";
413 enable-gpios = <&gpio_a 1>;
414 power-supply = <&ldo_1>;
415 pwms = <&pwm 0 1000>;
416 default-brightness-level = <5>;
417 brightness-levels = <0 16 32 64 128 170 202 234 255>;
418 };
419
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200420 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200421 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200422 bind-test-child1 {
423 compatible = "sandbox,phy";
424 #phy-cells = <1>;
425 };
426
427 bind-test-child2 {
428 compatible = "simple-bus";
429 };
430 };
431
Simon Glass2e7d35d2014-02-26 15:59:21 -0700432 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600433 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700434 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600435 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700436 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530437
438 mux-controls = <&muxcontroller0 0>;
439 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700440 };
441
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200442 phy_provider0: gen_phy@0 {
443 compatible = "sandbox,phy";
444 #phy-cells = <1>;
445 };
446
447 phy_provider1: gen_phy@1 {
448 compatible = "sandbox,phy";
449 #phy-cells = <0>;
450 broken;
451 };
452
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200453 phy_provider2: gen_phy@2 {
454 compatible = "sandbox,phy";
455 #phy-cells = <0>;
456 };
457
Jonas Karlman14639bf2023-08-31 22:16:35 +0000458 phy_provider3: gen_phy@3 {
459 compatible = "sandbox,phy";
460 #phy-cells = <2>;
461 };
462
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200463 gen_phy_user: gen_phy_user {
464 compatible = "simple-bus";
465 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
466 phy-names = "phy1", "phy2", "phy3";
467 };
468
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200469 gen_phy_user1: gen_phy_user1 {
470 compatible = "simple-bus";
471 phys = <&phy_provider0 0>, <&phy_provider2>;
472 phy-names = "phy1", "phy2";
473 };
474
Jonas Karlman14639bf2023-08-31 22:16:35 +0000475 gen_phy_user2: gen_phy_user2 {
476 compatible = "simple-bus";
477 phys = <&phy_provider3 0 0>;
478 phy-names = "phy1";
479 };
480
Simon Glass2e7d35d2014-02-26 15:59:21 -0700481 some-bus {
482 #address-cells = <1>;
483 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600484 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600485 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600486 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700487 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600488 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700489 compatible = "denx,u-boot-fdt-test";
490 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600491 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700492 ping-add = <5>;
493 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600494 c-test@0 {
495 compatible = "denx,u-boot-fdt-test";
496 reg = <0>;
497 ping-expect = <6>;
498 ping-add = <6>;
499 };
500 c-test@1 {
501 compatible = "denx,u-boot-fdt-test";
502 reg = <1>;
503 ping-expect = <7>;
504 ping-add = <7>;
505 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700506 };
507
508 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600509 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600510 ping-expect = <6>;
511 ping-add = <6>;
512 compatible = "google,another-fdt-test";
513 };
514
515 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600516 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600517 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700518 ping-add = <6>;
519 compatible = "google,another-fdt-test";
520 };
521
Simon Glass9cc36a22015-01-25 08:27:05 -0700522 f-test {
523 compatible = "denx,u-boot-fdt-test";
524 };
525
526 g-test {
527 compatible = "denx,u-boot-fdt-test";
528 };
529
Bin Meng2786cd72018-10-10 22:07:01 -0700530 h-test {
531 compatible = "denx,u-boot-fdt-test1";
532 };
533
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200534 i-test {
535 compatible = "mediatek,u-boot-fdt-test";
536 #address-cells = <1>;
537 #size-cells = <0>;
538
539 subnode@0 {
540 reg = <0>;
541 };
542
543 subnode@1 {
544 reg = <1>;
545 };
546
547 subnode@2 {
548 reg = <2>;
549 };
550 };
551
Simon Glassdc12ebb2019-12-29 21:19:25 -0700552 devres-test {
553 compatible = "denx,u-boot-devres-test";
554 };
555
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530556 another-test {
557 reg = <0 2>;
558 compatible = "denx,u-boot-fdt-test";
559 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
560 test5-gpios = <&gpio_a 19>;
561 };
562
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100563 mmio-bus@0 {
564 #address-cells = <1>;
565 #size-cells = <1>;
566 compatible = "denx,u-boot-test-bus";
567 dma-ranges = <0x10000000 0x00000000 0x00040000>;
568
569 subnode@0 {
570 compatible = "denx,u-boot-fdt-test";
571 };
572 };
573
574 mmio-bus@1 {
575 #address-cells = <1>;
576 #size-cells = <1>;
577 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100578
579 subnode@0 {
580 compatible = "denx,u-boot-fdt-test";
581 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100582 };
583
Simon Glass0f7b1112020-07-07 13:12:06 -0600584 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600585 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600586 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600587 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600588 child {
589 compatible = "denx,u-boot-acpi-test";
590 };
Simon Glassf50cc952020-04-08 16:57:34 -0600591 };
592
Simon Glass0f7b1112020-07-07 13:12:06 -0600593 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600594 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600595 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600596 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600597 };
598
Patrice Chotardee87a092017-09-04 14:55:57 +0200599 clocks {
600 clk_fixed: clk-fixed {
601 compatible = "fixed-clock";
602 #clock-cells = <0>;
603 clock-frequency = <1234>;
604 };
Anup Patelb630d572019-02-25 08:14:55 +0000605
606 clk_fixed_factor: clk-fixed-factor {
607 compatible = "fixed-factor-clock";
608 #clock-cells = <0>;
609 clock-div = <3>;
610 clock-mult = <2>;
611 clocks = <&clk_fixed>;
612 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200613
614 osc {
615 compatible = "fixed-clock";
616 #clock-cells = <0>;
617 clock-frequency = <20000000>;
618 };
Stephen Warren135aa952016-06-17 09:44:00 -0600619 };
620
621 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600622 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600623 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200624 assigned-clocks = <&clk_sandbox 3>;
625 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600626 };
627
628 clk-test {
629 compatible = "sandbox,clk-test";
630 clocks = <&clk_fixed>,
631 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200632 <&clk_sandbox 0>,
633 <&clk_sandbox 3>,
634 <&clk_sandbox 2>;
635 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600636 };
637
Ashok Reddy Soma99b46472023-08-30 10:31:42 +0200638 clk-test2 {
639 compatible = "sandbox,clk-test";
640 assigned-clock-rates = <321>;
641 };
642
643 clk-test3 {
644 compatible = "sandbox,clk-test";
645 assigned-clocks = <&clk_sandbox 1>;
646 };
647
648 clk-test4 {
649 compatible = "sandbox,clk-test";
650 assigned-clock-rates = <654>, <321>;
651 assigned-clocks = <&clk_sandbox 1>;
652 };
653
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200654 ccf: clk-ccf {
655 compatible = "sandbox,clk-ccf";
656 };
657
Simon Glass42b7f422021-12-04 08:56:31 -0700658 efi-media {
659 compatible = "sandbox,efi-media";
660 };
661
Simon Glass171e9912015-05-22 15:42:15 -0600662 eth@10002000 {
663 compatible = "sandbox,eth";
664 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600665 };
666
667 eth_5: eth@10003000 {
668 compatible = "sandbox,eth";
669 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400670 nvmem-cells = <&eth5_addr>;
671 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600672 };
673
Bin Meng71d79712015-08-27 22:25:53 -0700674 eth_3: sbe5 {
675 compatible = "sandbox,eth";
676 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400677 nvmem-cells = <&eth3_addr>;
678 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700679 };
680
Simon Glass171e9912015-05-22 15:42:15 -0600681 eth@10004000 {
682 compatible = "sandbox,eth";
683 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600684 };
685
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200686 phy_eth0: phy-test-eth {
687 compatible = "sandbox,eth";
688 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400689 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200690 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200691 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200692 };
693
Claudiu Manoilff98da02021-03-14 20:14:57 +0800694 dsa_eth0: dsa-test-eth {
695 compatible = "sandbox,eth";
696 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400697 nvmem-cells = <&eth4_addr>;
698 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800699 };
700
701 dsa-test {
702 compatible = "sandbox,dsa";
703
704 ports {
705 #address-cells = <1>;
706 #size-cells = <0>;
707 swp_0: port@0 {
708 reg = <0>;
709 label = "lan0";
710 phy-mode = "rgmii-rxid";
711
712 fixed-link {
713 speed = <100>;
714 full-duplex;
715 };
716 };
717
718 swp_1: port@1 {
719 reg = <1>;
720 label = "lan1";
721 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800722 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800723 };
724
725 port@2 {
726 reg = <2>;
727 ethernet = <&dsa_eth0>;
728
729 fixed-link {
730 speed = <1000>;
731 full-duplex;
732 };
733 };
734 };
735 };
736
Rajan Vaja31b82172018-09-19 03:43:46 -0700737 firmware {
738 sandbox_firmware: sandbox-firmware {
739 compatible = "sandbox,firmware";
740 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200741
Etienne Carriere41d62e22022-02-21 09:22:39 +0100742 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200743 compatible = "sandbox,scmi-agent";
744 #address-cells = <1>;
745 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200746
Etienne Carriere41d62e22022-02-21 09:22:39 +0100747 protocol@10 {
748 reg = <0x10>;
749 };
750
751 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200752 reg = <0x14>;
753 #clock-cells = <1>;
754 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200755
Etienne Carriere41d62e22022-02-21 09:22:39 +0100756 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200757 reg = <0x16>;
758 #reset-cells = <1>;
759 };
Etienne Carriere01242182021-03-08 22:38:07 +0100760
761 protocol@17 {
762 reg = <0x17>;
763
764 regulators {
765 #address-cells = <1>;
766 #size-cells = <0>;
767
Etienne Carriere41d62e22022-02-21 09:22:39 +0100768 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100769 reg = <0>;
770 regulator-name = "sandbox-voltd0";
771 regulator-min-microvolt = <1100000>;
772 regulator-max-microvolt = <3300000>;
773 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100774 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100775 reg = <0x1>;
776 regulator-name = "sandbox-voltd1";
777 regulator-min-microvolt = <1800000>;
778 };
779 };
780 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200781 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700782 };
783
Alexander Dahl1323d082022-09-30 14:04:30 +0200784 fpga {
785 compatible = "sandbox,fpga";
786 };
787
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100788 pinctrl-gpio {
789 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700790
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100791 gpio_a: base-gpios {
792 compatible = "sandbox,gpio";
793 gpio-controller;
794 #gpio-cells = <1>;
795 gpio-bank-name = "a";
796 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200797 hog_input_active_low {
798 gpio-hog;
799 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200800 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200801 };
802 hog_input_active_high {
803 gpio-hog;
804 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200805 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200806 };
807 hog_output_low {
808 gpio-hog;
809 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200810 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200811 };
812 hog_output_high {
813 gpio-hog;
814 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200815 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200816 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100817 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600818
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100819 gpio_b: extra-gpios {
820 compatible = "sandbox,gpio";
821 gpio-controller;
822 #gpio-cells = <5>;
823 gpio-bank-name = "b";
824 sandbox,gpio-count = <10>;
825 };
826
827 gpio_c: pinmux-gpios {
828 compatible = "sandbox,gpio";
829 gpio-controller;
830 #gpio-cells = <2>;
831 gpio-bank-name = "c";
832 sandbox,gpio-count = <10>;
833 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100834 };
835
Simon Glassecc2ed52014-12-10 08:55:55 -0700836 i2c@0 {
837 #address-cells = <1>;
838 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600839 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700840 compatible = "sandbox,i2c";
841 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200842 pinctrl-names = "default";
843 pinctrl-0 = <&pinmux_i2c0_pins>;
844
Simon Glassecc2ed52014-12-10 08:55:55 -0700845 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400846 #address-cells = <1>;
847 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700848 reg = <0x2c>;
849 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700850 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200851 partitions {
852 compatible = "fixed-partitions";
853 #address-cells = <1>;
854 #size-cells = <1>;
855 bootcount_i2c: bootcount@10 {
856 reg = <10 2>;
857 };
858 };
Sean Anderson472caa62022-05-05 13:11:42 -0400859
860 eth3_addr: mac-address@24 {
861 reg = <24 6>;
862 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700863 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200864
Simon Glass52d3bc52015-05-22 15:42:17 -0600865 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400866 #address-cells = <1>;
867 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600868 reg = <0x43>;
869 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700870 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400871
872 eth4_addr: mac-address@40 {
873 reg = <0x40 6>;
874 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600875 };
876
877 rtc_1: rtc@61 {
878 reg = <0x61>;
879 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700880 sandbox,emul = <&emul1>;
881 };
882
883 i2c_emul: emul {
884 reg = <0xff>;
885 compatible = "sandbox,i2c-emul-parent";
886 emul_eeprom: emul-eeprom {
887 compatible = "sandbox,i2c-eeprom";
888 sandbox,filename = "i2c.bin";
889 sandbox,size = <256>;
890 };
891 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700892 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700893 };
894 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700895 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600896 };
897 };
898
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200899 sandbox_pmic: sandbox_pmic {
900 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700901 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200902 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200903
904 mc34708: pmic@41 {
905 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700906 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200907 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700908 };
909
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100910 bootcount@0 {
911 compatible = "u-boot,bootcount-rtc";
912 rtc = <&rtc_1>;
913 offset = <0x13>;
914 };
915
Michal Simekf692b472020-05-28 11:48:55 +0200916 bootcount {
917 compatible = "u-boot,bootcount-i2c-eeprom";
918 i2c-eeprom = <&bootcount_i2c>;
919 };
920
Nandor Hanc50b21b2021-06-10 15:40:38 +0300921 bootcount_4@0 {
922 compatible = "u-boot,bootcount-syscon";
923 syscon = <&syscon0>;
924 reg = <0x0 0x04>, <0x0 0x04>;
925 reg-names = "syscon_reg", "offset";
926 };
927
928 bootcount_2@0 {
929 compatible = "u-boot,bootcount-syscon";
930 syscon = <&syscon0>;
931 reg = <0x0 0x04>, <0x0 0x02> ;
932 reg-names = "syscon_reg", "offset";
933 };
934
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100935 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100936 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100937 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100938 vdd-supply = <&buck2>;
939 vss-microvolts = <0>;
940 };
941
Mark Kettenisfb574622021-10-23 16:58:02 +0200942 iommu: iommu@0 {
943 compatible = "sandbox,iommu";
944 #iommu-cells = <0>;
945 };
946
Simon Glass02554352020-02-06 09:55:00 -0700947 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700948 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700949 interrupt-controller;
950 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700951 };
952
Simon Glass3c97c4f2016-01-18 19:52:26 -0700953 lcd {
Simon Glass8c103c32023-02-13 08:56:33 -0700954 bootph-all;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700955 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200956 pinctrl-names = "default";
957 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700958 xres = <1366>;
959 yres = <768>;
960 };
961
Simon Glass3c43fba2015-07-06 12:54:34 -0600962 leds {
963 compatible = "gpio-leds";
964
965 iracibble {
966 gpios = <&gpio_a 1 0>;
967 label = "sandbox:red";
968 };
969
970 martinet {
971 gpios = <&gpio_a 2 0>;
972 label = "sandbox:green";
973 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200974
975 default_on {
976 gpios = <&gpio_a 5 0>;
977 label = "sandbox:default_on";
978 default-state = "on";
979 };
980
981 default_off {
982 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400983 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200984 default-state = "off";
985 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600986 };
987
Paul Doelle1fc45d62022-07-04 09:00:25 +0000988 wdt-gpio-toggle {
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200989 gpios = <&gpio_a 7 0>;
990 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200991 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000992 hw_algo = "toggle";
993 always-running;
994 };
995
996 wdt-gpio-level {
997 gpios = <&gpio_a 7 0>;
998 compatible = "linux,wdt-gpio";
999 hw_margin_ms = <100>;
1000 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +02001001 always-running;
1002 };
1003
Stephen Warren8961b522016-05-16 17:41:37 -06001004 mbox: mbox {
1005 compatible = "sandbox,mbox";
1006 #mbox-cells = <1>;
1007 };
1008
1009 mbox-test {
1010 compatible = "sandbox,mbox-test";
1011 mboxes = <&mbox 100>, <&mbox 1>;
1012 mbox-names = "other", "test";
1013 };
1014
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001015 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001016 #address-cells = <1>;
1017 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -04001018 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001019 cpu1: cpu@1 {
1020 device_type = "cpu";
1021 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -04001022 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001023 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001024 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001025 };
Mario Sixfa44b532018-08-06 10:23:44 +02001026
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001027 cpu2: cpu@2 {
1028 device_type = "cpu";
1029 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001030 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001031 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001032 };
Mario Sixfa44b532018-08-06 10:23:44 +02001033
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001034 cpu3: cpu@3 {
1035 device_type = "cpu";
1036 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001037 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001038 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001039 };
Mario Sixfa44b532018-08-06 10:23:44 +02001040 };
1041
Dave Gerlach21e3c212020-07-15 23:39:58 -05001042 chipid: chipid {
1043 compatible = "sandbox,soc";
1044 };
1045
Simon Glasse96fa6c2018-12-10 10:37:34 -07001046 i2s: i2s {
1047 compatible = "sandbox,i2s";
1048 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -07001049 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -07001050 };
1051
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +02001052 nop-test_0 {
1053 compatible = "sandbox,nop_sandbox1";
1054 nop-test_1 {
1055 compatible = "sandbox,nop_sandbox2";
1056 bind = "True";
1057 };
1058 nop-test_2 {
1059 compatible = "sandbox,nop_sandbox2";
1060 bind = "False";
1061 };
1062 };
1063
Roger Quadros2c120372022-10-20 16:30:46 +03001064 memory-controller {
1065 compatible = "sandbox,memory";
1066 };
1067
Mario Six004e67c2018-07-31 14:24:14 +02001068 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -04001069 #address-cells = <1>;
1070 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +02001071 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -04001072
1073 eth5_addr: mac-address@10 {
1074 reg = <0x10 6>;
1075 };
Mario Six004e67c2018-07-31 14:24:14 +02001076 };
1077
Simon Glasse48eeb92017-04-23 20:02:07 -06001078 mmc2 {
1079 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -06001080 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -06001081 };
1082
Simon Glassfb1451b2022-04-24 23:31:24 -06001083 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001084 mmc1 {
1085 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001086 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001087 };
1088
Simon Glassfb1451b2022-04-24 23:31:24 -06001089 /* This is used for the fastboot tests */
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301090 mmc0: mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001091 compatible = "sandbox,mmc";
1092 };
1093
Simon Glass77bec9e2022-10-20 18:23:20 -06001094 /* This is used for VBE VPL tests */
1095 mmc3 {
1096 status = "disabled";
1097 compatible = "sandbox,mmc";
1098 filename = "image.bin";
1099 non-removable;
1100 };
1101
Simon Glassd985f1d2023-01-06 08:52:41 -06001102 /* This is used for bootstd bootmenu tests */
1103 mmc4 {
1104 status = "disabled";
1105 compatible = "sandbox,mmc";
1106 filename = "mmc4.img";
1107 };
1108
Simon Glassd08db022023-08-24 13:55:41 -06001109 /* This is used for ChromiumOS tests */
1110 mmc5 {
1111 status = "disabled";
1112 compatible = "sandbox,mmc";
1113 filename = "mmc5.img";
1114 };
1115
Simon Glassb45c8332019-02-16 20:24:50 -07001116 pch {
1117 compatible = "sandbox,pch";
1118 };
1119
Tom Rini42c64d12020-02-11 12:41:23 -05001120 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001121 compatible = "sandbox,pci";
1122 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001123 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001124 #address-cells = <3>;
1125 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001126 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001127 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis08386da2023-01-21 20:27:57 +01001128 iommu-map = <0x0010 &iommu 0 1>;
1129 iommu-map-mask = <0xfffffff8>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001130 pci@0,0 {
1131 compatible = "pci-generic";
1132 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001133 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001134 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001135 pci@1,0 {
1136 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001137 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1138 reg = <0x02000814 0 0 0 0
1139 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001140 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001141 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001142 p2sb-pci@2,0 {
1143 compatible = "sandbox,p2sb";
1144 reg = <0x02001010 0 0 0 0>;
1145 sandbox,emul = <&p2sb_emul>;
1146
1147 adder {
1148 intel,p2sb-port-id = <3>;
1149 compatible = "sandbox,adder";
1150 };
1151 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001152 pci@1e,0 {
1153 compatible = "sandbox,pmc";
1154 reg = <0xf000 0 0 0 0>;
1155 sandbox,emul = <&pmc_emul1e>;
1156 acpi-base = <0x400>;
1157 gpe0-dwx-mask = <0xf>;
1158 gpe0-dwx-shift-base = <4>;
1159 gpe0-dw = <6 7 9>;
1160 gpe0-sts = <0x20>;
1161 gpe0-en = <0x30>;
1162 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001163 pci@1f,0 {
1164 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001165 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1166 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001167 sandbox,emul = <&swap_case_emul0_1f>;
1168 };
1169 };
1170
1171 pci-emul0 {
1172 compatible = "sandbox,pci-emul-parent";
1173 swap_case_emul0_0: emul0@0,0 {
1174 compatible = "sandbox,swap-case";
1175 };
1176 swap_case_emul0_1: emul0@1,0 {
1177 compatible = "sandbox,swap-case";
1178 use-ea;
1179 };
1180 swap_case_emul0_1f: emul0@1f,0 {
1181 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001182 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001183 p2sb_emul: emul@2,0 {
1184 compatible = "sandbox,p2sb-emul";
1185 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001186 pmc_emul1e: emul@1e,0 {
1187 compatible = "sandbox,pmc-emul";
1188 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001189 };
1190
Tom Rini42c64d12020-02-11 12:41:23 -05001191 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001192 compatible = "sandbox,pci";
1193 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001194 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001195 #address-cells = <3>;
1196 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001197 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001198 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001199 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001200 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001201 0x0c 0x00 0x1234 0x5678
1202 0x10 0x00 0x1234 0x5678>;
1203 pci@10,0 {
1204 reg = <0x8000 0 0 0 0>;
1205 };
Bin Mengdee4d752018-08-03 01:14:41 -07001206 };
1207
Tom Rini42c64d12020-02-11 12:41:23 -05001208 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001209 compatible = "sandbox,pci";
1210 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001211 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001212 #address-cells = <3>;
1213 #size-cells = <2>;
1214 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1215 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1216 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1217 pci@1f,0 {
1218 compatible = "pci-generic";
1219 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001220 sandbox,emul = <&swap_case_emul2_1f>;
1221 };
1222 };
1223
1224 pci-emul2 {
1225 compatible = "sandbox,pci-emul-parent";
1226 swap_case_emul2_1f: emul2@1f,0 {
1227 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001228 };
1229 };
1230
Ramon Friedbb413332019-04-27 11:15:23 +03001231 pci_ep: pci_ep {
1232 compatible = "sandbox,pci_ep";
1233 };
1234
Simon Glass98561572017-04-23 20:10:44 -06001235 probing {
1236 compatible = "simple-bus";
1237 test1 {
1238 compatible = "denx,u-boot-probe-test";
1239 };
1240
1241 test2 {
1242 compatible = "denx,u-boot-probe-test";
1243 };
1244
1245 test3 {
1246 compatible = "denx,u-boot-probe-test";
1247 };
1248
1249 test4 {
1250 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001251 first-syscon = <&syscon0>;
1252 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001253 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001254 };
1255 };
1256
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001257 pwrdom: power-domain {
1258 compatible = "sandbox,power-domain";
1259 #power-domain-cells = <1>;
1260 };
1261
1262 power-domain-test {
1263 compatible = "sandbox,power-domain-test";
1264 power-domains = <&pwrdom 2>;
1265 };
1266
Simon Glass5d9a88f2018-10-01 12:22:40 -06001267 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001268 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001269 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001270 pinctrl-names = "default";
1271 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001272 };
1273
1274 pwm2 {
1275 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001276 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001277 };
1278
Simon Glass64ce0ca2015-07-06 12:54:31 -06001279 ram {
1280 compatible = "sandbox,ram";
1281 };
1282
Simon Glass5010d982015-07-06 12:54:29 -06001283 reset@0 {
1284 compatible = "sandbox,warm-reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001285 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001286 };
1287
1288 reset@1 {
1289 compatible = "sandbox,reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001290 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001291 };
1292
Stephen Warren4581b712016-06-17 09:43:59 -06001293 resetc: reset-ctl {
1294 compatible = "sandbox,reset-ctl";
1295 #reset-cells = <1>;
1296 };
1297
1298 reset-ctl-test {
1299 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001300 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1301 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001302 };
1303
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301304 rng {
1305 compatible = "sandbox,sandbox-rng";
1306 };
1307
Nishanth Menon52159402015-09-17 15:42:41 -05001308 rproc_1: rproc@1 {
1309 compatible = "sandbox,test-processor";
1310 remoteproc-name = "remoteproc-test-dev1";
1311 };
1312
1313 rproc_2: rproc@2 {
1314 compatible = "sandbox,test-processor";
1315 internal-memory-mapped;
1316 remoteproc-name = "remoteproc-test-dev2";
1317 };
1318
Simon Glass5d9a88f2018-10-01 12:22:40 -06001319 panel {
1320 compatible = "simple-panel";
1321 backlight = <&backlight 0 100>;
1322 };
1323
Simon Glass22c80d52022-09-21 16:21:47 +02001324 scsi {
1325 compatible = "sandbox,scsi";
1326 sandbox,filepath = "scsi.img";
1327 };
1328
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001329 smem@0 {
1330 compatible = "sandbox,smem";
1331 };
1332
Simon Glassd4901892018-12-10 10:37:36 -07001333 sound {
1334 compatible = "sandbox,sound";
1335 cpu {
1336 sound-dai = <&i2s 0>;
1337 };
1338
1339 codec {
1340 sound-dai = <&audio 0>;
1341 };
1342 };
1343
Simon Glass0ae0cb72014-10-13 23:42:11 -06001344 spi@0 {
1345 #address-cells = <1>;
1346 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001347 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001348 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001349 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001350 pinctrl-names = "default";
1351 pinctrl-0 = <&pinmux_spi0_pins>;
1352
Simon Glass0ae0cb72014-10-13 23:42:11 -06001353 spi.bin@0 {
1354 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001355 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001356 spi-max-frequency = <40000000>;
1357 sandbox,filename = "spi.bin";
1358 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001359 spi.bin@1 {
1360 reg = <1>;
1361 compatible = "spansion,m25p16", "jedec,spi-nor";
1362 spi-max-frequency = <50000000>;
1363 sandbox,filename = "spi.bin";
1364 spi-cpol;
1365 spi-cpha;
1366 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001367 };
1368
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001369 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001370 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001371 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001372 };
1373
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001374 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001375 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001376 reg = <0x20 5
1377 0x28 6
1378 0x30 7
1379 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001380 };
1381
Patrick Delaunaya442e612019-03-07 09:57:13 +01001382 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001383 compatible = "simple-mfd", "syscon";
1384 reg = <0x40 5
1385 0x48 6
1386 0x50 7
1387 0x58 8>;
1388 };
1389
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301390 syscon3: syscon@3 {
1391 compatible = "simple-mfd", "syscon";
1392 reg = <0x000100 0x10>;
1393
1394 muxcontroller0: a-mux-controller {
1395 compatible = "mmio-mux";
1396 #mux-control-cells = <1>;
1397
1398 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1399 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1400 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1401 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1402 u-boot,mux-autoprobe;
1403 };
1404 };
1405
1406 muxcontroller1: emul-mux-controller {
1407 compatible = "mux-emul";
1408 #mux-control-cells = <0>;
1409 u-boot,mux-autoprobe;
1410 idle-state = <0xabcd>;
1411 };
1412
Simon Glass93f44e82020-12-16 21:20:27 -07001413 testfdtm0 {
1414 compatible = "denx,u-boot-fdtm-test";
1415 };
1416
1417 testfdtm1: testfdtm1 {
1418 compatible = "denx,u-boot-fdtm-test";
1419 };
1420
1421 testfdtm2 {
1422 compatible = "denx,u-boot-fdtm-test";
1423 };
1424
Sean Anderson7616e362020-09-28 10:52:23 -04001425 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001426 compatible = "sandbox,timer";
1427 clock-frequency = <1000000>;
1428 };
1429
Sean Anderson7616e362020-09-28 10:52:23 -04001430 timer@1 {
1431 compatible = "sandbox,timer";
1432 sandbox,timebase-frequency-fallback;
1433 };
1434
Miquel Raynalb91ad162018-05-15 11:57:27 +02001435 tpm2 {
1436 compatible = "sandbox,tpm2";
Eddie James5999ea22023-10-24 10:43:51 -05001437 memory-region = <&event_log>;
Miquel Raynalb91ad162018-05-15 11:57:27 +02001438 };
1439
Simon Glass4fef6572023-02-21 06:24:51 -07001440 tpm {
1441 compatible = "google,sandbox-tpm";
1442 };
1443
Simon Glass171e9912015-05-22 15:42:15 -06001444 uart0: serial {
1445 compatible = "sandbox,serial";
Simon Glass8c103c32023-02-13 08:56:33 -07001446 bootph-all;
Dario Binacchi55322622021-04-11 09:39:50 +02001447 pinctrl-names = "default";
1448 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001449 };
1450
Simon Glasse00cb222015-03-25 12:23:05 -06001451 usb_0: usb@0 {
1452 compatible = "sandbox,usb";
1453 status = "disabled";
1454 hub {
1455 compatible = "sandbox,usb-hub";
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1458 flash-stick {
1459 reg = <0>;
1460 compatible = "sandbox,usb-flash";
1461 };
1462 };
1463 };
1464
1465 usb_1: usb@1 {
1466 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001467 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001468 hub {
1469 compatible = "usb-hub";
1470 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001471 #address-cells = <1>;
1472 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001473 hub-emul {
1474 compatible = "sandbox,usb-hub";
1475 #address-cells = <1>;
1476 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001477 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001478 reg = <0>;
1479 compatible = "sandbox,usb-flash";
1480 sandbox,filepath = "testflash.bin";
1481 };
1482
Simon Glass431cbd62015-11-08 23:48:01 -07001483 flash-stick@1 {
1484 reg = <1>;
1485 compatible = "sandbox,usb-flash";
1486 sandbox,filepath = "testflash1.bin";
1487 };
1488
1489 flash-stick@2 {
1490 reg = <2>;
1491 compatible = "sandbox,usb-flash";
1492 sandbox,filepath = "testflash2.bin";
1493 };
1494
Simon Glassbff1a712015-11-08 23:48:08 -07001495 keyb@3 {
1496 reg = <3>;
1497 compatible = "sandbox,usb-keyb";
1498 };
1499
Simon Glasse00cb222015-03-25 12:23:05 -06001500 };
Michael Wallec03b7612020-06-02 01:47:07 +02001501
1502 usbstor@1 {
1503 reg = <1>;
1504 };
1505 usbstor@3 {
1506 reg = <3>;
1507 };
Simon Glasse00cb222015-03-25 12:23:05 -06001508 };
1509 };
1510
1511 usb_2: usb@2 {
1512 compatible = "sandbox,usb";
1513 status = "disabled";
1514 };
1515
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001516 spmi: spmi@0 {
1517 compatible = "sandbox,spmi";
1518 #address-cells = <0x1>;
1519 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001520 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001521 pm8916@0 {
1522 compatible = "qcom,spmi-pmic";
1523 reg = <0x0 0x1>;
1524 #address-cells = <0x1>;
1525 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001526 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001527
1528 spmi_gpios: gpios@c000 {
1529 compatible = "qcom,pm8916-gpio";
1530 reg = <0xc000 0x400>;
1531 gpio-controller;
1532 gpio-count = <4>;
1533 #gpio-cells = <2>;
1534 gpio-bank-name="spmi";
1535 };
1536 };
1537 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001538
1539 wdt0: wdt@0 {
1540 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001541 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001542 };
Rob Clarkf2006802018-01-10 11:33:30 +01001543
Mario Six957983e2018-08-09 14:51:19 +02001544 axi: axi@0 {
1545 compatible = "sandbox,axi";
1546 #address-cells = <0x1>;
1547 #size-cells = <0x1>;
1548 store@0 {
1549 compatible = "sandbox,sandbox_store";
1550 reg = <0x0 0x400>;
1551 };
1552 };
1553
Rob Clarkf2006802018-01-10 11:33:30 +01001554 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001555 #address-cells = <1>;
1556 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001557 setting = "sunrise ohoka";
1558 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001559 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001560 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001561 chosen-test {
1562 compatible = "denx,u-boot-fdt-test";
1563 reg = <9 1>;
1564 };
1565 };
Mario Sixe8d52912018-03-12 14:53:33 +01001566
1567 translation-test@8000 {
1568 compatible = "simple-bus";
1569 reg = <0x8000 0x4000>;
1570
1571 #address-cells = <0x2>;
1572 #size-cells = <0x1>;
1573
1574 ranges = <0 0x0 0x8000 0x1000
1575 1 0x100 0x9000 0x1000
1576 2 0x200 0xA000 0x1000
1577 3 0x300 0xB000 0x1000
1578 >;
1579
Fabien Dessenne641067f2019-05-31 15:11:30 +02001580 dma-ranges = <0 0x000 0x10000000 0x1000
1581 1 0x100 0x20000000 0x1000
1582 >;
1583
Mario Sixe8d52912018-03-12 14:53:33 +01001584 dev@0,0 {
1585 compatible = "denx,u-boot-fdt-dummy";
1586 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001587 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001588 };
1589
1590 dev@1,100 {
1591 compatible = "denx,u-boot-fdt-dummy";
1592 reg = <1 0x100 0x1000>;
1593
1594 };
1595
1596 dev@2,200 {
1597 compatible = "denx,u-boot-fdt-dummy";
1598 reg = <2 0x200 0x1000>;
1599 };
1600
1601
1602 noxlatebus@3,300 {
1603 compatible = "simple-bus";
1604 reg = <3 0x300 0x1000>;
1605
1606 #address-cells = <0x1>;
1607 #size-cells = <0x0>;
1608
1609 dev@42 {
1610 compatible = "denx,u-boot-fdt-dummy";
1611 reg = <0x42>;
1612 };
1613 };
1614 };
Mario Six4eea5312018-09-27 09:19:31 +02001615
Dzmitry Sankouski298ffdd2023-01-22 18:21:23 +03001616 ofnode-foreach {
1617 compatible = "foreach";
1618
1619 first {
1620 prop1 = <1>;
1621 prop2 = <2>;
1622 };
1623
1624 second {
1625 prop1 = <1>;
1626 prop2 = <2>;
1627 };
1628 };
1629
Mario Six4eea5312018-09-27 09:19:31 +02001630 osd {
1631 compatible = "sandbox,sandbox_osd";
1632 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001633
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001634 sandbox_tee {
1635 compatible = "sandbox,tee";
1636 };
Bin Meng4f89d492018-10-15 02:21:26 -07001637
1638 sandbox_virtio1 {
1639 compatible = "sandbox,virtio1";
Simon Glass00fc8ca2023-01-17 10:47:51 -07001640 virtio-type = <4>; /* rng */
Bin Meng4f89d492018-10-15 02:21:26 -07001641 };
1642
1643 sandbox_virtio2 {
1644 compatible = "sandbox,virtio2";
1645 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001646
Simon Glass00fc8ca2023-01-17 10:47:51 -07001647 sandbox-virtio-blk {
1648 compatible = "sandbox,virtio1";
1649 virtio-type = <2>; /* block */
1650 };
1651
Etienne Carriere87d4f272020-09-09 18:44:05 +02001652 sandbox_scmi {
1653 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001654 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001655 resets = <&reset_scmi 3>;
1656 regul0-supply = <&regul0_scmi>;
1657 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001658 };
1659
Patrice Chotardf41a8242018-10-24 14:10:23 +02001660 pinctrl {
1661 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001662
Sean Anderson7f0f1802020-09-14 11:01:57 -04001663 pinctrl-names = "default", "alternate";
1664 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1665 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001666
Sean Anderson7f0f1802020-09-14 11:01:57 -04001667 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001668 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001669 pins = "P5";
1670 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001671 bias-pull-up;
1672 input-disable;
1673 };
1674 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001675 pins = "P6";
1676 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001677 output-high;
1678 drive-open-drain;
1679 };
1680 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001681 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001682 bias-pull-down;
1683 input-enable;
1684 };
1685 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001686 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001687 bias-disable;
1688 };
1689 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001690
1691 pinctrl_i2c: i2c {
1692 groups {
1693 groups = "I2C_UART";
1694 function = "I2C";
1695 };
1696
1697 pins {
1698 pins = "P0", "P1";
1699 drive-open-drain;
1700 };
1701 };
1702
1703 pinctrl_i2s: i2s {
1704 groups = "SPI_I2S";
1705 function = "I2S";
1706 };
1707
1708 pinctrl_spi: spi {
1709 groups = "SPI_I2S";
1710 function = "SPI";
1711
1712 cs {
1713 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1714 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1715 };
1716 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001717 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001718
Dario Binacchi55322622021-04-11 09:39:50 +02001719 pinctrl-single-no-width {
1720 compatible = "pinctrl-single";
1721 reg = <0x0000 0x238>;
1722 #pinctrl-cells = <1>;
1723 pinctrl-single,function-mask = <0x7f>;
1724 };
1725
1726 pinctrl-single-pins {
1727 compatible = "pinctrl-single";
1728 reg = <0x0000 0x238>;
1729 #pinctrl-cells = <1>;
1730 pinctrl-single,register-width = <32>;
1731 pinctrl-single,function-mask = <0x7f>;
1732
1733 pinmux_pwm_pins: pinmux_pwm_pins {
1734 pinctrl-single,pins = < 0x48 0x06 >;
1735 };
1736
1737 pinmux_spi0_pins: pinmux_spi0_pins {
1738 pinctrl-single,pins = <
1739 0x190 0x0c
1740 0x194 0x0c
1741 0x198 0x23
1742 0x19c 0x0c
1743 >;
1744 };
1745
1746 pinmux_uart0_pins: pinmux_uart0_pins {
1747 pinctrl-single,pins = <
1748 0x70 0x30
1749 0x74 0x00
1750 >;
1751 };
1752 };
1753
1754 pinctrl-single-bits {
1755 compatible = "pinctrl-single";
1756 reg = <0x0000 0x50>;
1757 #pinctrl-cells = <2>;
1758 pinctrl-single,bit-per-mux;
1759 pinctrl-single,register-width = <32>;
1760 pinctrl-single,function-mask = <0xf>;
1761
1762 pinmux_i2c0_pins: pinmux_i2c0_pins {
1763 pinctrl-single,bits = <
1764 0x10 0x00002200 0x0000ff00
1765 >;
1766 };
1767
1768 pinmux_lcd_pins: pinmux_lcd_pins {
1769 pinctrl-single,bits = <
1770 0x40 0x22222200 0xffffff00
1771 0x44 0x22222222 0xffffffff
1772 0x48 0x00000022 0x000000ff
1773 0x48 0x02000000 0x0f000000
1774 0x4c 0x02000022 0x0f0000ff
1775 >;
1776 };
1777 };
1778
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001779 hwspinlock@0 {
1780 compatible = "sandbox,hwspinlock";
1781 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001782
1783 dma: dma {
1784 compatible = "sandbox,dma";
1785 #dma-cells = <1>;
1786
1787 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1788 dma-names = "m2m", "tx0", "rx0";
1789 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001790
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001791 /*
1792 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1793 * end of the test. If parent mdio is removed first, clean-up of the
1794 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1795 * active at the end of the test. That it turn doesn't allow the mdio
1796 * class to be destroyed, triggering an error.
1797 */
1798 mdio-mux-test {
1799 compatible = "sandbox,mdio-mux";
1800 #address-cells = <1>;
1801 #size-cells = <0>;
1802 mdio-parent-bus = <&mdio>;
1803
1804 mdio-ch-test@0 {
1805 reg = <0>;
1806 };
1807 mdio-ch-test@1 {
1808 reg = <1>;
1809 };
1810 };
1811
1812 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001813 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001814 #address-cells = <1>;
1815 #size-cells = <0>;
1816
1817 ethphy1: ethernet-phy@1 {
1818 reg = <1>;
1819 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001820 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001821
1822 pm-bus-test {
1823 compatible = "simple-pm-bus";
1824 clocks = <&clk_sandbox 4>;
1825 power-domains = <&pwrdom 1>;
1826 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001827
1828 resetc2: syscon-reset {
1829 compatible = "syscon-reset";
1830 #reset-cells = <1>;
1831 regmap = <&syscon0>;
1832 offset = <1>;
1833 mask = <0x27FFFFFF>;
1834 assert-high = <0>;
1835 };
1836
1837 syscon-reset-test {
1838 compatible = "sandbox,misc_sandbox";
1839 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1840 reset-names = "valid", "no_mask", "out_of_range";
1841 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301842
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001843 sysinfo {
1844 compatible = "sandbox,sysinfo-sandbox";
1845 };
1846
Sean Anderson1cbfed82021-04-20 10:50:58 -04001847 sysinfo-gpio {
1848 compatible = "gpio-sysinfo";
1849 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1850 revisions = <19>, <5>;
1851 names = "rev_a", "foo";
1852 };
1853
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301854 some_regmapped-bus {
1855 #address-cells = <0x1>;
1856 #size-cells = <0x1>;
1857
1858 ranges = <0x0 0x0 0x10>;
1859 compatible = "simple-bus";
1860
1861 regmap-test_0 {
1862 reg = <0 0x10>;
1863 compatible = "sandbox,regmap_test";
1864 };
1865 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001866
1867 thermal {
1868 compatible = "sandbox,thermal";
1869 };
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301870
1871 fwu-mdata {
1872 compatible = "u-boot,fwu-mdata-gpt";
1873 fwu-mdata-store = <&mmc0>;
1874 };
Abdellatif El Khlificc89b7c2023-04-17 10:11:55 +01001875
1876 nvmxip-qspi1@08000000 {
1877 compatible = "nvmxip,qspi";
1878 reg = <0x08000000 0x00200000>;
1879 lba_shift = <9>;
1880 lba = <4096>;
1881 };
1882
1883 nvmxip-qspi2@08200000 {
1884 compatible = "nvmxip,qspi";
1885 reg = <0x08200000 0x00100000>;
1886 lba_shift = <9>;
1887 lba = <2048>;
1888 };
Svyatoslav Ryhel8b215e12023-04-25 10:57:21 +03001889
1890 extcon {
1891 compatible = "sandbox,extcon";
1892 };
Abdellatif El Khlifia09852d2023-08-04 14:33:41 +01001893
1894 arm-ffa-emul {
1895 compatible = "sandbox,arm-ffa-emul";
1896
1897 sandbox-arm-ffa {
1898 compatible = "sandbox,arm-ffa";
1899 };
1900 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001901};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001902
1903#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001904#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001905
1906#ifdef CONFIG_SANDBOX_VPL
1907#include "sandbox_vpl.dtsi"
1908#endif
Simon Glass82cafee2023-06-01 10:23:01 -06001909
1910#include "cedit.dtsi"