blob: 63fda15da76418a2266e3bd1a14516045856aca5 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010017
Simon Glass2e7d35d2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070023
Simon Glass00606d72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Simon Glassd08db022023-08-24 13:55:41 -060042 mmc4 = "/mmc4";
43 mmc5 = "/mmc5";
Bin Mengdee4d752018-08-03 01:14:41 -070044 pci0 = &pci0;
45 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070046 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020047 remoteproc0 = &rproc_1;
48 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060049 rtc0 = &rtc_0;
50 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060051 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020052 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070053 testbus3 = "/some-bus";
54 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070055 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070056 testfdt3 = "/b-test";
57 testfdt5 = "/some-bus/c-test@5";
58 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070059 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020060 fdt-dummy0 = "/translation-test@8000/dev@0,0";
61 fdt-dummy1 = "/translation-test@8000/dev@1,100";
62 fdt-dummy2 = "/translation-test@8000/dev@2,200";
63 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060064 usb0 = &usb_0;
65 usb1 = &usb_1;
66 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020067 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020068 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060069 };
70
Simon Glass8de98962022-10-20 18:23:15 -060071 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020072 };
73
Rasmus Villemoes8c728422021-04-21 11:06:55 +020074 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060075 testing-bool;
76 testing-int = <123>;
77 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020078 environment {
79 from_fdt = "yes";
80 fdt_env_path = "";
81 };
82 };
83
Simon Glassfb1451b2022-04-24 23:31:24 -060084 bootstd {
Simon Glass8c103c32023-02-13 08:56:33 -070085 bootph-verify;
Simon Glassfb1451b2022-04-24 23:31:24 -060086 compatible = "u-boot,boot-std";
87
88 filename-prefixes = "/", "/boot/";
89 bootdev-order = "mmc2", "mmc1";
90
Simon Glass79f66352023-05-10 16:34:46 -060091 extlinux {
92 compatible = "u-boot,extlinux";
Simon Glassfb1451b2022-04-24 23:31:24 -060093 };
94
95 efi {
96 compatible = "u-boot,distro-efi";
97 };
Simon Glassa56f6632022-10-20 18:23:14 -060098
Simon Glassd985f1d2023-01-06 08:52:41 -060099 theme {
100 font-size = <30>;
Simon Glass7230fdb2023-06-01 10:23:00 -0600101 menu-inset = <3>;
102 menuitem-gap-y = <1>;
Simon Glassd985f1d2023-01-06 08:52:41 -0600103 };
104
Simon Glass2045ca52023-08-14 16:40:30 -0600105 cedit-theme {
106 font-size = <30>;
107 menu-inset = <3>;
108 menuitem-gap-y = <1>;
109 };
110
Simon Glass77bec9e2022-10-20 18:23:20 -0600111 /*
112 * This is used for the VBE OS-request tests. A FAT filesystem
113 * created in a partition with the VBE information appearing
114 * before the parititon starts
115 */
Simon Glassa56f6632022-10-20 18:23:14 -0600116 firmware0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700117 bootph-verify;
Simon Glassa56f6632022-10-20 18:23:14 -0600118 compatible = "fwupd,vbe-simple";
119 storage = "mmc1";
120 skip-offset = <0x200>;
121 area-start = <0x400>;
122 area-size = <0x1000>;
123 state-offset = <0x400>;
124 state-size = <0x40>;
125 version-offset = <0x800>;
126 version-size = <0x100>;
127 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600128
129 /*
130 * This is used for the VBE VPL tests. The MMC device holds the
131 * binman image.bin file. The test progresses through each phase
132 * of U-Boot, loading each in turn from MMC.
133 *
134 * Note that the test enables this node (and mmc3) before
135 * running U-Boot
136 */
137 firmware1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700138 bootph-verify;
Simon Glass77bec9e2022-10-20 18:23:20 -0600139 status = "disabled";
140 compatible = "fwupd,vbe-simple";
141 storage = "mmc3";
Simon Glass74b75aa2023-04-02 14:01:24 +1200142 skip-offset = <0x800000>;
Simon Glass77bec9e2022-10-20 18:23:20 -0600143 area-start = <0>;
144 area-size = <0xe00000>;
145 state-offset = <0xdffc00>;
146 state-size = <0x40>;
147 version-offset = <0xdffe00>;
148 version-size = <0x100>;
149 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600150 };
151
Simon Glass82cafee2023-06-01 10:23:01 -0600152 cedit: cedit {
153 };
154
Andrew Scull0518e7a2022-05-30 10:00:12 +0000155 fuzzing-engine {
156 compatible = "sandbox,fuzzing-engine";
157 };
158
Nandor Hanf9db2f12021-06-10 16:56:44 +0300159 reboot-mode0 {
160 compatible = "reboot-mode-gpio";
161 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
162 u-boot,env-variable = "bootstatus";
163 mode-test = <0x01>;
164 mode-download = <0x03>;
165 };
166
Nandor Hanc74675b2021-06-10 16:56:45 +0300167 reboot_mode1: reboot-mode@14 {
168 compatible = "reboot-mode-rtc";
169 rtc = <&rtc_0>;
170 reg = <0x30 4>;
171 u-boot,env-variable = "bootstatus";
172 big-endian;
173 mode-test = <0x21969147>;
174 mode-download = <0x51939147>;
175 };
176
Simon Glassce6d99a2018-12-10 10:37:33 -0700177 audio: audio-codec {
178 compatible = "sandbox,audio-codec";
179 #sound-dai-cells = <1>;
180 };
181
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200182 buttons {
183 compatible = "gpio-keys";
184
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200185 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200186 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200187 label = "button1";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300188 linux,code = <BTN_1>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200189 };
190
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200191 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200192 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200193 label = "button2";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300194 linux,code = <BTN_2>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200195 };
196 };
197
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100198 buttons2 {
199 compatible = "adc-keys";
200 io-channels = <&adc 3>;
201 keyup-threshold-microvolt = <3000000>;
202
203 button-up {
204 label = "button3";
205 linux,code = <KEY_F3>;
206 press-threshold-microvolt = <1500000>;
207 };
208
209 button-down {
210 label = "button4";
211 linux,code = <KEY_F4>;
212 press-threshold-microvolt = <1000000>;
213 };
214
215 button-enter {
216 label = "button5";
217 linux,code = <KEY_F5>;
218 press-threshold-microvolt = <500000>;
219 };
220 };
221
Simon Glasse96fa6c2018-12-10 10:37:34 -0700222 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600223 reg = <0 0>;
224 compatible = "google,cros-ec-sandbox";
225
226 /*
227 * This describes the flash memory within the EC. Note
228 * that the STM32L flash erases to 0, not 0xff.
229 */
230 flash {
231 image-pos = <0x08000000>;
232 size = <0x20000>;
233 erase-value = <0>;
234
235 /* Information for sandbox */
236 ro {
237 image-pos = <0>;
238 size = <0xf000>;
239 };
240 wp-ro {
241 image-pos = <0xf000>;
242 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700243 used = <0x884>;
244 compress = "lz4";
245 uncomp-size = <0xcf8>;
246 hash {
247 algo = "sha256";
248 value = [00 01 02 03 04 05 06 07
249 08 09 0a 0b 0c 0d 0e 0f
250 10 11 12 13 14 15 16 17
251 18 19 1a 1b 1c 1d 1e 1f];
252 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600253 };
254 rw {
255 image-pos = <0x10000>;
256 size = <0x10000>;
257 };
258 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300259
260 cros_ec_pwm: cros-ec-pwm {
261 compatible = "google,cros-ec-pwm";
262 #pwm-cells = <1>;
263 };
264
Simon Glasse6c5c942018-10-01 12:22:08 -0600265 };
266
Yannick Fertré23f965a2019-10-07 15:29:05 +0200267 dsi_host: dsi_host {
268 compatible = "sandbox,dsi-host";
269 };
270
Simon Glass2e7d35d2014-02-26 15:59:21 -0700271 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600272 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700273 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600274 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700275 ping-add = <0>;
Simon Glass8c103c32023-02-13 08:56:33 -0700276 bootph-all;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100277 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
278 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700279 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100280 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
281 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
282 <&gpio_b 7 GPIO_IN 3 2 1>,
283 <&gpio_b 8 GPIO_OUT 3 2 1>,
284 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100285 test3-gpios =
286 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
287 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
288 <&gpio_c 2 GPIO_OUT>,
289 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
290 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200291 <&gpio_c 5 GPIO_IN>,
292 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
293 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530294 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
295 test5-gpios = <&gpio_a 19>;
296
Simon Glassfb933d02021-10-23 17:26:04 -0600297 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200298 int8-value = /bits/ 8 <0x12>;
299 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700300 int-value = <1234>;
301 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200302 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200303 int-array = <5678 9123 4567>;
Simon Glass06679002020-07-07 13:11:58 -0600304 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700305 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600306 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200307 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530308
309 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
310 <&muxcontroller0 2>, <&muxcontroller0 3>,
311 <&muxcontroller1>;
312 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
313 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100314 display-timings {
315 timing0: 240x320 {
316 clock-frequency = <6500000>;
317 hactive = <240>;
318 vactive = <320>;
319 hfront-porch = <6>;
320 hback-porch = <7>;
321 hsync-len = <1>;
322 vback-porch = <5>;
323 vfront-porch = <8>;
324 vsync-len = <2>;
325 hsync-active = <1>;
326 vsync-active = <0>;
327 de-active = <1>;
328 pixelclk-active = <1>;
329 interlaced;
330 doublescan;
331 doubleclk;
332 };
333 timing1: 480x800 {
334 clock-frequency = <9000000>;
335 hactive = <480>;
336 vactive = <800>;
337 hfront-porch = <10>;
338 hback-porch = <59>;
339 hsync-len = <12>;
340 vback-porch = <15>;
341 vfront-porch = <17>;
342 vsync-len = <16>;
343 hsync-active = <0>;
344 vsync-active = <1>;
345 de-active = <0>;
346 pixelclk-active = <0>;
347 };
348 timing2: 800x480 {
349 clock-frequency = <33500000>;
350 hactive = <800>;
351 vactive = <480>;
352 hback-porch = <89>;
353 hfront-porch = <164>;
354 vback-porch = <23>;
355 vfront-porch = <10>;
356 hsync-len = <11>;
357 vsync-len = <13>;
358 };
359 };
Raphael Gallais-Poucd880582023-05-11 16:36:52 +0200360 panel-timing {
Nikhil M Jain2f3d6a42023-01-31 15:35:15 +0530361 clock-frequency = <6500000>;
362 hactive = <240>;
363 vactive = <320>;
364 hfront-porch = <6>;
365 hback-porch = <7>;
366 hsync-len = <1>;
367 vback-porch = <5>;
368 vfront-porch = <8>;
369 vsync-len = <2>;
370 hsync-active = <1>;
371 vsync-active = <0>;
372 de-active = <1>;
373 pixelclk-active = <1>;
374 interlaced;
375 doublescan;
376 doubleclk;
377 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700378 };
379
380 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600381 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700382 compatible = "not,compatible";
383 };
384
385 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600386 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700387 };
388
Simon Glass5d9a88f2018-10-01 12:22:40 -0600389 backlight: backlight {
390 compatible = "pwm-backlight";
391 enable-gpios = <&gpio_a 1>;
392 power-supply = <&ldo_1>;
393 pwms = <&pwm 0 1000>;
394 default-brightness-level = <5>;
395 brightness-levels = <0 16 32 64 128 170 202 234 255>;
396 };
397
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200398 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200399 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200400 bind-test-child1 {
401 compatible = "sandbox,phy";
402 #phy-cells = <1>;
403 };
404
405 bind-test-child2 {
406 compatible = "simple-bus";
407 };
408 };
409
Simon Glass2e7d35d2014-02-26 15:59:21 -0700410 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600411 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700412 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600413 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700414 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530415
416 mux-controls = <&muxcontroller0 0>;
417 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700418 };
419
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200420 phy_provider0: gen_phy@0 {
421 compatible = "sandbox,phy";
422 #phy-cells = <1>;
423 };
424
425 phy_provider1: gen_phy@1 {
426 compatible = "sandbox,phy";
427 #phy-cells = <0>;
428 broken;
429 };
430
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200431 phy_provider2: gen_phy@2 {
432 compatible = "sandbox,phy";
433 #phy-cells = <0>;
434 };
435
Jonas Karlman14639bf2023-08-31 22:16:35 +0000436 phy_provider3: gen_phy@3 {
437 compatible = "sandbox,phy";
438 #phy-cells = <2>;
439 };
440
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200441 gen_phy_user: gen_phy_user {
442 compatible = "simple-bus";
443 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
444 phy-names = "phy1", "phy2", "phy3";
445 };
446
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200447 gen_phy_user1: gen_phy_user1 {
448 compatible = "simple-bus";
449 phys = <&phy_provider0 0>, <&phy_provider2>;
450 phy-names = "phy1", "phy2";
451 };
452
Jonas Karlman14639bf2023-08-31 22:16:35 +0000453 gen_phy_user2: gen_phy_user2 {
454 compatible = "simple-bus";
455 phys = <&phy_provider3 0 0>;
456 phy-names = "phy1";
457 };
458
Simon Glass2e7d35d2014-02-26 15:59:21 -0700459 some-bus {
460 #address-cells = <1>;
461 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600462 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600463 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600464 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700465 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600466 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700467 compatible = "denx,u-boot-fdt-test";
468 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600469 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700470 ping-add = <5>;
471 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600472 c-test@0 {
473 compatible = "denx,u-boot-fdt-test";
474 reg = <0>;
475 ping-expect = <6>;
476 ping-add = <6>;
477 };
478 c-test@1 {
479 compatible = "denx,u-boot-fdt-test";
480 reg = <1>;
481 ping-expect = <7>;
482 ping-add = <7>;
483 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700484 };
485
486 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600487 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600488 ping-expect = <6>;
489 ping-add = <6>;
490 compatible = "google,another-fdt-test";
491 };
492
493 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600494 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600495 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700496 ping-add = <6>;
497 compatible = "google,another-fdt-test";
498 };
499
Simon Glass9cc36a22015-01-25 08:27:05 -0700500 f-test {
501 compatible = "denx,u-boot-fdt-test";
502 };
503
504 g-test {
505 compatible = "denx,u-boot-fdt-test";
506 };
507
Bin Meng2786cd72018-10-10 22:07:01 -0700508 h-test {
509 compatible = "denx,u-boot-fdt-test1";
510 };
511
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200512 i-test {
513 compatible = "mediatek,u-boot-fdt-test";
514 #address-cells = <1>;
515 #size-cells = <0>;
516
517 subnode@0 {
518 reg = <0>;
519 };
520
521 subnode@1 {
522 reg = <1>;
523 };
524
525 subnode@2 {
526 reg = <2>;
527 };
528 };
529
Simon Glassdc12ebb2019-12-29 21:19:25 -0700530 devres-test {
531 compatible = "denx,u-boot-devres-test";
532 };
533
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530534 another-test {
535 reg = <0 2>;
536 compatible = "denx,u-boot-fdt-test";
537 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
538 test5-gpios = <&gpio_a 19>;
539 };
540
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100541 mmio-bus@0 {
542 #address-cells = <1>;
543 #size-cells = <1>;
544 compatible = "denx,u-boot-test-bus";
545 dma-ranges = <0x10000000 0x00000000 0x00040000>;
546
547 subnode@0 {
548 compatible = "denx,u-boot-fdt-test";
549 };
550 };
551
552 mmio-bus@1 {
553 #address-cells = <1>;
554 #size-cells = <1>;
555 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100556
557 subnode@0 {
558 compatible = "denx,u-boot-fdt-test";
559 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100560 };
561
Simon Glass0f7b1112020-07-07 13:12:06 -0600562 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600563 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600564 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600565 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600566 child {
567 compatible = "denx,u-boot-acpi-test";
568 };
Simon Glassf50cc952020-04-08 16:57:34 -0600569 };
570
Simon Glass0f7b1112020-07-07 13:12:06 -0600571 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600572 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600573 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600574 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600575 };
576
Patrice Chotardee87a092017-09-04 14:55:57 +0200577 clocks {
578 clk_fixed: clk-fixed {
579 compatible = "fixed-clock";
580 #clock-cells = <0>;
581 clock-frequency = <1234>;
582 };
Anup Patelb630d572019-02-25 08:14:55 +0000583
584 clk_fixed_factor: clk-fixed-factor {
585 compatible = "fixed-factor-clock";
586 #clock-cells = <0>;
587 clock-div = <3>;
588 clock-mult = <2>;
589 clocks = <&clk_fixed>;
590 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200591
592 osc {
593 compatible = "fixed-clock";
594 #clock-cells = <0>;
595 clock-frequency = <20000000>;
596 };
Stephen Warren135aa952016-06-17 09:44:00 -0600597 };
598
599 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600600 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600601 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200602 assigned-clocks = <&clk_sandbox 3>;
603 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600604 };
605
606 clk-test {
607 compatible = "sandbox,clk-test";
608 clocks = <&clk_fixed>,
609 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200610 <&clk_sandbox 0>,
611 <&clk_sandbox 3>,
612 <&clk_sandbox 2>;
613 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600614 };
615
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200616 ccf: clk-ccf {
617 compatible = "sandbox,clk-ccf";
618 };
619
Simon Glass42b7f422021-12-04 08:56:31 -0700620 efi-media {
621 compatible = "sandbox,efi-media";
622 };
623
Simon Glass171e9912015-05-22 15:42:15 -0600624 eth@10002000 {
625 compatible = "sandbox,eth";
626 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600627 };
628
629 eth_5: eth@10003000 {
630 compatible = "sandbox,eth";
631 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400632 nvmem-cells = <&eth5_addr>;
633 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600634 };
635
Bin Meng71d79712015-08-27 22:25:53 -0700636 eth_3: sbe5 {
637 compatible = "sandbox,eth";
638 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400639 nvmem-cells = <&eth3_addr>;
640 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700641 };
642
Simon Glass171e9912015-05-22 15:42:15 -0600643 eth@10004000 {
644 compatible = "sandbox,eth";
645 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600646 };
647
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200648 phy_eth0: phy-test-eth {
649 compatible = "sandbox,eth";
650 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400651 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200652 phy-handle = <&ethphy1>;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200653 phy-mode = "2500base-x";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +0200654 };
655
Claudiu Manoilff98da02021-03-14 20:14:57 +0800656 dsa_eth0: dsa-test-eth {
657 compatible = "sandbox,eth";
658 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400659 nvmem-cells = <&eth4_addr>;
660 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800661 };
662
663 dsa-test {
664 compatible = "sandbox,dsa";
665
666 ports {
667 #address-cells = <1>;
668 #size-cells = <0>;
669 swp_0: port@0 {
670 reg = <0>;
671 label = "lan0";
672 phy-mode = "rgmii-rxid";
673
674 fixed-link {
675 speed = <100>;
676 full-duplex;
677 };
678 };
679
680 swp_1: port@1 {
681 reg = <1>;
682 label = "lan1";
683 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800684 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800685 };
686
687 port@2 {
688 reg = <2>;
689 ethernet = <&dsa_eth0>;
690
691 fixed-link {
692 speed = <1000>;
693 full-duplex;
694 };
695 };
696 };
697 };
698
Rajan Vaja31b82172018-09-19 03:43:46 -0700699 firmware {
700 sandbox_firmware: sandbox-firmware {
701 compatible = "sandbox,firmware";
702 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200703
Etienne Carriere41d62e22022-02-21 09:22:39 +0100704 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200705 compatible = "sandbox,scmi-agent";
706 #address-cells = <1>;
707 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200708
Etienne Carriere41d62e22022-02-21 09:22:39 +0100709 protocol@10 {
710 reg = <0x10>;
711 };
712
713 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200714 reg = <0x14>;
715 #clock-cells = <1>;
716 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200717
Etienne Carriere41d62e22022-02-21 09:22:39 +0100718 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200719 reg = <0x16>;
720 #reset-cells = <1>;
721 };
Etienne Carriere01242182021-03-08 22:38:07 +0100722
723 protocol@17 {
724 reg = <0x17>;
725
726 regulators {
727 #address-cells = <1>;
728 #size-cells = <0>;
729
Etienne Carriere41d62e22022-02-21 09:22:39 +0100730 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100731 reg = <0>;
732 regulator-name = "sandbox-voltd0";
733 regulator-min-microvolt = <1100000>;
734 regulator-max-microvolt = <3300000>;
735 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100736 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100737 reg = <0x1>;
738 regulator-name = "sandbox-voltd1";
739 regulator-min-microvolt = <1800000>;
740 };
741 };
742 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200743 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700744 };
745
Alexander Dahl1323d082022-09-30 14:04:30 +0200746 fpga {
747 compatible = "sandbox,fpga";
748 };
749
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100750 pinctrl-gpio {
751 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700752
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100753 gpio_a: base-gpios {
754 compatible = "sandbox,gpio";
755 gpio-controller;
756 #gpio-cells = <1>;
757 gpio-bank-name = "a";
758 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200759 hog_input_active_low {
760 gpio-hog;
761 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200762 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200763 };
764 hog_input_active_high {
765 gpio-hog;
766 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200767 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200768 };
769 hog_output_low {
770 gpio-hog;
771 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200772 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200773 };
774 hog_output_high {
775 gpio-hog;
776 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200777 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200778 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100779 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600780
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100781 gpio_b: extra-gpios {
782 compatible = "sandbox,gpio";
783 gpio-controller;
784 #gpio-cells = <5>;
785 gpio-bank-name = "b";
786 sandbox,gpio-count = <10>;
787 };
788
789 gpio_c: pinmux-gpios {
790 compatible = "sandbox,gpio";
791 gpio-controller;
792 #gpio-cells = <2>;
793 gpio-bank-name = "c";
794 sandbox,gpio-count = <10>;
795 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100796 };
797
Simon Glassecc2ed52014-12-10 08:55:55 -0700798 i2c@0 {
799 #address-cells = <1>;
800 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600801 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700802 compatible = "sandbox,i2c";
803 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200804 pinctrl-names = "default";
805 pinctrl-0 = <&pinmux_i2c0_pins>;
806
Simon Glassecc2ed52014-12-10 08:55:55 -0700807 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400808 #address-cells = <1>;
809 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700810 reg = <0x2c>;
811 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700812 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200813 partitions {
814 compatible = "fixed-partitions";
815 #address-cells = <1>;
816 #size-cells = <1>;
817 bootcount_i2c: bootcount@10 {
818 reg = <10 2>;
819 };
820 };
Sean Anderson472caa62022-05-05 13:11:42 -0400821
822 eth3_addr: mac-address@24 {
823 reg = <24 6>;
824 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700825 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200826
Simon Glass52d3bc52015-05-22 15:42:17 -0600827 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400828 #address-cells = <1>;
829 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600830 reg = <0x43>;
831 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700832 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400833
834 eth4_addr: mac-address@40 {
835 reg = <0x40 6>;
836 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600837 };
838
839 rtc_1: rtc@61 {
840 reg = <0x61>;
841 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700842 sandbox,emul = <&emul1>;
843 };
844
845 i2c_emul: emul {
846 reg = <0xff>;
847 compatible = "sandbox,i2c-emul-parent";
848 emul_eeprom: emul-eeprom {
849 compatible = "sandbox,i2c-eeprom";
850 sandbox,filename = "i2c.bin";
851 sandbox,size = <256>;
852 };
853 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700854 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700855 };
856 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700857 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600858 };
859 };
860
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200861 sandbox_pmic: sandbox_pmic {
862 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700863 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200864 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200865
866 mc34708: pmic@41 {
867 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700868 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200869 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700870 };
871
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100872 bootcount@0 {
873 compatible = "u-boot,bootcount-rtc";
874 rtc = <&rtc_1>;
875 offset = <0x13>;
876 };
877
Michal Simekf692b472020-05-28 11:48:55 +0200878 bootcount {
879 compatible = "u-boot,bootcount-i2c-eeprom";
880 i2c-eeprom = <&bootcount_i2c>;
881 };
882
Nandor Hanc50b21b2021-06-10 15:40:38 +0300883 bootcount_4@0 {
884 compatible = "u-boot,bootcount-syscon";
885 syscon = <&syscon0>;
886 reg = <0x0 0x04>, <0x0 0x04>;
887 reg-names = "syscon_reg", "offset";
888 };
889
890 bootcount_2@0 {
891 compatible = "u-boot,bootcount-syscon";
892 syscon = <&syscon0>;
893 reg = <0x0 0x04>, <0x0 0x02> ;
894 reg-names = "syscon_reg", "offset";
895 };
896
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100897 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100898 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100899 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100900 vdd-supply = <&buck2>;
901 vss-microvolts = <0>;
902 };
903
Mark Kettenisfb574622021-10-23 16:58:02 +0200904 iommu: iommu@0 {
905 compatible = "sandbox,iommu";
906 #iommu-cells = <0>;
907 };
908
Simon Glass02554352020-02-06 09:55:00 -0700909 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700910 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700911 interrupt-controller;
912 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700913 };
914
Simon Glass3c97c4f2016-01-18 19:52:26 -0700915 lcd {
Simon Glass8c103c32023-02-13 08:56:33 -0700916 bootph-all;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700917 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200918 pinctrl-names = "default";
919 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700920 xres = <1366>;
921 yres = <768>;
922 };
923
Simon Glass3c43fba2015-07-06 12:54:34 -0600924 leds {
925 compatible = "gpio-leds";
926
927 iracibble {
928 gpios = <&gpio_a 1 0>;
929 label = "sandbox:red";
930 };
931
932 martinet {
933 gpios = <&gpio_a 2 0>;
934 label = "sandbox:green";
935 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200936
937 default_on {
938 gpios = <&gpio_a 5 0>;
939 label = "sandbox:default_on";
940 default-state = "on";
941 };
942
943 default_off {
944 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400945 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200946 default-state = "off";
947 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600948 };
949
Paul Doelle1fc45d62022-07-04 09:00:25 +0000950 wdt-gpio-toggle {
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200951 gpios = <&gpio_a 7 0>;
952 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200953 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000954 hw_algo = "toggle";
955 always-running;
956 };
957
958 wdt-gpio-level {
959 gpios = <&gpio_a 7 0>;
960 compatible = "linux,wdt-gpio";
961 hw_margin_ms = <100>;
962 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200963 always-running;
964 };
965
Stephen Warren8961b522016-05-16 17:41:37 -0600966 mbox: mbox {
967 compatible = "sandbox,mbox";
968 #mbox-cells = <1>;
969 };
970
971 mbox-test {
972 compatible = "sandbox,mbox-test";
973 mboxes = <&mbox 100>, <&mbox 1>;
974 mbox-names = "other", "test";
975 };
976
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900977 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200978 #address-cells = <1>;
979 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -0400980 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200981 cpu1: cpu@1 {
982 device_type = "cpu";
983 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -0400984 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900985 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700986 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900987 };
Mario Sixfa44b532018-08-06 10:23:44 +0200988
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200989 cpu2: cpu@2 {
990 device_type = "cpu";
991 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900992 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -0700993 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900994 };
Mario Sixfa44b532018-08-06 10:23:44 +0200995
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +0200996 cpu3: cpu@3 {
997 device_type = "cpu";
998 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +0900999 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001000 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001001 };
Mario Sixfa44b532018-08-06 10:23:44 +02001002 };
1003
Dave Gerlach21e3c212020-07-15 23:39:58 -05001004 chipid: chipid {
1005 compatible = "sandbox,soc";
1006 };
1007
Simon Glasse96fa6c2018-12-10 10:37:34 -07001008 i2s: i2s {
1009 compatible = "sandbox,i2s";
1010 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -07001011 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -07001012 };
1013
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +02001014 nop-test_0 {
1015 compatible = "sandbox,nop_sandbox1";
1016 nop-test_1 {
1017 compatible = "sandbox,nop_sandbox2";
1018 bind = "True";
1019 };
1020 nop-test_2 {
1021 compatible = "sandbox,nop_sandbox2";
1022 bind = "False";
1023 };
1024 };
1025
Roger Quadros2c120372022-10-20 16:30:46 +03001026 memory-controller {
1027 compatible = "sandbox,memory";
1028 };
1029
Mario Six004e67c2018-07-31 14:24:14 +02001030 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -04001031 #address-cells = <1>;
1032 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +02001033 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -04001034
1035 eth5_addr: mac-address@10 {
1036 reg = <0x10 6>;
1037 };
Mario Six004e67c2018-07-31 14:24:14 +02001038 };
1039
Simon Glasse48eeb92017-04-23 20:02:07 -06001040 mmc2 {
1041 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -06001042 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -06001043 };
1044
Simon Glassfb1451b2022-04-24 23:31:24 -06001045 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001046 mmc1 {
1047 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001048 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001049 };
1050
Simon Glassfb1451b2022-04-24 23:31:24 -06001051 /* This is used for the fastboot tests */
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301052 mmc0: mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001053 compatible = "sandbox,mmc";
1054 };
1055
Simon Glass77bec9e2022-10-20 18:23:20 -06001056 /* This is used for VBE VPL tests */
1057 mmc3 {
1058 status = "disabled";
1059 compatible = "sandbox,mmc";
1060 filename = "image.bin";
1061 non-removable;
1062 };
1063
Simon Glassd985f1d2023-01-06 08:52:41 -06001064 /* This is used for bootstd bootmenu tests */
1065 mmc4 {
1066 status = "disabled";
1067 compatible = "sandbox,mmc";
1068 filename = "mmc4.img";
1069 };
1070
Simon Glassd08db022023-08-24 13:55:41 -06001071 /* This is used for ChromiumOS tests */
1072 mmc5 {
1073 status = "disabled";
1074 compatible = "sandbox,mmc";
1075 filename = "mmc5.img";
1076 };
1077
Simon Glassb45c8332019-02-16 20:24:50 -07001078 pch {
1079 compatible = "sandbox,pch";
1080 };
1081
Tom Rini42c64d12020-02-11 12:41:23 -05001082 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001083 compatible = "sandbox,pci";
1084 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001085 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001086 #address-cells = <3>;
1087 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001088 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001089 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis08386da2023-01-21 20:27:57 +01001090 iommu-map = <0x0010 &iommu 0 1>;
1091 iommu-map-mask = <0xfffffff8>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001092 pci@0,0 {
1093 compatible = "pci-generic";
1094 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001095 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001096 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001097 pci@1,0 {
1098 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001099 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1100 reg = <0x02000814 0 0 0 0
1101 0x01000810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001102 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001103 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001104 p2sb-pci@2,0 {
1105 compatible = "sandbox,p2sb";
1106 reg = <0x02001010 0 0 0 0>;
1107 sandbox,emul = <&p2sb_emul>;
1108
1109 adder {
1110 intel,p2sb-port-id = <3>;
1111 compatible = "sandbox,adder";
1112 };
1113 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001114 pci@1e,0 {
1115 compatible = "sandbox,pmc";
1116 reg = <0xf000 0 0 0 0>;
1117 sandbox,emul = <&pmc_emul1e>;
1118 acpi-base = <0x400>;
1119 gpe0-dwx-mask = <0xf>;
1120 gpe0-dwx-shift-base = <4>;
1121 gpe0-dw = <6 7 9>;
1122 gpe0-sts = <0x20>;
1123 gpe0-en = <0x30>;
1124 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001125 pci@1f,0 {
1126 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001127 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1128 reg = <0x0100f810 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001129 sandbox,emul = <&swap_case_emul0_1f>;
1130 };
1131 };
1132
1133 pci-emul0 {
1134 compatible = "sandbox,pci-emul-parent";
1135 swap_case_emul0_0: emul0@0,0 {
1136 compatible = "sandbox,swap-case";
1137 };
1138 swap_case_emul0_1: emul0@1,0 {
1139 compatible = "sandbox,swap-case";
1140 use-ea;
1141 };
1142 swap_case_emul0_1f: emul0@1f,0 {
1143 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001144 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001145 p2sb_emul: emul@2,0 {
1146 compatible = "sandbox,p2sb-emul";
1147 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001148 pmc_emul1e: emul@1e,0 {
1149 compatible = "sandbox,pmc-emul";
1150 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001151 };
1152
Tom Rini42c64d12020-02-11 12:41:23 -05001153 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001154 compatible = "sandbox,pci";
1155 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001156 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001157 #address-cells = <3>;
1158 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001159 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001160 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001161 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001162 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001163 0x0c 0x00 0x1234 0x5678
1164 0x10 0x00 0x1234 0x5678>;
1165 pci@10,0 {
1166 reg = <0x8000 0 0 0 0>;
1167 };
Bin Mengdee4d752018-08-03 01:14:41 -07001168 };
1169
Tom Rini42c64d12020-02-11 12:41:23 -05001170 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001171 compatible = "sandbox,pci";
1172 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001173 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001174 #address-cells = <3>;
1175 #size-cells = <2>;
1176 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1177 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1178 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1179 pci@1f,0 {
1180 compatible = "pci-generic";
1181 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001182 sandbox,emul = <&swap_case_emul2_1f>;
1183 };
1184 };
1185
1186 pci-emul2 {
1187 compatible = "sandbox,pci-emul-parent";
1188 swap_case_emul2_1f: emul2@1f,0 {
1189 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001190 };
1191 };
1192
Ramon Friedbb413332019-04-27 11:15:23 +03001193 pci_ep: pci_ep {
1194 compatible = "sandbox,pci_ep";
1195 };
1196
Simon Glass98561572017-04-23 20:10:44 -06001197 probing {
1198 compatible = "simple-bus";
1199 test1 {
1200 compatible = "denx,u-boot-probe-test";
1201 };
1202
1203 test2 {
1204 compatible = "denx,u-boot-probe-test";
1205 };
1206
1207 test3 {
1208 compatible = "denx,u-boot-probe-test";
1209 };
1210
1211 test4 {
1212 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001213 first-syscon = <&syscon0>;
1214 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001215 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001216 };
1217 };
1218
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001219 pwrdom: power-domain {
1220 compatible = "sandbox,power-domain";
1221 #power-domain-cells = <1>;
1222 };
1223
1224 power-domain-test {
1225 compatible = "sandbox,power-domain-test";
1226 power-domains = <&pwrdom 2>;
1227 };
1228
Simon Glass5d9a88f2018-10-01 12:22:40 -06001229 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001230 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001231 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001232 pinctrl-names = "default";
1233 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001234 };
1235
1236 pwm2 {
1237 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001238 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001239 };
1240
Simon Glass64ce0ca2015-07-06 12:54:31 -06001241 ram {
1242 compatible = "sandbox,ram";
1243 };
1244
Simon Glass5010d982015-07-06 12:54:29 -06001245 reset@0 {
1246 compatible = "sandbox,warm-reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001247 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001248 };
1249
1250 reset@1 {
1251 compatible = "sandbox,reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001252 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001253 };
1254
Stephen Warren4581b712016-06-17 09:43:59 -06001255 resetc: reset-ctl {
1256 compatible = "sandbox,reset-ctl";
1257 #reset-cells = <1>;
1258 };
1259
1260 reset-ctl-test {
1261 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001262 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1263 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001264 };
1265
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301266 rng {
1267 compatible = "sandbox,sandbox-rng";
1268 };
1269
Nishanth Menon52159402015-09-17 15:42:41 -05001270 rproc_1: rproc@1 {
1271 compatible = "sandbox,test-processor";
1272 remoteproc-name = "remoteproc-test-dev1";
1273 };
1274
1275 rproc_2: rproc@2 {
1276 compatible = "sandbox,test-processor";
1277 internal-memory-mapped;
1278 remoteproc-name = "remoteproc-test-dev2";
1279 };
1280
Simon Glass5d9a88f2018-10-01 12:22:40 -06001281 panel {
1282 compatible = "simple-panel";
1283 backlight = <&backlight 0 100>;
1284 };
1285
Simon Glass22c80d52022-09-21 16:21:47 +02001286 scsi {
1287 compatible = "sandbox,scsi";
1288 sandbox,filepath = "scsi.img";
1289 };
1290
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001291 smem@0 {
1292 compatible = "sandbox,smem";
1293 };
1294
Simon Glassd4901892018-12-10 10:37:36 -07001295 sound {
1296 compatible = "sandbox,sound";
1297 cpu {
1298 sound-dai = <&i2s 0>;
1299 };
1300
1301 codec {
1302 sound-dai = <&audio 0>;
1303 };
1304 };
1305
Simon Glass0ae0cb72014-10-13 23:42:11 -06001306 spi@0 {
1307 #address-cells = <1>;
1308 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001309 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001310 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001311 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001312 pinctrl-names = "default";
1313 pinctrl-0 = <&pinmux_spi0_pins>;
1314
Simon Glass0ae0cb72014-10-13 23:42:11 -06001315 spi.bin@0 {
1316 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001317 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001318 spi-max-frequency = <40000000>;
1319 sandbox,filename = "spi.bin";
1320 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001321 spi.bin@1 {
1322 reg = <1>;
1323 compatible = "spansion,m25p16", "jedec,spi-nor";
1324 spi-max-frequency = <50000000>;
1325 sandbox,filename = "spi.bin";
1326 spi-cpol;
1327 spi-cpha;
1328 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001329 };
1330
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001331 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001332 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001333 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001334 };
1335
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001336 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001337 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001338 reg = <0x20 5
1339 0x28 6
1340 0x30 7
1341 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001342 };
1343
Patrick Delaunaya442e612019-03-07 09:57:13 +01001344 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001345 compatible = "simple-mfd", "syscon";
1346 reg = <0x40 5
1347 0x48 6
1348 0x50 7
1349 0x58 8>;
1350 };
1351
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301352 syscon3: syscon@3 {
1353 compatible = "simple-mfd", "syscon";
1354 reg = <0x000100 0x10>;
1355
1356 muxcontroller0: a-mux-controller {
1357 compatible = "mmio-mux";
1358 #mux-control-cells = <1>;
1359
1360 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1361 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1362 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1363 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1364 u-boot,mux-autoprobe;
1365 };
1366 };
1367
1368 muxcontroller1: emul-mux-controller {
1369 compatible = "mux-emul";
1370 #mux-control-cells = <0>;
1371 u-boot,mux-autoprobe;
1372 idle-state = <0xabcd>;
1373 };
1374
Simon Glass93f44e82020-12-16 21:20:27 -07001375 testfdtm0 {
1376 compatible = "denx,u-boot-fdtm-test";
1377 };
1378
1379 testfdtm1: testfdtm1 {
1380 compatible = "denx,u-boot-fdtm-test";
1381 };
1382
1383 testfdtm2 {
1384 compatible = "denx,u-boot-fdtm-test";
1385 };
1386
Sean Anderson7616e362020-09-28 10:52:23 -04001387 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001388 compatible = "sandbox,timer";
1389 clock-frequency = <1000000>;
1390 };
1391
Sean Anderson7616e362020-09-28 10:52:23 -04001392 timer@1 {
1393 compatible = "sandbox,timer";
1394 sandbox,timebase-frequency-fallback;
1395 };
1396
Miquel Raynalb91ad162018-05-15 11:57:27 +02001397 tpm2 {
1398 compatible = "sandbox,tpm2";
1399 };
1400
Simon Glass4fef6572023-02-21 06:24:51 -07001401 tpm {
1402 compatible = "google,sandbox-tpm";
1403 };
1404
Simon Glass171e9912015-05-22 15:42:15 -06001405 uart0: serial {
1406 compatible = "sandbox,serial";
Simon Glass8c103c32023-02-13 08:56:33 -07001407 bootph-all;
Dario Binacchi55322622021-04-11 09:39:50 +02001408 pinctrl-names = "default";
1409 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001410 };
1411
Simon Glasse00cb222015-03-25 12:23:05 -06001412 usb_0: usb@0 {
1413 compatible = "sandbox,usb";
1414 status = "disabled";
1415 hub {
1416 compatible = "sandbox,usb-hub";
1417 #address-cells = <1>;
1418 #size-cells = <0>;
1419 flash-stick {
1420 reg = <0>;
1421 compatible = "sandbox,usb-flash";
1422 };
1423 };
1424 };
1425
1426 usb_1: usb@1 {
1427 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001428 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001429 hub {
1430 compatible = "usb-hub";
1431 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001432 #address-cells = <1>;
1433 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001434 hub-emul {
1435 compatible = "sandbox,usb-hub";
1436 #address-cells = <1>;
1437 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001438 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001439 reg = <0>;
1440 compatible = "sandbox,usb-flash";
1441 sandbox,filepath = "testflash.bin";
1442 };
1443
Simon Glass431cbd62015-11-08 23:48:01 -07001444 flash-stick@1 {
1445 reg = <1>;
1446 compatible = "sandbox,usb-flash";
1447 sandbox,filepath = "testflash1.bin";
1448 };
1449
1450 flash-stick@2 {
1451 reg = <2>;
1452 compatible = "sandbox,usb-flash";
1453 sandbox,filepath = "testflash2.bin";
1454 };
1455
Simon Glassbff1a712015-11-08 23:48:08 -07001456 keyb@3 {
1457 reg = <3>;
1458 compatible = "sandbox,usb-keyb";
1459 };
1460
Simon Glasse00cb222015-03-25 12:23:05 -06001461 };
Michael Wallec03b7612020-06-02 01:47:07 +02001462
1463 usbstor@1 {
1464 reg = <1>;
1465 };
1466 usbstor@3 {
1467 reg = <3>;
1468 };
Simon Glasse00cb222015-03-25 12:23:05 -06001469 };
1470 };
1471
1472 usb_2: usb@2 {
1473 compatible = "sandbox,usb";
1474 status = "disabled";
1475 };
1476
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001477 spmi: spmi@0 {
1478 compatible = "sandbox,spmi";
1479 #address-cells = <0x1>;
1480 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001481 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001482 pm8916@0 {
1483 compatible = "qcom,spmi-pmic";
1484 reg = <0x0 0x1>;
1485 #address-cells = <0x1>;
1486 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001487 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001488
1489 spmi_gpios: gpios@c000 {
1490 compatible = "qcom,pm8916-gpio";
1491 reg = <0xc000 0x400>;
1492 gpio-controller;
1493 gpio-count = <4>;
1494 #gpio-cells = <2>;
1495 gpio-bank-name="spmi";
1496 };
1497 };
1498 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001499
1500 wdt0: wdt@0 {
1501 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001502 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001503 };
Rob Clarkf2006802018-01-10 11:33:30 +01001504
Mario Six957983e2018-08-09 14:51:19 +02001505 axi: axi@0 {
1506 compatible = "sandbox,axi";
1507 #address-cells = <0x1>;
1508 #size-cells = <0x1>;
1509 store@0 {
1510 compatible = "sandbox,sandbox_store";
1511 reg = <0x0 0x400>;
1512 };
1513 };
1514
Rob Clarkf2006802018-01-10 11:33:30 +01001515 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001516 #address-cells = <1>;
1517 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001518 setting = "sunrise ohoka";
1519 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001520 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001521 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarkf2006802018-01-10 11:33:30 +01001522 chosen-test {
1523 compatible = "denx,u-boot-fdt-test";
1524 reg = <9 1>;
1525 };
1526 };
Mario Sixe8d52912018-03-12 14:53:33 +01001527
1528 translation-test@8000 {
1529 compatible = "simple-bus";
1530 reg = <0x8000 0x4000>;
1531
1532 #address-cells = <0x2>;
1533 #size-cells = <0x1>;
1534
1535 ranges = <0 0x0 0x8000 0x1000
1536 1 0x100 0x9000 0x1000
1537 2 0x200 0xA000 0x1000
1538 3 0x300 0xB000 0x1000
1539 >;
1540
Fabien Dessenne641067f2019-05-31 15:11:30 +02001541 dma-ranges = <0 0x000 0x10000000 0x1000
1542 1 0x100 0x20000000 0x1000
1543 >;
1544
Mario Sixe8d52912018-03-12 14:53:33 +01001545 dev@0,0 {
1546 compatible = "denx,u-boot-fdt-dummy";
1547 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojas79598822018-12-03 19:37:09 +01001548 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001549 };
1550
1551 dev@1,100 {
1552 compatible = "denx,u-boot-fdt-dummy";
1553 reg = <1 0x100 0x1000>;
1554
1555 };
1556
1557 dev@2,200 {
1558 compatible = "denx,u-boot-fdt-dummy";
1559 reg = <2 0x200 0x1000>;
1560 };
1561
1562
1563 noxlatebus@3,300 {
1564 compatible = "simple-bus";
1565 reg = <3 0x300 0x1000>;
1566
1567 #address-cells = <0x1>;
1568 #size-cells = <0x0>;
1569
1570 dev@42 {
1571 compatible = "denx,u-boot-fdt-dummy";
1572 reg = <0x42>;
1573 };
1574 };
1575 };
Mario Six4eea5312018-09-27 09:19:31 +02001576
Dzmitry Sankouski298ffdd2023-01-22 18:21:23 +03001577 ofnode-foreach {
1578 compatible = "foreach";
1579
1580 first {
1581 prop1 = <1>;
1582 prop2 = <2>;
1583 };
1584
1585 second {
1586 prop1 = <1>;
1587 prop2 = <2>;
1588 };
1589 };
1590
Mario Six4eea5312018-09-27 09:19:31 +02001591 osd {
1592 compatible = "sandbox,sandbox_osd";
1593 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001594
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001595 sandbox_tee {
1596 compatible = "sandbox,tee";
1597 };
Bin Meng4f89d492018-10-15 02:21:26 -07001598
1599 sandbox_virtio1 {
1600 compatible = "sandbox,virtio1";
Simon Glass00fc8ca2023-01-17 10:47:51 -07001601 virtio-type = <4>; /* rng */
Bin Meng4f89d492018-10-15 02:21:26 -07001602 };
1603
1604 sandbox_virtio2 {
1605 compatible = "sandbox,virtio2";
1606 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001607
Simon Glass00fc8ca2023-01-17 10:47:51 -07001608 sandbox-virtio-blk {
1609 compatible = "sandbox,virtio1";
1610 virtio-type = <2>; /* block */
1611 };
1612
Etienne Carriere87d4f272020-09-09 18:44:05 +02001613 sandbox_scmi {
1614 compatible = "sandbox,scmi-devices";
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001615 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001616 resets = <&reset_scmi 3>;
1617 regul0-supply = <&regul0_scmi>;
1618 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001619 };
1620
Patrice Chotardf41a8242018-10-24 14:10:23 +02001621 pinctrl {
1622 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001623
Sean Anderson7f0f1802020-09-14 11:01:57 -04001624 pinctrl-names = "default", "alternate";
1625 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1626 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001627
Sean Anderson7f0f1802020-09-14 11:01:57 -04001628 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001629 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001630 pins = "P5";
1631 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001632 bias-pull-up;
1633 input-disable;
1634 };
1635 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001636 pins = "P6";
1637 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001638 output-high;
1639 drive-open-drain;
1640 };
1641 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001642 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001643 bias-pull-down;
1644 input-enable;
1645 };
1646 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001647 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001648 bias-disable;
1649 };
1650 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001651
1652 pinctrl_i2c: i2c {
1653 groups {
1654 groups = "I2C_UART";
1655 function = "I2C";
1656 };
1657
1658 pins {
1659 pins = "P0", "P1";
1660 drive-open-drain;
1661 };
1662 };
1663
1664 pinctrl_i2s: i2s {
1665 groups = "SPI_I2S";
1666 function = "I2S";
1667 };
1668
1669 pinctrl_spi: spi {
1670 groups = "SPI_I2S";
1671 function = "SPI";
1672
1673 cs {
1674 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1675 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1676 };
1677 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001678 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001679
Dario Binacchi55322622021-04-11 09:39:50 +02001680 pinctrl-single-no-width {
1681 compatible = "pinctrl-single";
1682 reg = <0x0000 0x238>;
1683 #pinctrl-cells = <1>;
1684 pinctrl-single,function-mask = <0x7f>;
1685 };
1686
1687 pinctrl-single-pins {
1688 compatible = "pinctrl-single";
1689 reg = <0x0000 0x238>;
1690 #pinctrl-cells = <1>;
1691 pinctrl-single,register-width = <32>;
1692 pinctrl-single,function-mask = <0x7f>;
1693
1694 pinmux_pwm_pins: pinmux_pwm_pins {
1695 pinctrl-single,pins = < 0x48 0x06 >;
1696 };
1697
1698 pinmux_spi0_pins: pinmux_spi0_pins {
1699 pinctrl-single,pins = <
1700 0x190 0x0c
1701 0x194 0x0c
1702 0x198 0x23
1703 0x19c 0x0c
1704 >;
1705 };
1706
1707 pinmux_uart0_pins: pinmux_uart0_pins {
1708 pinctrl-single,pins = <
1709 0x70 0x30
1710 0x74 0x00
1711 >;
1712 };
1713 };
1714
1715 pinctrl-single-bits {
1716 compatible = "pinctrl-single";
1717 reg = <0x0000 0x50>;
1718 #pinctrl-cells = <2>;
1719 pinctrl-single,bit-per-mux;
1720 pinctrl-single,register-width = <32>;
1721 pinctrl-single,function-mask = <0xf>;
1722
1723 pinmux_i2c0_pins: pinmux_i2c0_pins {
1724 pinctrl-single,bits = <
1725 0x10 0x00002200 0x0000ff00
1726 >;
1727 };
1728
1729 pinmux_lcd_pins: pinmux_lcd_pins {
1730 pinctrl-single,bits = <
1731 0x40 0x22222200 0xffffff00
1732 0x44 0x22222222 0xffffffff
1733 0x48 0x00000022 0x000000ff
1734 0x48 0x02000000 0x0f000000
1735 0x4c 0x02000022 0x0f0000ff
1736 >;
1737 };
1738 };
1739
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001740 hwspinlock@0 {
1741 compatible = "sandbox,hwspinlock";
1742 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001743
1744 dma: dma {
1745 compatible = "sandbox,dma";
1746 #dma-cells = <1>;
1747
1748 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1749 dma-names = "m2m", "tx0", "rx0";
1750 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001751
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001752 /*
1753 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1754 * end of the test. If parent mdio is removed first, clean-up of the
1755 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1756 * active at the end of the test. That it turn doesn't allow the mdio
1757 * class to be destroyed, triggering an error.
1758 */
1759 mdio-mux-test {
1760 compatible = "sandbox,mdio-mux";
1761 #address-cells = <1>;
1762 #size-cells = <0>;
1763 mdio-parent-bus = <&mdio>;
1764
1765 mdio-ch-test@0 {
1766 reg = <0>;
1767 };
1768 mdio-ch-test@1 {
1769 reg = <1>;
1770 };
1771 };
1772
1773 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001774 compatible = "sandbox,mdio";
Marek BehĂșnf3dd2132022-04-07 00:32:57 +02001775 #address-cells = <1>;
1776 #size-cells = <0>;
1777
1778 ethphy1: ethernet-phy@1 {
1779 reg = <1>;
1780 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001781 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001782
1783 pm-bus-test {
1784 compatible = "simple-pm-bus";
1785 clocks = <&clk_sandbox 4>;
1786 power-domains = <&pwrdom 1>;
1787 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001788
1789 resetc2: syscon-reset {
1790 compatible = "syscon-reset";
1791 #reset-cells = <1>;
1792 regmap = <&syscon0>;
1793 offset = <1>;
1794 mask = <0x27FFFFFF>;
1795 assert-high = <0>;
1796 };
1797
1798 syscon-reset-test {
1799 compatible = "sandbox,misc_sandbox";
1800 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1801 reset-names = "valid", "no_mask", "out_of_range";
1802 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301803
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001804 sysinfo {
1805 compatible = "sandbox,sysinfo-sandbox";
1806 };
1807
Sean Anderson1cbfed82021-04-20 10:50:58 -04001808 sysinfo-gpio {
1809 compatible = "gpio-sysinfo";
1810 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1811 revisions = <19>, <5>;
1812 names = "rev_a", "foo";
1813 };
1814
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301815 some_regmapped-bus {
1816 #address-cells = <0x1>;
1817 #size-cells = <0x1>;
1818
1819 ranges = <0x0 0x0 0x10>;
1820 compatible = "simple-bus";
1821
1822 regmap-test_0 {
1823 reg = <0 0x10>;
1824 compatible = "sandbox,regmap_test";
1825 };
1826 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001827
1828 thermal {
1829 compatible = "sandbox,thermal";
1830 };
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301831
1832 fwu-mdata {
1833 compatible = "u-boot,fwu-mdata-gpt";
1834 fwu-mdata-store = <&mmc0>;
1835 };
Abdellatif El Khlificc89b7c2023-04-17 10:11:55 +01001836
1837 nvmxip-qspi1@08000000 {
1838 compatible = "nvmxip,qspi";
1839 reg = <0x08000000 0x00200000>;
1840 lba_shift = <9>;
1841 lba = <4096>;
1842 };
1843
1844 nvmxip-qspi2@08200000 {
1845 compatible = "nvmxip,qspi";
1846 reg = <0x08200000 0x00100000>;
1847 lba_shift = <9>;
1848 lba = <2048>;
1849 };
Svyatoslav Ryhel8b215e12023-04-25 10:57:21 +03001850
1851 extcon {
1852 compatible = "sandbox,extcon";
1853 };
Abdellatif El Khlifia09852d2023-08-04 14:33:41 +01001854
1855 arm-ffa-emul {
1856 compatible = "sandbox,arm-ffa-emul";
1857
1858 sandbox-arm-ffa {
1859 compatible = "sandbox,arm-ffa";
1860 };
1861 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001862};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001863
1864#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001865#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001866
1867#ifdef CONFIG_SANDBOX_VPL
1868#include "sandbox_vpl.dtsi"
1869#endif
Simon Glass82cafee2023-06-01 10:23:01 -06001870
1871#include "cedit.dtsi"