blob: 9131eda970b03fe07dffec775c2ce8bcc8c3c982 [file] [log] [blame]
Simon Glass7dcc2f72021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glass2e7d35d2014-02-26 15:59:21 -070010/dts-v1/;
11
Eddie James5999ea22023-10-24 10:43:51 -050012#include <config.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010013#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowski289d0ea2021-02-18 11:33:18 +010015#include <dt-bindings/input/input.h>
Sean Anderson7f0f1802020-09-14 11:01:57 -040016#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +053017#include <dt-bindings/mux/mux.h>
Patrick Delaunay2c0f7822020-01-13 11:35:13 +010018
Simon Glass2e7d35d2014-02-26 15:59:21 -070019/ {
20 model = "sandbox";
21 compatible = "sandbox";
22 #address-cells = <1>;
Simon Glass0503e822015-07-06 12:54:36 -060023 #size-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -070024
Simon Glass00606d72014-07-23 06:55:03 -060025 aliases {
26 console = &uart0;
Michael Walle82a3c9e2021-02-25 16:51:11 +010027 ethernet0 = "/eth@10002000";
28 ethernet2 = &swp_0;
29 ethernet3 = &eth_3;
30 ethernet4 = &dsa_eth0;
31 ethernet5 = &eth_5;
Sean Andersonbedb1822022-05-05 13:11:30 -040032 ethernet6 = "/eth@10004000";
33 ethernet7 = &swp_1;
34 ethernet8 = &phy_eth0;
Simon Glass5d9a88f2018-10-01 12:22:40 -060035 gpio1 = &gpio_a;
36 gpio2 = &gpio_b;
Patrick Delaunayff526652020-01-13 11:35:14 +010037 gpio3 = &gpio_c;
Simon Glass9cc36a22015-01-25 08:27:05 -070038 i2c0 = "/i2c@0";
Simon Glasse48eeb92017-04-23 20:02:07 -060039 mmc0 = "/mmc0";
40 mmc1 = "/mmc1";
Simon Glass77bec9e2022-10-20 18:23:20 -060041 mmc2 = "/mmc2";
42 mmc3 = "/mmc3";
Simon Glassd08db022023-08-24 13:55:41 -060043 mmc4 = "/mmc4";
44 mmc5 = "/mmc5";
Alexander Gendin04291ee2023-10-09 01:24:36 +000045 mmc6 = "/mmc6";
Bin Mengdee4d752018-08-03 01:14:41 -070046 pci0 = &pci0;
47 pci1 = &pci1;
Bin Meng3ed214a2018-08-03 01:14:50 -070048 pci2 = &pci2;
Michael Wallebe1a6e92020-06-02 01:47:09 +020049 remoteproc0 = &rproc_1;
50 remoteproc1 = &rproc_2;
Simon Glass52d3bc52015-05-22 15:42:17 -060051 rtc0 = &rtc_0;
52 rtc1 = &rtc_1;
Simon Glass171e9912015-05-22 15:42:15 -060053 spi0 = "/spi@0";
Przemyslaw Marczakf64000c2015-05-13 13:38:34 +020054 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -070055 testbus3 = "/some-bus";
56 testfdt0 = "/some-bus/c-test@0";
Simon Glass981426e2020-12-16 21:20:26 -070057 testfdt12 = "/some-bus/c-test@1";
Simon Glass9cc36a22015-01-25 08:27:05 -070058 testfdt3 = "/b-test";
59 testfdt5 = "/some-bus/c-test@5";
60 testfdt8 = "/a-test";
Simon Glass93f44e82020-12-16 21:20:27 -070061 testfdtm1 = &testfdtm1;
Eugeniu Rosca507cef32018-05-19 14:13:55 +020062 fdt-dummy0 = "/translation-test@8000/dev@0,0";
63 fdt-dummy1 = "/translation-test@8000/dev@1,100";
64 fdt-dummy2 = "/translation-test@8000/dev@2,200";
65 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glasse00cb222015-03-25 12:23:05 -060066 usb0 = &usb_0;
67 usb1 = &usb_1;
68 usb2 = &usb_2;
Mario Six957983e2018-08-09 14:51:19 +020069 axi0 = &axi;
Mario Six4eea5312018-09-27 09:19:31 +020070 osd0 = "/osd";
Simon Glass00606d72014-07-23 06:55:03 -060071 };
72
Eddie James5999ea22023-10-24 10:43:51 -050073 reserved-memory {
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges;
77
78 event_log: tcg_event_log {
79 no-map;
80 reg = <(CFG_SYS_SDRAM_SIZE - 0x2000) 0x2000>;
81 };
82 };
83
Simon Glass8de98962022-10-20 18:23:15 -060084 binman: binman {
Philippe Reynes059df562022-03-28 22:56:53 +020085 };
86
Rasmus Villemoes8c728422021-04-21 11:06:55 +020087 config {
Simon Glass7de8bd02021-08-07 07:24:01 -060088 testing-bool;
89 testing-int = <123>;
90 testing-str = "testing";
Rasmus Villemoes8c728422021-04-21 11:06:55 +020091 environment {
92 from_fdt = "yes";
93 fdt_env_path = "";
94 };
95 };
96
Michal Simekdb5e3492023-08-31 08:59:05 +020097 options {
98 u-boot {
99 compatible = "u-boot,config";
100 bootscr-ram-offset = /bits/ 64 <0x12345678>;
Michal Simek44f35e12023-08-31 09:04:27 +0200101 bootscr-flash-offset = /bits/ 64 <0>;
102 bootscr-flash-size = /bits/ 64 <0x2000>;
Michal Simekdb5e3492023-08-31 08:59:05 +0200103 };
104 };
105
Simon Glassfb1451b2022-04-24 23:31:24 -0600106 bootstd {
Simon Glass8c103c32023-02-13 08:56:33 -0700107 bootph-verify;
Simon Glassfb1451b2022-04-24 23:31:24 -0600108 compatible = "u-boot,boot-std";
109
110 filename-prefixes = "/", "/boot/";
111 bootdev-order = "mmc2", "mmc1";
112
Simon Glass79f66352023-05-10 16:34:46 -0600113 extlinux {
114 compatible = "u-boot,extlinux";
Simon Glassfb1451b2022-04-24 23:31:24 -0600115 };
116
117 efi {
118 compatible = "u-boot,distro-efi";
119 };
Simon Glassa56f6632022-10-20 18:23:14 -0600120
Simon Glassd985f1d2023-01-06 08:52:41 -0600121 theme {
122 font-size = <30>;
Simon Glass7230fdb2023-06-01 10:23:00 -0600123 menu-inset = <3>;
124 menuitem-gap-y = <1>;
Simon Glassd985f1d2023-01-06 08:52:41 -0600125 };
126
Simon Glass2045ca52023-08-14 16:40:30 -0600127 cedit-theme {
128 font-size = <30>;
129 menu-inset = <3>;
130 menuitem-gap-y = <1>;
131 };
132
Simon Glass77bec9e2022-10-20 18:23:20 -0600133 /*
134 * This is used for the VBE OS-request tests. A FAT filesystem
135 * created in a partition with the VBE information appearing
Michal Simek92271d62023-09-07 14:55:48 +0200136 * before the partition starts
Simon Glass77bec9e2022-10-20 18:23:20 -0600137 */
Simon Glassa56f6632022-10-20 18:23:14 -0600138 firmware0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700139 bootph-verify;
Simon Glassa56f6632022-10-20 18:23:14 -0600140 compatible = "fwupd,vbe-simple";
141 storage = "mmc1";
142 skip-offset = <0x200>;
143 area-start = <0x400>;
144 area-size = <0x1000>;
145 state-offset = <0x400>;
146 state-size = <0x40>;
147 version-offset = <0x800>;
148 version-size = <0x100>;
149 };
Simon Glass77bec9e2022-10-20 18:23:20 -0600150
151 /*
152 * This is used for the VBE VPL tests. The MMC device holds the
153 * binman image.bin file. The test progresses through each phase
154 * of U-Boot, loading each in turn from MMC.
155 *
156 * Note that the test enables this node (and mmc3) before
157 * running U-Boot
158 */
159 firmware1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700160 bootph-verify;
Simon Glass77bec9e2022-10-20 18:23:20 -0600161 status = "disabled";
162 compatible = "fwupd,vbe-simple";
163 storage = "mmc3";
Simon Glass74b75aa2023-04-02 14:01:24 +1200164 skip-offset = <0x800000>;
Simon Glass77bec9e2022-10-20 18:23:20 -0600165 area-start = <0>;
166 area-size = <0xe00000>;
167 state-offset = <0xdffc00>;
168 state-size = <0x40>;
169 version-offset = <0xdffe00>;
170 version-size = <0x100>;
171 };
Simon Glassfb1451b2022-04-24 23:31:24 -0600172 };
173
Simon Glass82cafee2023-06-01 10:23:01 -0600174 cedit: cedit {
175 };
176
Andrew Scull0518e7a2022-05-30 10:00:12 +0000177 fuzzing-engine {
178 compatible = "sandbox,fuzzing-engine";
179 };
180
Nandor Hanf9db2f12021-06-10 16:56:44 +0300181 reboot-mode0 {
182 compatible = "reboot-mode-gpio";
183 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
184 u-boot,env-variable = "bootstatus";
185 mode-test = <0x01>;
186 mode-download = <0x03>;
187 };
188
Nandor Hanc74675b2021-06-10 16:56:45 +0300189 reboot_mode1: reboot-mode@14 {
190 compatible = "reboot-mode-rtc";
191 rtc = <&rtc_0>;
192 reg = <0x30 4>;
193 u-boot,env-variable = "bootstatus";
194 big-endian;
195 mode-test = <0x21969147>;
196 mode-download = <0x51939147>;
197 };
198
Simon Glassce6d99a2018-12-10 10:37:33 -0700199 audio: audio-codec {
200 compatible = "sandbox,audio-codec";
201 #sound-dai-cells = <1>;
202 };
203
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200204 buttons {
205 compatible = "gpio-keys";
206
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200207 btn1 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200208 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200209 label = "button1";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300210 linux,code = <BTN_1>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200211 };
212
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200213 btn2 {
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200214 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt39916bb2020-09-14 12:50:54 +0200215 label = "button2";
Dzmitry Sankouskiea6fdc12023-01-22 18:21:24 +0300216 linux,code = <BTN_2>;
Philippe Reynesa6c6f0f2020-07-24 18:19:51 +0200217 };
218 };
219
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100220 buttons2 {
221 compatible = "adc-keys";
222 io-channels = <&adc 3>;
223 keyup-threshold-microvolt = <3000000>;
224
225 button-up {
226 label = "button3";
227 linux,code = <KEY_F3>;
228 press-threshold-microvolt = <1500000>;
229 };
230
231 button-down {
232 label = "button4";
233 linux,code = <KEY_F4>;
234 press-threshold-microvolt = <1000000>;
235 };
236
237 button-enter {
238 label = "button5";
239 linux,code = <KEY_F5>;
240 press-threshold-microvolt = <500000>;
241 };
242 };
243
Simon Glasse96fa6c2018-12-10 10:37:34 -0700244 cros_ec: cros-ec {
Simon Glasse6c5c942018-10-01 12:22:08 -0600245 reg = <0 0>;
246 compatible = "google,cros-ec-sandbox";
247
248 /*
249 * This describes the flash memory within the EC. Note
250 * that the STM32L flash erases to 0, not 0xff.
251 */
252 flash {
253 image-pos = <0x08000000>;
254 size = <0x20000>;
255 erase-value = <0>;
256
257 /* Information for sandbox */
258 ro {
259 image-pos = <0>;
260 size = <0xf000>;
261 };
262 wp-ro {
263 image-pos = <0xf000>;
264 size = <0x1000>;
Simon Glassff5fa7d2021-01-21 13:57:14 -0700265 used = <0x884>;
266 compress = "lz4";
267 uncomp-size = <0xcf8>;
268 hash {
269 algo = "sha256";
270 value = [00 01 02 03 04 05 06 07
271 08 09 0a 0b 0c 0d 0e 0f
272 10 11 12 13 14 15 16 17
273 18 19 1a 1b 1c 1d 1e 1f];
274 };
Simon Glasse6c5c942018-10-01 12:22:08 -0600275 };
276 rw {
277 image-pos = <0x10000>;
278 size = <0x10000>;
279 };
280 };
Alper Nebi Yasake7122452021-05-19 19:33:31 +0300281
282 cros_ec_pwm: cros-ec-pwm {
283 compatible = "google,cros-ec-pwm";
284 #pwm-cells = <1>;
285 };
286
Simon Glasse6c5c942018-10-01 12:22:08 -0600287 };
288
Yannick Fertré23f965a2019-10-07 15:29:05 +0200289 dsi_host: dsi_host {
290 compatible = "sandbox,dsi-host";
291 };
292
Simon Glass2e7d35d2014-02-26 15:59:21 -0700293 a-test {
Simon Glass0503e822015-07-06 12:54:36 -0600294 reg = <0 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700295 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600296 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700297 ping-add = <0>;
Simon Glass8c103c32023-02-13 08:56:33 -0700298 bootph-all;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100299 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
300 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass3669e0e2015-01-05 20:05:29 -0700301 <0>, <&gpio_a 12>;
Patrick Delaunay2c0f7822020-01-13 11:35:13 +0100302 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
303 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
304 <&gpio_b 7 GPIO_IN 3 2 1>,
305 <&gpio_b 8 GPIO_OUT 3 2 1>,
306 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunayff526652020-01-13 11:35:14 +0100307 test3-gpios =
308 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
309 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
310 <&gpio_c 2 GPIO_OUT>,
311 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
312 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong9bf87e22020-05-05 10:43:18 +0200313 <&gpio_c 5 GPIO_IN>,
314 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
315 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530316 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
317 test5-gpios = <&gpio_a 19>;
318
Simon Glassfb933d02021-10-23 17:26:04 -0600319 bool-value;
Stefan Herbrechtsmeierb471bdc2022-06-14 15:21:30 +0200320 int8-value = /bits/ 8 <0x12>;
321 int16-value = /bits/ 16 <0x1234>;
Simon Glassa1b17e42018-12-10 10:37:37 -0700322 int-value = <1234>;
323 uint-value = <(-1234)>;
Dario Binacchi70573c62020-03-29 18:04:40 +0200324 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi4bb70752020-03-29 18:04:41 +0200325 int-array = <5678 9123 4567>;
Michal Simekfa12dfa2023-08-25 11:37:46 +0200326 int64-array = /bits/ 64 <0x1111222233334444 0x4444333322221111>;
Simon Glass06679002020-07-07 13:11:58 -0600327 str-value = "test string";
Simon Glass02554352020-02-06 09:55:00 -0700328 interrupts-extended = <&irq 3 0>;
Simon Glassfefac0b2020-07-07 13:12:11 -0600329 acpi,name = "GHIJ";
Patrick Delaunaycc72f3e2020-09-25 09:41:16 +0200330 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530331
332 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
333 <&muxcontroller0 2>, <&muxcontroller0 3>,
334 <&muxcontroller1>;
335 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
336 mux-syscon = <&syscon3>;
Dario Binacchi15daa482020-12-30 00:16:26 +0100337 display-timings {
338 timing0: 240x320 {
339 clock-frequency = <6500000>;
340 hactive = <240>;
341 vactive = <320>;
342 hfront-porch = <6>;
343 hback-porch = <7>;
344 hsync-len = <1>;
345 vback-porch = <5>;
346 vfront-porch = <8>;
347 vsync-len = <2>;
348 hsync-active = <1>;
349 vsync-active = <0>;
350 de-active = <1>;
351 pixelclk-active = <1>;
352 interlaced;
353 doublescan;
354 doubleclk;
355 };
356 timing1: 480x800 {
357 clock-frequency = <9000000>;
358 hactive = <480>;
359 vactive = <800>;
360 hfront-porch = <10>;
361 hback-porch = <59>;
362 hsync-len = <12>;
363 vback-porch = <15>;
364 vfront-porch = <17>;
365 vsync-len = <16>;
366 hsync-active = <0>;
367 vsync-active = <1>;
368 de-active = <0>;
369 pixelclk-active = <0>;
370 };
371 timing2: 800x480 {
372 clock-frequency = <33500000>;
373 hactive = <800>;
374 vactive = <480>;
375 hback-porch = <89>;
376 hfront-porch = <164>;
377 vback-porch = <23>;
378 vfront-porch = <10>;
379 hsync-len = <11>;
380 vsync-len = <13>;
381 };
382 };
Raphael Gallais-Poucd880582023-05-11 16:36:52 +0200383 panel-timing {
Nikhil M Jain2f3d6a42023-01-31 15:35:15 +0530384 clock-frequency = <6500000>;
385 hactive = <240>;
386 vactive = <320>;
387 hfront-porch = <6>;
388 hback-porch = <7>;
389 hsync-len = <1>;
390 vback-porch = <5>;
391 vfront-porch = <8>;
392 vsync-len = <2>;
393 hsync-active = <1>;
394 vsync-active = <0>;
395 de-active = <1>;
396 pixelclk-active = <1>;
397 interlaced;
398 doublescan;
399 doubleclk;
400 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700401 };
402
403 junk {
Simon Glass0503e822015-07-06 12:54:36 -0600404 reg = <1 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700405 compatible = "not,compatible";
406 };
407
408 no-compatible {
Simon Glass0503e822015-07-06 12:54:36 -0600409 reg = <2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700410 };
411
Simon Glass5d9a88f2018-10-01 12:22:40 -0600412 backlight: backlight {
413 compatible = "pwm-backlight";
414 enable-gpios = <&gpio_a 1>;
415 power-supply = <&ldo_1>;
416 pwms = <&pwm 0 1000>;
417 default-brightness-level = <5>;
418 brightness-levels = <0 16 32 64 128 170 202 234 255>;
419 };
420
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200421 bind-test {
Patrice Chotard1f0d5882020-07-28 09:13:33 +0200422 compatible = "simple-bus";
Jean-Jacques Hiblot49c752c2018-08-09 16:17:46 +0200423 bind-test-child1 {
424 compatible = "sandbox,phy";
425 #phy-cells = <1>;
426 };
427
428 bind-test-child2 {
429 compatible = "simple-bus";
430 };
431 };
432
Simon Glass2e7d35d2014-02-26 15:59:21 -0700433 b-test {
Simon Glass0503e822015-07-06 12:54:36 -0600434 reg = <3 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700435 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600436 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700437 ping-add = <3>;
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +0530438
439 mux-controls = <&muxcontroller0 0>;
440 mux-control-names = "mux0";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700441 };
442
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200443 phy_provider0: gen_phy@0 {
444 compatible = "sandbox,phy";
445 #phy-cells = <1>;
446 };
447
448 phy_provider1: gen_phy@1 {
449 compatible = "sandbox,phy";
450 #phy-cells = <0>;
451 broken;
452 };
453
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200454 phy_provider2: gen_phy@2 {
455 compatible = "sandbox,phy";
456 #phy-cells = <0>;
457 };
458
Jonas Karlman14639bf2023-08-31 22:16:35 +0000459 phy_provider3: gen_phy@3 {
460 compatible = "sandbox,phy";
461 #phy-cells = <2>;
462 };
463
Jean-Jacques Hiblot86322f52017-04-24 11:51:28 +0200464 gen_phy_user: gen_phy_user {
465 compatible = "simple-bus";
466 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
467 phy-names = "phy1", "phy2", "phy3";
468 };
469
Chunfeng Yun00c82ac2020-05-02 11:35:12 +0200470 gen_phy_user1: gen_phy_user1 {
471 compatible = "simple-bus";
472 phys = <&phy_provider0 0>, <&phy_provider2>;
473 phy-names = "phy1", "phy2";
474 };
475
Jonas Karlman14639bf2023-08-31 22:16:35 +0000476 gen_phy_user2: gen_phy_user2 {
477 compatible = "simple-bus";
478 phys = <&phy_provider3 0 0>;
479 phy-names = "phy1";
480 };
481
Simon Glass2e7d35d2014-02-26 15:59:21 -0700482 some-bus {
483 #address-cells = <1>;
484 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600485 compatible = "denx,u-boot-test-bus";
Simon Glass0503e822015-07-06 12:54:36 -0600486 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600487 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700488 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600489 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700490 compatible = "denx,u-boot-fdt-test";
491 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600492 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700493 ping-add = <5>;
494 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600495 c-test@0 {
496 compatible = "denx,u-boot-fdt-test";
497 reg = <0>;
498 ping-expect = <6>;
499 ping-add = <6>;
500 };
501 c-test@1 {
502 compatible = "denx,u-boot-fdt-test";
503 reg = <1>;
504 ping-expect = <7>;
505 ping-add = <7>;
506 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700507 };
508
509 d-test {
Simon Glass0503e822015-07-06 12:54:36 -0600510 reg = <3 1>;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600511 ping-expect = <6>;
512 ping-add = <6>;
513 compatible = "google,another-fdt-test";
514 };
515
516 e-test {
Simon Glass0503e822015-07-06 12:54:36 -0600517 reg = <3 1>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600518 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700519 ping-add = <6>;
520 compatible = "google,another-fdt-test";
521 };
522
Simon Glass9cc36a22015-01-25 08:27:05 -0700523 f-test {
524 compatible = "denx,u-boot-fdt-test";
525 };
526
527 g-test {
528 compatible = "denx,u-boot-fdt-test";
529 };
530
Bin Meng2786cd72018-10-10 22:07:01 -0700531 h-test {
532 compatible = "denx,u-boot-fdt-test1";
533 };
534
Chunfeng Yunbf6ad912020-05-02 11:35:10 +0200535 i-test {
536 compatible = "mediatek,u-boot-fdt-test";
537 #address-cells = <1>;
538 #size-cells = <0>;
539
540 subnode@0 {
541 reg = <0>;
542 };
543
544 subnode@1 {
545 reg = <1>;
546 };
547
548 subnode@2 {
549 reg = <2>;
550 };
551 };
552
Simon Glassdc12ebb2019-12-29 21:19:25 -0700553 devres-test {
554 compatible = "denx,u-boot-devres-test";
555 };
556
Jean-Jacques Hiblot88e6a602020-09-11 13:43:35 +0530557 another-test {
558 reg = <0 2>;
559 compatible = "denx,u-boot-fdt-test";
560 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
561 test5-gpios = <&gpio_a 19>;
562 };
563
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100564 mmio-bus@0 {
565 #address-cells = <1>;
566 #size-cells = <1>;
567 compatible = "denx,u-boot-test-bus";
568 dma-ranges = <0x10000000 0x00000000 0x00040000>;
569
570 subnode@0 {
571 compatible = "denx,u-boot-fdt-test";
572 };
573 };
574
575 mmio-bus@1 {
576 #address-cells = <1>;
577 #size-cells = <1>;
578 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Juliennee8801872021-01-12 13:55:25 +0100579
580 subnode@0 {
581 compatible = "denx,u-boot-fdt-test";
582 };
Nicolas Saenz Julienne283628c2021-01-12 13:55:23 +0100583 };
584
Simon Glass0f7b1112020-07-07 13:12:06 -0600585 acpi_test1: acpi-test {
Simon Glassf50cc952020-04-08 16:57:34 -0600586 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600587 acpi-ssdt-test-data = "ab";
Simon Glass01694582020-07-07 13:12:08 -0600588 acpi-dsdt-test-data = "hi";
Simon Glass1361a532020-07-07 13:11:39 -0600589 child {
590 compatible = "denx,u-boot-acpi-test";
591 };
Simon Glassf50cc952020-04-08 16:57:34 -0600592 };
593
Simon Glass0f7b1112020-07-07 13:12:06 -0600594 acpi_test2: acpi-test2 {
Simon Glass93f7f822020-04-26 09:19:46 -0600595 compatible = "denx,u-boot-acpi-test";
Simon Glassb5183172020-07-07 13:12:03 -0600596 acpi-ssdt-test-data = "cd";
Simon Glass01694582020-07-07 13:12:08 -0600597 acpi-dsdt-test-data = "jk";
Simon Glass93f7f822020-04-26 09:19:46 -0600598 };
599
Patrice Chotardee87a092017-09-04 14:55:57 +0200600 clocks {
601 clk_fixed: clk-fixed {
602 compatible = "fixed-clock";
603 #clock-cells = <0>;
604 clock-frequency = <1234>;
605 };
Anup Patelb630d572019-02-25 08:14:55 +0000606
607 clk_fixed_factor: clk-fixed-factor {
608 compatible = "fixed-factor-clock";
609 #clock-cells = <0>;
610 clock-div = <3>;
611 clock-mult = <2>;
612 clocks = <&clk_fixed>;
613 };
Lukasz Majewski4ab8e782019-06-24 15:50:47 +0200614
615 osc {
616 compatible = "fixed-clock";
617 #clock-cells = <0>;
618 clock-frequency = <20000000>;
619 };
Stephen Warren135aa952016-06-17 09:44:00 -0600620 };
621
622 clk_sandbox: clk-sbox {
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600623 compatible = "sandbox,clk";
Stephen Warren135aa952016-06-17 09:44:00 -0600624 #clock-cells = <1>;
Jean-Jacques Hiblot9a52be12019-10-22 14:00:07 +0200625 assigned-clocks = <&clk_sandbox 3>;
626 assigned-clock-rates = <321>;
Stephen Warren135aa952016-06-17 09:44:00 -0600627 };
628
629 clk-test {
630 compatible = "sandbox,clk-test";
631 clocks = <&clk_fixed>,
632 <&clk_sandbox 1>,
Jean-Jacques Hiblotdd2e0ce2019-10-22 14:00:05 +0200633 <&clk_sandbox 0>,
634 <&clk_sandbox 3>,
635 <&clk_sandbox 2>;
636 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass6a1c7ce2015-07-06 12:54:24 -0600637 };
638
Ashok Reddy Soma99b46472023-08-30 10:31:42 +0200639 clk-test2 {
640 compatible = "sandbox,clk-test";
641 assigned-clock-rates = <321>;
642 };
643
644 clk-test3 {
645 compatible = "sandbox,clk-test";
646 assigned-clocks = <&clk_sandbox 1>;
647 };
648
649 clk-test4 {
650 compatible = "sandbox,clk-test";
651 assigned-clock-rates = <654>, <321>;
652 assigned-clocks = <&clk_sandbox 1>;
653 };
654
Lukasz Majewski87e460c2019-06-24 15:50:50 +0200655 ccf: clk-ccf {
656 compatible = "sandbox,clk-ccf";
657 };
658
Simon Glass42b7f422021-12-04 08:56:31 -0700659 efi-media {
660 compatible = "sandbox,efi-media";
661 };
662
Simon Glass171e9912015-05-22 15:42:15 -0600663 eth@10002000 {
664 compatible = "sandbox,eth";
665 reg = <0x10002000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600666 };
667
668 eth_5: eth@10003000 {
669 compatible = "sandbox,eth";
670 reg = <0x10003000 0x1000>;
Sean Anderson3f51ba92022-05-05 13:11:44 -0400671 nvmem-cells = <&eth5_addr>;
672 nvmem-cell-names = "mac-address";
Simon Glass171e9912015-05-22 15:42:15 -0600673 };
674
Bin Meng71d79712015-08-27 22:25:53 -0700675 eth_3: sbe5 {
676 compatible = "sandbox,eth";
677 reg = <0x10005000 0x1000>;
Sean Anderson472caa62022-05-05 13:11:42 -0400678 nvmem-cells = <&eth3_addr>;
679 nvmem-cell-names = "mac-address";
Bin Meng71d79712015-08-27 22:25:53 -0700680 };
681
Simon Glass171e9912015-05-22 15:42:15 -0600682 eth@10004000 {
683 compatible = "sandbox,eth";
684 reg = <0x10004000 0x1000>;
Simon Glass171e9912015-05-22 15:42:15 -0600685 };
686
Marek Behúnf3dd2132022-04-07 00:32:57 +0200687 phy_eth0: phy-test-eth {
688 compatible = "sandbox,eth";
689 reg = <0x10007000 0x1000>;
Sean Andersone844e5d2022-05-05 13:11:35 -0400690 mac-address = [ 02 00 11 22 33 49 ];
Marek Behúnf3dd2132022-04-07 00:32:57 +0200691 phy-handle = <&ethphy1>;
Marek Behún123ca112022-04-07 00:33:01 +0200692 phy-mode = "2500base-x";
Marek Behúnf3dd2132022-04-07 00:32:57 +0200693 };
694
Claudiu Manoilff98da02021-03-14 20:14:57 +0800695 dsa_eth0: dsa-test-eth {
696 compatible = "sandbox,eth";
697 reg = <0x10006000 0x1000>;
Sean Andersond3f72872022-05-05 13:11:43 -0400698 nvmem-cells = <&eth4_addr>;
699 nvmem-cell-names = "mac-address";
Claudiu Manoilff98da02021-03-14 20:14:57 +0800700 };
701
702 dsa-test {
703 compatible = "sandbox,dsa";
704
705 ports {
706 #address-cells = <1>;
707 #size-cells = <0>;
708 swp_0: port@0 {
709 reg = <0>;
710 label = "lan0";
711 phy-mode = "rgmii-rxid";
712
713 fixed-link {
714 speed = <100>;
715 full-duplex;
716 };
717 };
718
719 swp_1: port@1 {
720 reg = <1>;
721 label = "lan1";
722 phy-mode = "rgmii-txid";
Bin Meng534c69b2021-03-14 20:14:58 +0800723 fixed-link = <0 1 100 0 0>;
Claudiu Manoilff98da02021-03-14 20:14:57 +0800724 };
725
726 port@2 {
727 reg = <2>;
728 ethernet = <&dsa_eth0>;
729
730 fixed-link {
731 speed = <1000>;
732 full-duplex;
733 };
734 };
735 };
736 };
737
Rajan Vaja31b82172018-09-19 03:43:46 -0700738 firmware {
739 sandbox_firmware: sandbox-firmware {
740 compatible = "sandbox,firmware";
741 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200742
Etienne Carriere41d62e22022-02-21 09:22:39 +0100743 scmi {
Etienne Carriere358599e2020-09-09 18:44:00 +0200744 compatible = "sandbox,scmi-agent";
745 #address-cells = <1>;
746 #size-cells = <0>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200747
AKASHI Takahiro8e545b32023-10-16 14:39:45 +0900748 pwrdom_scmi: protocol@11 {
749 reg = <0x11>;
750 #power-domain-cells = <1>;
751 };
752
Etienne Carriere41d62e22022-02-21 09:22:39 +0100753 clk_scmi: protocol@14 {
Etienne Carriere87d4f272020-09-09 18:44:05 +0200754 reg = <0x14>;
755 #clock-cells = <1>;
AKASHI Takahiroa89d9f42023-10-11 19:06:59 +0900756 linaro,sandbox-channel-id = <0x14>;
Etienne Carriere87d4f272020-09-09 18:44:05 +0200757 };
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200758
Etienne Carriere41d62e22022-02-21 09:22:39 +0100759 reset_scmi: protocol@16 {
Etienne Carrierec0dd1772020-09-09 18:44:07 +0200760 reg = <0x16>;
761 #reset-cells = <1>;
762 };
Etienne Carriere01242182021-03-08 22:38:07 +0100763
764 protocol@17 {
765 reg = <0x17>;
766
767 regulators {
768 #address-cells = <1>;
769 #size-cells = <0>;
770
Etienne Carriere41d62e22022-02-21 09:22:39 +0100771 regul0_scmi: reg@0 {
Etienne Carriere01242182021-03-08 22:38:07 +0100772 reg = <0>;
773 regulator-name = "sandbox-voltd0";
774 regulator-min-microvolt = <1100000>;
775 regulator-max-microvolt = <3300000>;
776 };
Etienne Carriere41d62e22022-02-21 09:22:39 +0100777 regul1_scmi: reg@1 {
Etienne Carriere01242182021-03-08 22:38:07 +0100778 reg = <0x1>;
779 regulator-name = "sandbox-voltd1";
780 regulator-min-microvolt = <1800000>;
781 };
782 };
783 };
Etienne Carriere358599e2020-09-09 18:44:00 +0200784 };
Alexey Romanovc3be2f12023-09-21 11:13:36 +0300785
786 sm: secure-monitor {
787 compatible = "sandbox,sm";
788 };
Rajan Vaja31b82172018-09-19 03:43:46 -0700789 };
790
Alexander Dahl1323d082022-09-30 14:04:30 +0200791 fpga {
792 compatible = "sandbox,fpga";
793 };
794
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100795 pinctrl-gpio {
796 compatible = "sandbox,pinctrl-gpio";
Simon Glass2e7d35d2014-02-26 15:59:21 -0700797
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100798 gpio_a: base-gpios {
799 compatible = "sandbox,gpio";
800 gpio-controller;
801 #gpio-cells = <1>;
802 gpio-bank-name = "a";
803 sandbox,gpio-count = <20>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200804 hog_input_active_low {
805 gpio-hog;
806 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200807 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200808 };
809 hog_input_active_high {
810 gpio-hog;
811 input;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200812 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200813 };
814 hog_output_low {
815 gpio-hog;
816 output-low;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200817 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200818 };
819 hog_output_high {
820 gpio-hog;
821 output-high;
Philippe Reynes037a56d2020-07-24 15:51:53 +0200822 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher9ba84322020-05-22 11:08:58 +0200823 };
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100824 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600825
Patrick Delaunaye5301ba2020-01-13 11:35:15 +0100826 gpio_b: extra-gpios {
827 compatible = "sandbox,gpio";
828 gpio-controller;
829 #gpio-cells = <5>;
830 gpio-bank-name = "b";
831 sandbox,gpio-count = <10>;
832 };
833
834 gpio_c: pinmux-gpios {
835 compatible = "sandbox,gpio";
836 gpio-controller;
837 #gpio-cells = <2>;
838 gpio-bank-name = "c";
839 sandbox,gpio-count = <10>;
840 };
Patrick Delaunayff526652020-01-13 11:35:14 +0100841 };
842
Simon Glassecc2ed52014-12-10 08:55:55 -0700843 i2c@0 {
844 #address-cells = <1>;
845 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -0600846 reg = <0 1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700847 compatible = "sandbox,i2c";
848 clock-frequency = <100000>;
Dario Binacchi55322622021-04-11 09:39:50 +0200849 pinctrl-names = "default";
850 pinctrl-0 = <&pinmux_i2c0_pins>;
851
Simon Glassecc2ed52014-12-10 08:55:55 -0700852 eeprom@2c {
Sean Anderson472caa62022-05-05 13:11:42 -0400853 #address-cells = <1>;
854 #size-cells = <1>;
Simon Glassecc2ed52014-12-10 08:55:55 -0700855 reg = <0x2c>;
856 compatible = "i2c-eeprom";
Simon Glass031a6502018-11-18 08:14:34 -0700857 sandbox,emul = <&emul_eeprom>;
Michal Simekf692b472020-05-28 11:48:55 +0200858 partitions {
859 compatible = "fixed-partitions";
860 #address-cells = <1>;
861 #size-cells = <1>;
862 bootcount_i2c: bootcount@10 {
863 reg = <10 2>;
864 };
865 };
Sean Anderson472caa62022-05-05 13:11:42 -0400866
867 eth3_addr: mac-address@24 {
868 reg = <24 6>;
869 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700870 };
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200871
Simon Glass52d3bc52015-05-22 15:42:17 -0600872 rtc_0: rtc@43 {
Sean Andersond3f72872022-05-05 13:11:43 -0400873 #address-cells = <1>;
874 #size-cells = <1>;
Simon Glass52d3bc52015-05-22 15:42:17 -0600875 reg = <0x43>;
876 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700877 sandbox,emul = <&emul0>;
Sean Andersond3f72872022-05-05 13:11:43 -0400878
879 eth4_addr: mac-address@40 {
880 reg = <0x40 6>;
881 };
Simon Glass52d3bc52015-05-22 15:42:17 -0600882 };
883
884 rtc_1: rtc@61 {
885 reg = <0x61>;
886 compatible = "sandbox-rtc";
Simon Glass031a6502018-11-18 08:14:34 -0700887 sandbox,emul = <&emul1>;
888 };
889
890 i2c_emul: emul {
891 reg = <0xff>;
892 compatible = "sandbox,i2c-emul-parent";
893 emul_eeprom: emul-eeprom {
894 compatible = "sandbox,i2c-eeprom";
895 sandbox,filename = "i2c.bin";
896 sandbox,size = <256>;
897 };
898 emul0: emul0 {
Simon Glassc4085d72021-02-03 06:01:17 -0700899 compatible = "sandbox,i2c-rtc-emul";
Simon Glass031a6502018-11-18 08:14:34 -0700900 };
901 emul1: emull {
Simon Glassc4085d72021-02-03 06:01:17 -0700902 compatible = "sandbox,i2c-rtc-emul";
Simon Glass52d3bc52015-05-22 15:42:17 -0600903 };
904 };
905
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200906 sandbox_pmic: sandbox_pmic {
907 reg = <0x40>;
Simon Glass031a6502018-11-18 08:14:34 -0700908 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +0200909 };
Lukasz Majewski686df492018-05-15 16:26:40 +0200910
911 mc34708: pmic@41 {
912 reg = <0x41>;
Simon Glass031a6502018-11-18 08:14:34 -0700913 sandbox,emul = <&emul_pmic1>;
Lukasz Majewski686df492018-05-15 16:26:40 +0200914 };
Simon Glassecc2ed52014-12-10 08:55:55 -0700915 };
916
Philipp Tomsich6f2d59c2018-12-14 21:14:29 +0100917 bootcount@0 {
918 compatible = "u-boot,bootcount-rtc";
919 rtc = <&rtc_1>;
920 offset = <0x13>;
921 };
922
Michal Simekf692b472020-05-28 11:48:55 +0200923 bootcount {
924 compatible = "u-boot,bootcount-i2c-eeprom";
925 i2c-eeprom = <&bootcount_i2c>;
926 };
927
Nandor Hanc50b21b2021-06-10 15:40:38 +0300928 bootcount_4@0 {
929 compatible = "u-boot,bootcount-syscon";
930 syscon = <&syscon0>;
931 reg = <0x0 0x04>, <0x0 0x04>;
932 reg-names = "syscon_reg", "offset";
933 };
934
935 bootcount_2@0 {
936 compatible = "u-boot,bootcount-syscon";
937 syscon = <&syscon0>;
938 reg = <0x0 0x04>, <0x0 0x02> ;
939 reg-names = "syscon_reg", "offset";
940 };
941
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100942 adc: adc@0 {
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100943 compatible = "sandbox,adc";
Marek Szyprowski289d0ea2021-02-18 11:33:18 +0100944 #io-channel-cells = <1>;
Przemyslaw Marczak08d63002015-10-27 13:08:06 +0100945 vdd-supply = <&buck2>;
946 vss-microvolts = <0>;
947 };
948
Mark Kettenisfb574622021-10-23 16:58:02 +0200949 iommu: iommu@0 {
950 compatible = "sandbox,iommu";
951 #iommu-cells = <0>;
952 };
953
Simon Glass02554352020-02-06 09:55:00 -0700954 irq: irq {
Simon Glassfbb0efd2019-12-06 21:41:59 -0700955 compatible = "sandbox,irq";
Simon Glass02554352020-02-06 09:55:00 -0700956 interrupt-controller;
957 #interrupt-cells = <2>;
Simon Glassfbb0efd2019-12-06 21:41:59 -0700958 };
959
Simon Glass3c97c4f2016-01-18 19:52:26 -0700960 lcd {
Simon Glass8c103c32023-02-13 08:56:33 -0700961 bootph-all;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700962 compatible = "sandbox,lcd-sdl";
Dario Binacchi55322622021-04-11 09:39:50 +0200963 pinctrl-names = "default";
964 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass3c97c4f2016-01-18 19:52:26 -0700965 xres = <1366>;
966 yres = <768>;
967 };
968
Simon Glass3c43fba2015-07-06 12:54:34 -0600969 leds {
970 compatible = "gpio-leds";
971
972 iracibble {
973 gpios = <&gpio_a 1 0>;
974 label = "sandbox:red";
975 };
976
977 martinet {
978 gpios = <&gpio_a 2 0>;
979 label = "sandbox:green";
980 };
Patrick Bruenn274fb462018-04-11 11:16:29 +0200981
982 default_on {
983 gpios = <&gpio_a 5 0>;
984 label = "sandbox:default_on";
985 default-state = "on";
986 };
987
988 default_off {
989 gpios = <&gpio_a 6 0>;
Sean Anderson3e41c7b2020-09-14 11:02:03 -0400990 /* label intentionally omitted */
Patrick Bruenn274fb462018-04-11 11:16:29 +0200991 default-state = "off";
992 };
Simon Glass3c43fba2015-07-06 12:54:34 -0600993 };
994
Paul Doelle1fc45d62022-07-04 09:00:25 +0000995 wdt-gpio-toggle {
Simon Glassbc003ca2023-08-10 09:53:13 -0600996 gpios = <&gpio_a 8 0>;
Rasmus Villemoesa9346b92021-08-19 11:57:05 +0200997 compatible = "linux,wdt-gpio";
Rasmus Villemoes4171c572021-08-19 11:57:06 +0200998 hw_margin_ms = <100>;
Paul Doelle1fc45d62022-07-04 09:00:25 +0000999 hw_algo = "toggle";
1000 always-running;
1001 };
1002
1003 wdt-gpio-level {
1004 gpios = <&gpio_a 7 0>;
1005 compatible = "linux,wdt-gpio";
1006 hw_margin_ms = <100>;
1007 hw_algo = "level";
Rasmus Villemoesa9346b92021-08-19 11:57:05 +02001008 always-running;
1009 };
1010
Stephen Warren8961b522016-05-16 17:41:37 -06001011 mbox: mbox {
1012 compatible = "sandbox,mbox";
1013 #mbox-cells = <1>;
1014 };
1015
1016 mbox-test {
1017 compatible = "sandbox,mbox-test";
1018 mboxes = <&mbox 100>, <&mbox 1>;
1019 mbox-names = "other", "test";
1020 };
1021
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001022 cpus {
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001023 #address-cells = <1>;
1024 #size-cells = <0>;
Sean Anderson7616e362020-09-28 10:52:23 -04001025 timebase-frequency = <2000000>;
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001026 cpu1: cpu@1 {
1027 device_type = "cpu";
1028 reg = <0x1>;
Sean Anderson7616e362020-09-28 10:52:23 -04001029 timebase-frequency = <3000000>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001030 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001031 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001032 };
Mario Sixfa44b532018-08-06 10:23:44 +02001033
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001034 cpu2: cpu@2 {
1035 device_type = "cpu";
1036 reg = <0x2>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001037 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001038 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001039 };
Mario Sixfa44b532018-08-06 10:23:44 +02001040
Heinrich Schuchardt8ae8da12021-08-28 11:42:08 +02001041 cpu3: cpu@3 {
1042 device_type = "cpu";
1043 reg = <0x3>;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001044 compatible = "sandbox,cpu_sandbox";
Simon Glass8c103c32023-02-13 08:56:33 -07001045 bootph-all;
AKASHI Takahiro073e6d62019-08-27 17:17:03 +09001046 };
Mario Sixfa44b532018-08-06 10:23:44 +02001047 };
1048
Dave Gerlach21e3c212020-07-15 23:39:58 -05001049 chipid: chipid {
1050 compatible = "sandbox,soc";
1051 };
1052
Simon Glasse96fa6c2018-12-10 10:37:34 -07001053 i2s: i2s {
1054 compatible = "sandbox,i2s";
1055 #sound-dai-cells = <1>;
Simon Glassecc79732019-02-16 20:24:56 -07001056 sandbox,silent; /* Don't emit sounds while testing */
Simon Glasse96fa6c2018-12-10 10:37:34 -07001057 };
1058
Jean-Jacques Hiblot07e33712019-07-05 09:33:57 +02001059 nop-test_0 {
1060 compatible = "sandbox,nop_sandbox1";
1061 nop-test_1 {
1062 compatible = "sandbox,nop_sandbox2";
1063 bind = "True";
1064 };
1065 nop-test_2 {
1066 compatible = "sandbox,nop_sandbox2";
1067 bind = "False";
1068 };
1069 };
1070
Roger Quadros2c120372022-10-20 16:30:46 +03001071 memory-controller {
1072 compatible = "sandbox,memory";
1073 };
1074
Mario Six004e67c2018-07-31 14:24:14 +02001075 misc-test {
Sean Anderson3f51ba92022-05-05 13:11:44 -04001076 #address-cells = <1>;
1077 #size-cells = <1>;
Mario Six004e67c2018-07-31 14:24:14 +02001078 compatible = "sandbox,misc_sandbox";
Sean Anderson3f51ba92022-05-05 13:11:44 -04001079
1080 eth5_addr: mac-address@10 {
1081 reg = <0x10 6>;
1082 };
Mario Six004e67c2018-07-31 14:24:14 +02001083 };
1084
Simon Glasse48eeb92017-04-23 20:02:07 -06001085 mmc2 {
1086 compatible = "sandbox,mmc";
Simon Glass6b165ab2021-07-05 16:32:58 -06001087 non-removable;
Simon Glasse48eeb92017-04-23 20:02:07 -06001088 };
1089
Simon Glassfb1451b2022-04-24 23:31:24 -06001090 /* This is used for the bootdev tests */
Simon Glasse48eeb92017-04-23 20:02:07 -06001091 mmc1 {
1092 compatible = "sandbox,mmc";
Simon Glassfb1451b2022-04-24 23:31:24 -06001093 filename = "mmc1.img";
Simon Glasse48eeb92017-04-23 20:02:07 -06001094 };
1095
Simon Glassfb1451b2022-04-24 23:31:24 -06001096 /* This is used for the fastboot tests */
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301097 mmc0: mmc0 {
Simon Glass8e6cc462015-07-06 12:54:32 -06001098 compatible = "sandbox,mmc";
1099 };
1100
Simon Glass77bec9e2022-10-20 18:23:20 -06001101 /* This is used for VBE VPL tests */
1102 mmc3 {
1103 status = "disabled";
1104 compatible = "sandbox,mmc";
1105 filename = "image.bin";
1106 non-removable;
1107 };
1108
Simon Glassd985f1d2023-01-06 08:52:41 -06001109 /* This is used for bootstd bootmenu tests */
1110 mmc4 {
1111 status = "disabled";
1112 compatible = "sandbox,mmc";
1113 filename = "mmc4.img";
1114 };
1115
Simon Glassd08db022023-08-24 13:55:41 -06001116 /* This is used for ChromiumOS tests */
1117 mmc5 {
1118 status = "disabled";
1119 compatible = "sandbox,mmc";
1120 filename = "mmc5.img";
1121 };
1122
Alexander Gendin04291ee2023-10-09 01:24:36 +00001123 /* This is used for mbr tests */
1124 mmc6 {
1125 status = "disabled";
1126 compatible = "sandbox,mmc";
1127 filename = "mmc6.img";
1128 };
1129
Simon Glassb45c8332019-02-16 20:24:50 -07001130 pch {
1131 compatible = "sandbox,pch";
1132 };
1133
Tom Rini42c64d12020-02-11 12:41:23 -05001134 pci0: pci@0 {
Simon Glassd3b7ff12015-03-05 12:25:34 -07001135 compatible = "sandbox,pci";
1136 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001137 bus-range = <0x00 0xff>;
Simon Glassd3b7ff12015-03-05 12:25:34 -07001138 #address-cells = <3>;
1139 #size-cells = <2>;
Simon Glassb0e2c232019-09-25 08:56:08 -06001140 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glassd3b7ff12015-03-05 12:25:34 -07001141 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis08386da2023-01-21 20:27:57 +01001142 iommu-map = <0x0010 &iommu 0 1>;
1143 iommu-map-mask = <0xfffffff8>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001144 pci@0,0 {
1145 compatible = "pci-generic";
1146 reg = <0x0000 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001147 sandbox,emul = <&swap_case_emul0_0>;
Bin Meng2db7f2b2018-08-03 01:14:39 -07001148 };
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001149 pci@1,0 {
1150 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001151 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
Simon Glassf69d3d62023-09-26 08:14:58 -06001152 reg = <0x02000814 0 0 0x80 0
1153 0x01000810 0 0 0xc0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001154 sandbox,emul = <&swap_case_emul0_1>;
Alex Marginean21ebbaf2019-06-07 11:24:24 +03001155 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001156 p2sb-pci@2,0 {
1157 compatible = "sandbox,p2sb";
1158 reg = <0x02001010 0 0 0 0>;
1159 sandbox,emul = <&p2sb_emul>;
1160
1161 adder {
1162 intel,p2sb-port-id = <3>;
1163 compatible = "sandbox,adder";
1164 };
1165 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001166 pci@1e,0 {
1167 compatible = "sandbox,pmc";
1168 reg = <0xf000 0 0 0 0>;
1169 sandbox,emul = <&pmc_emul1e>;
1170 acpi-base = <0x400>;
1171 gpe0-dwx-mask = <0xf>;
1172 gpe0-dwx-shift-base = <4>;
1173 gpe0-dw = <6 7 9>;
1174 gpe0-sts = <0x20>;
1175 gpe0-en = <0x30>;
1176 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001177 pci@1f,0 {
1178 compatible = "pci-generic";
Simon Glass33c215a2019-09-15 12:08:58 -06001179 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
Simon Glassf69d3d62023-09-26 08:14:58 -06001180 reg = <0x0100f810 0 0 0x100 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001181 sandbox,emul = <&swap_case_emul0_1f>;
1182 };
1183 };
1184
1185 pci-emul0 {
1186 compatible = "sandbox,pci-emul-parent";
1187 swap_case_emul0_0: emul0@0,0 {
1188 compatible = "sandbox,swap-case";
1189 };
1190 swap_case_emul0_1: emul0@1,0 {
1191 compatible = "sandbox,swap-case";
1192 use-ea;
1193 };
1194 swap_case_emul0_1f: emul0@1f,0 {
1195 compatible = "sandbox,swap-case";
Simon Glassd3b7ff12015-03-05 12:25:34 -07001196 };
Simon Glass3e17ffb2019-12-06 21:41:57 -07001197 p2sb_emul: emul@2,0 {
1198 compatible = "sandbox,p2sb-emul";
1199 };
Simon Glass3b65ee32019-12-06 21:41:54 -07001200 pmc_emul1e: emul@1e,0 {
1201 compatible = "sandbox,pmc-emul";
1202 };
Simon Glassd3b7ff12015-03-05 12:25:34 -07001203 };
1204
Tom Rini42c64d12020-02-11 12:41:23 -05001205 pci1: pci@1 {
Bin Mengdee4d752018-08-03 01:14:41 -07001206 compatible = "sandbox,pci";
1207 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001208 bus-range = <0x00 0xff>;
Bin Mengdee4d752018-08-03 01:14:41 -07001209 #address-cells = <3>;
1210 #size-cells = <2>;
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001211 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scull55e6adb2022-04-21 16:11:09 +00001212 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati4cf56ec2019-10-19 17:10:20 -07001213 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng490d13a2018-08-03 01:14:47 -07001214 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasutb59349a2018-10-10 21:27:08 +02001215 0x0c 0x00 0x1234 0x5678
1216 0x10 0x00 0x1234 0x5678>;
1217 pci@10,0 {
1218 reg = <0x8000 0 0 0 0>;
1219 };
Bin Mengdee4d752018-08-03 01:14:41 -07001220 };
1221
Tom Rini42c64d12020-02-11 12:41:23 -05001222 pci2: pci@2 {
Bin Meng3ed214a2018-08-03 01:14:50 -07001223 compatible = "sandbox,pci";
1224 device_type = "pci";
Tom Rini42c64d12020-02-11 12:41:23 -05001225 bus-range = <0x00 0xff>;
Bin Meng3ed214a2018-08-03 01:14:50 -07001226 #address-cells = <3>;
1227 #size-cells = <2>;
1228 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1229 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1230 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1231 pci@1f,0 {
1232 compatible = "pci-generic";
1233 reg = <0xf800 0 0 0 0>;
Simon Glass9b69ba42019-09-25 08:56:10 -06001234 sandbox,emul = <&swap_case_emul2_1f>;
1235 };
1236 };
1237
1238 pci-emul2 {
1239 compatible = "sandbox,pci-emul-parent";
1240 swap_case_emul2_1f: emul2@1f,0 {
1241 compatible = "sandbox,swap-case";
Bin Meng3ed214a2018-08-03 01:14:50 -07001242 };
1243 };
1244
Ramon Friedbb413332019-04-27 11:15:23 +03001245 pci_ep: pci_ep {
1246 compatible = "sandbox,pci_ep";
1247 };
1248
Simon Glass98561572017-04-23 20:10:44 -06001249 probing {
1250 compatible = "simple-bus";
1251 test1 {
1252 compatible = "denx,u-boot-probe-test";
1253 };
1254
1255 test2 {
1256 compatible = "denx,u-boot-probe-test";
1257 };
1258
1259 test3 {
1260 compatible = "denx,u-boot-probe-test";
1261 };
1262
1263 test4 {
1264 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001265 first-syscon = <&syscon0>;
1266 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunaya442e612019-03-07 09:57:13 +01001267 third-syscon = <&syscon2>;
Simon Glass98561572017-04-23 20:10:44 -06001268 };
1269 };
1270
Stephen Warren61f5ddc2016-07-13 13:45:31 -06001271 pwrdom: power-domain {
1272 compatible = "sandbox,power-domain";
1273 #power-domain-cells = <1>;
1274 };
1275
1276 power-domain-test {
1277 compatible = "sandbox,power-domain-test";
1278 power-domains = <&pwrdom 2>;
1279 };
1280
Simon Glass5d9a88f2018-10-01 12:22:40 -06001281 pwm: pwm {
Simon Glass43b41562017-04-16 21:01:11 -06001282 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001283 #pwm-cells = <2>;
Dario Binacchi55322622021-04-11 09:39:50 +02001284 pinctrl-names = "default";
1285 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glass43b41562017-04-16 21:01:11 -06001286 };
1287
1288 pwm2 {
1289 compatible = "sandbox,pwm";
Simon Glass5d9a88f2018-10-01 12:22:40 -06001290 #pwm-cells = <2>;
Simon Glass43b41562017-04-16 21:01:11 -06001291 };
1292
Simon Glass64ce0ca2015-07-06 12:54:31 -06001293 ram {
1294 compatible = "sandbox,ram";
1295 };
1296
Simon Glass5010d982015-07-06 12:54:29 -06001297 reset@0 {
1298 compatible = "sandbox,warm-reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001299 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001300 };
1301
1302 reset@1 {
1303 compatible = "sandbox,reset";
Simon Glass8c103c32023-02-13 08:56:33 -07001304 bootph-some-ram;
Simon Glass5010d982015-07-06 12:54:29 -06001305 };
1306
Stephen Warren4581b712016-06-17 09:43:59 -06001307 resetc: reset-ctl {
1308 compatible = "sandbox,reset-ctl";
1309 #reset-cells = <1>;
1310 };
1311
1312 reset-ctl-test {
1313 compatible = "sandbox,reset-ctl-test";
Neil Armstrongbdfe6902021-04-20 10:42:25 +02001314 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1315 reset-names = "other", "test", "test2", "test3";
Stephen Warren4581b712016-06-17 09:43:59 -06001316 };
1317
Sughosh Ganuff0dada2019-12-28 23:58:31 +05301318 rng {
1319 compatible = "sandbox,sandbox-rng";
1320 };
1321
Nishanth Menon52159402015-09-17 15:42:41 -05001322 rproc_1: rproc@1 {
1323 compatible = "sandbox,test-processor";
1324 remoteproc-name = "remoteproc-test-dev1";
1325 };
1326
1327 rproc_2: rproc@2 {
1328 compatible = "sandbox,test-processor";
1329 internal-memory-mapped;
1330 remoteproc-name = "remoteproc-test-dev2";
1331 };
1332
Simon Glass5d9a88f2018-10-01 12:22:40 -06001333 panel {
1334 compatible = "simple-panel";
1335 backlight = <&backlight 0 100>;
1336 };
1337
Simon Glass22c80d52022-09-21 16:21:47 +02001338 scsi {
1339 compatible = "sandbox,scsi";
1340 sandbox,filepath = "scsi.img";
1341 };
1342
Ramon Fried7fd7e2c2018-07-02 02:57:59 +03001343 smem@0 {
1344 compatible = "sandbox,smem";
1345 };
1346
Simon Glassd4901892018-12-10 10:37:36 -07001347 sound {
1348 compatible = "sandbox,sound";
1349 cpu {
1350 sound-dai = <&i2s 0>;
1351 };
1352
1353 codec {
1354 sound-dai = <&audio 0>;
1355 };
1356 };
1357
Simon Glass0ae0cb72014-10-13 23:42:11 -06001358 spi@0 {
1359 #address-cells = <1>;
1360 #size-cells = <0>;
Simon Glass0503e822015-07-06 12:54:36 -06001361 reg = <0 1>;
Simon Glass0ae0cb72014-10-13 23:42:11 -06001362 compatible = "sandbox,spi";
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001363 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi55322622021-04-11 09:39:50 +02001364 pinctrl-names = "default";
1365 pinctrl-0 = <&pinmux_spi0_pins>;
1366
Simon Glass0ae0cb72014-10-13 23:42:11 -06001367 spi.bin@0 {
1368 reg = <0>;
Neil Armstrongffd4c7c2019-02-10 10:16:20 +00001369 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass0ae0cb72014-10-13 23:42:11 -06001370 spi-max-frequency = <40000000>;
1371 sandbox,filename = "spi.bin";
1372 };
Ovidiu Panait1dc53ce2020-12-14 19:06:47 +02001373 spi.bin@1 {
1374 reg = <1>;
1375 compatible = "spansion,m25p16", "jedec,spi-nor";
1376 spi-max-frequency = <50000000>;
1377 sandbox,filename = "spi.bin";
1378 spi-cpol;
1379 spi-cpha;
1380 };
Simon Glass0ae0cb72014-10-13 23:42:11 -06001381 };
1382
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001383 syscon0: syscon@0 {
Simon Glass04035fd2015-07-06 12:54:35 -06001384 compatible = "sandbox,syscon0";
Mario Six82744c22018-10-04 09:00:40 +02001385 reg = <0x10 16>;
Simon Glass04035fd2015-07-06 12:54:35 -06001386 };
1387
Jean-Jacques Hiblot6c3af1f2018-11-29 10:57:37 +01001388 another_system_controller: syscon@1 {
Simon Glass04035fd2015-07-06 12:54:35 -06001389 compatible = "sandbox,syscon1";
Simon Glass0503e822015-07-06 12:54:36 -06001390 reg = <0x20 5
1391 0x28 6
1392 0x30 7
1393 0x38 8>;
Simon Glass04035fd2015-07-06 12:54:35 -06001394 };
1395
Patrick Delaunaya442e612019-03-07 09:57:13 +01001396 syscon2: syscon@2 {
Masahiro Yamada99552c32018-04-23 13:26:53 +09001397 compatible = "simple-mfd", "syscon";
1398 reg = <0x40 5
1399 0x48 6
1400 0x50 7
1401 0x58 8>;
1402 };
1403
Jean-Jacques Hiblot739592c2020-10-16 16:16:34 +05301404 syscon3: syscon@3 {
1405 compatible = "simple-mfd", "syscon";
1406 reg = <0x000100 0x10>;
1407
1408 muxcontroller0: a-mux-controller {
1409 compatible = "mmio-mux";
1410 #mux-control-cells = <1>;
1411
1412 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1413 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1414 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1415 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1416 u-boot,mux-autoprobe;
1417 };
1418 };
1419
1420 muxcontroller1: emul-mux-controller {
1421 compatible = "mux-emul";
1422 #mux-control-cells = <0>;
1423 u-boot,mux-autoprobe;
1424 idle-state = <0xabcd>;
1425 };
1426
Simon Glass93f44e82020-12-16 21:20:27 -07001427 testfdtm0 {
1428 compatible = "denx,u-boot-fdtm-test";
1429 };
1430
1431 testfdtm1: testfdtm1 {
1432 compatible = "denx,u-boot-fdtm-test";
1433 };
1434
1435 testfdtm2 {
1436 compatible = "denx,u-boot-fdtm-test";
1437 };
1438
Sean Anderson7616e362020-09-28 10:52:23 -04001439 timer@0 {
Thomas Choue7cc8d12015-12-11 16:27:34 +08001440 compatible = "sandbox,timer";
1441 clock-frequency = <1000000>;
1442 };
1443
Sean Anderson7616e362020-09-28 10:52:23 -04001444 timer@1 {
1445 compatible = "sandbox,timer";
1446 sandbox,timebase-frequency-fallback;
1447 };
1448
Miquel Raynalb91ad162018-05-15 11:57:27 +02001449 tpm2 {
1450 compatible = "sandbox,tpm2";
Eddie James5999ea22023-10-24 10:43:51 -05001451 memory-region = <&event_log>;
Miquel Raynalb91ad162018-05-15 11:57:27 +02001452 };
1453
Simon Glass4fef6572023-02-21 06:24:51 -07001454 tpm {
1455 compatible = "google,sandbox-tpm";
1456 };
1457
Simon Glass171e9912015-05-22 15:42:15 -06001458 uart0: serial {
1459 compatible = "sandbox,serial";
Simon Glass8c103c32023-02-13 08:56:33 -07001460 bootph-all;
Dario Binacchi55322622021-04-11 09:39:50 +02001461 pinctrl-names = "default";
1462 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershbergerbfacad72015-03-22 17:09:15 -05001463 };
1464
Simon Glasse00cb222015-03-25 12:23:05 -06001465 usb_0: usb@0 {
1466 compatible = "sandbox,usb";
1467 status = "disabled";
1468 hub {
1469 compatible = "sandbox,usb-hub";
1470 #address-cells = <1>;
1471 #size-cells = <0>;
1472 flash-stick {
1473 reg = <0>;
1474 compatible = "sandbox,usb-flash";
1475 };
1476 };
1477 };
1478
1479 usb_1: usb@1 {
1480 compatible = "sandbox,usb";
Mark Kettenisfb574622021-10-23 16:58:02 +02001481 iommus = <&iommu>;
Simon Glasse00cb222015-03-25 12:23:05 -06001482 hub {
1483 compatible = "usb-hub";
1484 usb,device-class = <9>;
Michael Wallec03b7612020-06-02 01:47:07 +02001485 #address-cells = <1>;
1486 #size-cells = <0>;
Simon Glasse00cb222015-03-25 12:23:05 -06001487 hub-emul {
1488 compatible = "sandbox,usb-hub";
1489 #address-cells = <1>;
1490 #size-cells = <0>;
Simon Glass431cbd62015-11-08 23:48:01 -07001491 flash-stick@0 {
Simon Glasse00cb222015-03-25 12:23:05 -06001492 reg = <0>;
1493 compatible = "sandbox,usb-flash";
1494 sandbox,filepath = "testflash.bin";
1495 };
1496
Simon Glass431cbd62015-11-08 23:48:01 -07001497 flash-stick@1 {
1498 reg = <1>;
1499 compatible = "sandbox,usb-flash";
1500 sandbox,filepath = "testflash1.bin";
1501 };
1502
1503 flash-stick@2 {
1504 reg = <2>;
1505 compatible = "sandbox,usb-flash";
1506 sandbox,filepath = "testflash2.bin";
1507 };
1508
Simon Glassbff1a712015-11-08 23:48:08 -07001509 keyb@3 {
1510 reg = <3>;
1511 compatible = "sandbox,usb-keyb";
1512 };
1513
Simon Glasse00cb222015-03-25 12:23:05 -06001514 };
Michael Wallec03b7612020-06-02 01:47:07 +02001515
1516 usbstor@1 {
1517 reg = <1>;
1518 };
1519 usbstor@3 {
1520 reg = <3>;
1521 };
Simon Glasse00cb222015-03-25 12:23:05 -06001522 };
1523 };
1524
1525 usb_2: usb@2 {
1526 compatible = "sandbox,usb";
1527 status = "disabled";
1528 };
1529
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001530 spmi: spmi@0 {
1531 compatible = "sandbox,spmi";
1532 #address-cells = <0x1>;
1533 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001534 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001535 pm8916@0 {
1536 compatible = "qcom,spmi-pmic";
1537 reg = <0x0 0x1>;
1538 #address-cells = <0x1>;
1539 #size-cells = <0x1>;
Simon Glassa605b0f2019-09-25 08:55:59 -06001540 ranges;
Mateusz Kulikowskid33776e2016-03-31 23:12:28 +02001541
1542 spmi_gpios: gpios@c000 {
1543 compatible = "qcom,pm8916-gpio";
1544 reg = <0xc000 0x400>;
1545 gpio-controller;
1546 gpio-count = <4>;
1547 #gpio-cells = <2>;
1548 gpio-bank-name="spmi";
1549 };
1550 };
1551 };
maxims@google.com0753bc22017-04-17 12:00:21 -07001552
1553 wdt0: wdt@0 {
1554 compatible = "sandbox,wdt";
Rasmus Villemoes4171c572021-08-19 11:57:06 +02001555 hw_margin_ms = <200>;
maxims@google.com0753bc22017-04-17 12:00:21 -07001556 };
Rob Clarkf2006802018-01-10 11:33:30 +01001557
Mario Six957983e2018-08-09 14:51:19 +02001558 axi: axi@0 {
1559 compatible = "sandbox,axi";
1560 #address-cells = <0x1>;
1561 #size-cells = <0x1>;
1562 store@0 {
1563 compatible = "sandbox,sandbox_store";
1564 reg = <0x0 0x400>;
1565 };
1566 };
1567
Rob Clarkf2006802018-01-10 11:33:30 +01001568 chosen {
Simon Glass7e878162018-02-03 10:36:58 -07001569 #address-cells = <1>;
1570 #size-cells = <1>;
Simon Glass14ca9f72020-01-27 08:49:43 -07001571 setting = "sunrise ohoka";
1572 other-node = "/some-bus/c-test@5";
Simon Glassbd933bf2020-01-27 08:49:46 -07001573 int-values = <0x1937 72993>;
Simon Glass0f7b1112020-07-07 13:12:06 -06001574 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Algapally Santosh Sagarbd9ff682023-09-21 16:50:43 +05301575 stdout-path = "serial0:115200n8";
Rob Clarkf2006802018-01-10 11:33:30 +01001576 chosen-test {
1577 compatible = "denx,u-boot-fdt-test";
1578 reg = <9 1>;
1579 };
1580 };
Mario Sixe8d52912018-03-12 14:53:33 +01001581
1582 translation-test@8000 {
1583 compatible = "simple-bus";
1584 reg = <0x8000 0x4000>;
1585
1586 #address-cells = <0x2>;
1587 #size-cells = <0x1>;
1588
1589 ranges = <0 0x0 0x8000 0x1000
1590 1 0x100 0x9000 0x1000
1591 2 0x200 0xA000 0x1000
1592 3 0x300 0xB000 0x1000
1593 >;
1594
Fabien Dessenne641067f2019-05-31 15:11:30 +02001595 dma-ranges = <0 0x000 0x10000000 0x1000
1596 1 0x100 0x20000000 0x1000
1597 >;
1598
Mario Sixe8d52912018-03-12 14:53:33 +01001599 dev@0,0 {
1600 compatible = "denx,u-boot-fdt-dummy";
1601 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojas79598822018-12-03 19:37:09 +01001602 reg-names = "sandbox-dummy-0";
Mario Sixe8d52912018-03-12 14:53:33 +01001603 };
1604
1605 dev@1,100 {
1606 compatible = "denx,u-boot-fdt-dummy";
1607 reg = <1 0x100 0x1000>;
1608
1609 };
1610
1611 dev@2,200 {
1612 compatible = "denx,u-boot-fdt-dummy";
1613 reg = <2 0x200 0x1000>;
1614 };
1615
1616
1617 noxlatebus@3,300 {
1618 compatible = "simple-bus";
1619 reg = <3 0x300 0x1000>;
1620
1621 #address-cells = <0x1>;
1622 #size-cells = <0x0>;
1623
1624 dev@42 {
1625 compatible = "denx,u-boot-fdt-dummy";
1626 reg = <0x42>;
1627 };
1628 };
1629 };
Mario Six4eea5312018-09-27 09:19:31 +02001630
Dzmitry Sankouski298ffdd2023-01-22 18:21:23 +03001631 ofnode-foreach {
1632 compatible = "foreach";
1633
1634 first {
1635 prop1 = <1>;
1636 prop2 = <2>;
1637 };
1638
1639 second {
1640 prop1 = <1>;
1641 prop2 = <2>;
1642 };
1643 };
1644
Mario Six4eea5312018-09-27 09:19:31 +02001645 osd {
1646 compatible = "sandbox,sandbox_osd";
1647 };
Tom Rinid24c1d02018-09-30 18:16:51 -04001648
Jens Wiklanderfa830ae2018-09-25 16:40:16 +02001649 sandbox_tee {
1650 compatible = "sandbox,tee";
1651 };
Bin Meng4f89d492018-10-15 02:21:26 -07001652
1653 sandbox_virtio1 {
1654 compatible = "sandbox,virtio1";
Simon Glass00fc8ca2023-01-17 10:47:51 -07001655 virtio-type = <4>; /* rng */
Bin Meng4f89d492018-10-15 02:21:26 -07001656 };
1657
1658 sandbox_virtio2 {
1659 compatible = "sandbox,virtio2";
1660 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001661
Simon Glass00fc8ca2023-01-17 10:47:51 -07001662 sandbox-virtio-blk {
1663 compatible = "sandbox,virtio1";
1664 virtio-type = <2>; /* block */
1665 };
1666
Etienne Carriere87d4f272020-09-09 18:44:05 +02001667 sandbox_scmi {
1668 compatible = "sandbox,scmi-devices";
AKASHI Takahiro8e545b32023-10-16 14:39:45 +09001669 power-domains = <&pwrdom_scmi 2>;
Etienne Carriere10d3e5d2022-02-21 09:22:41 +01001670 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere41d62e22022-02-21 09:22:39 +01001671 resets = <&reset_scmi 3>;
1672 regul0-supply = <&regul0_scmi>;
1673 regul1-supply = <&regul1_scmi>;
Etienne Carriere87d4f272020-09-09 18:44:05 +02001674 };
1675
Patrice Chotardf41a8242018-10-24 14:10:23 +02001676 pinctrl {
1677 compatible = "sandbox,pinctrl";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001678
Sean Anderson7f0f1802020-09-14 11:01:57 -04001679 pinctrl-names = "default", "alternate";
1680 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1681 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001682
Sean Anderson7f0f1802020-09-14 11:01:57 -04001683 pinctrl_gpios: gpios {
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001684 gpio0 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001685 pins = "P5";
1686 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001687 bias-pull-up;
1688 input-disable;
1689 };
1690 gpio1 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001691 pins = "P6";
1692 function = "GPIO";
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001693 output-high;
1694 drive-open-drain;
1695 };
1696 gpio2 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001697 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001698 bias-pull-down;
1699 input-enable;
1700 };
1701 gpio3 {
Sean Anderson7f0f1802020-09-14 11:01:57 -04001702 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunayd15c05b2020-01-13 11:35:12 +01001703 bias-disable;
1704 };
1705 };
Sean Anderson7f0f1802020-09-14 11:01:57 -04001706
1707 pinctrl_i2c: i2c {
1708 groups {
1709 groups = "I2C_UART";
1710 function = "I2C";
1711 };
1712
1713 pins {
1714 pins = "P0", "P1";
1715 drive-open-drain;
1716 };
1717 };
1718
1719 pinctrl_i2s: i2s {
1720 groups = "SPI_I2S";
1721 function = "I2S";
1722 };
1723
1724 pinctrl_spi: spi {
1725 groups = "SPI_I2S";
1726 function = "SPI";
1727
1728 cs {
1729 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1730 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1731 };
1732 };
Patrice Chotardf41a8242018-10-24 14:10:23 +02001733 };
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001734
Dario Binacchi55322622021-04-11 09:39:50 +02001735 pinctrl-single-no-width {
1736 compatible = "pinctrl-single";
1737 reg = <0x0000 0x238>;
1738 #pinctrl-cells = <1>;
1739 pinctrl-single,function-mask = <0x7f>;
1740 };
1741
1742 pinctrl-single-pins {
1743 compatible = "pinctrl-single";
1744 reg = <0x0000 0x238>;
1745 #pinctrl-cells = <1>;
1746 pinctrl-single,register-width = <32>;
1747 pinctrl-single,function-mask = <0x7f>;
1748
1749 pinmux_pwm_pins: pinmux_pwm_pins {
1750 pinctrl-single,pins = < 0x48 0x06 >;
1751 };
1752
1753 pinmux_spi0_pins: pinmux_spi0_pins {
1754 pinctrl-single,pins = <
1755 0x190 0x0c
1756 0x194 0x0c
1757 0x198 0x23
1758 0x19c 0x0c
1759 >;
1760 };
1761
1762 pinmux_uart0_pins: pinmux_uart0_pins {
1763 pinctrl-single,pins = <
1764 0x70 0x30
1765 0x74 0x00
1766 >;
1767 };
1768 };
1769
1770 pinctrl-single-bits {
1771 compatible = "pinctrl-single";
1772 reg = <0x0000 0x50>;
1773 #pinctrl-cells = <2>;
1774 pinctrl-single,bit-per-mux;
1775 pinctrl-single,register-width = <32>;
1776 pinctrl-single,function-mask = <0xf>;
1777
1778 pinmux_i2c0_pins: pinmux_i2c0_pins {
1779 pinctrl-single,bits = <
1780 0x10 0x00002200 0x0000ff00
1781 >;
1782 };
1783
1784 pinmux_lcd_pins: pinmux_lcd_pins {
1785 pinctrl-single,bits = <
1786 0x40 0x22222200 0xffffff00
1787 0x44 0x22222222 0xffffffff
1788 0x48 0x00000022 0x000000ff
1789 0x48 0x02000000 0x0f000000
1790 0x4c 0x02000022 0x0f0000ff
1791 >;
1792 };
1793 };
1794
Benjamin Gaignard7f84fc62018-11-27 13:49:50 +01001795 hwspinlock@0 {
1796 compatible = "sandbox,hwspinlock";
1797 };
Grygorii Strashkob3309912018-11-28 19:17:51 +01001798
1799 dma: dma {
1800 compatible = "sandbox,dma";
1801 #dma-cells = <1>;
1802
1803 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1804 dma-names = "m2m", "tx0", "rx0";
1805 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001806
Alex Margineanc3d9f3f2019-07-12 10:13:53 +03001807 /*
1808 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1809 * end of the test. If parent mdio is removed first, clean-up of the
1810 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1811 * active at the end of the test. That it turn doesn't allow the mdio
1812 * class to be destroyed, triggering an error.
1813 */
1814 mdio-mux-test {
1815 compatible = "sandbox,mdio-mux";
1816 #address-cells = <1>;
1817 #size-cells = <0>;
1818 mdio-parent-bus = <&mdio>;
1819
1820 mdio-ch-test@0 {
1821 reg = <0>;
1822 };
1823 mdio-ch-test@1 {
1824 reg = <1>;
1825 };
1826 };
1827
1828 mdio: mdio-test {
Alex Margineanec9594a2019-06-03 19:12:28 +03001829 compatible = "sandbox,mdio";
Marek Behúnf3dd2132022-04-07 00:32:57 +02001830 #address-cells = <1>;
1831 #size-cells = <0>;
1832
1833 ethphy1: ethernet-phy@1 {
1834 reg = <1>;
1835 };
Alex Margineanec9594a2019-06-03 19:12:28 +03001836 };
Sean Anderson4a3390f2020-06-24 06:41:12 -04001837
1838 pm-bus-test {
1839 compatible = "simple-pm-bus";
1840 clocks = <&clk_sandbox 4>;
1841 power-domains = <&pwrdom 1>;
1842 };
Sean Anderson038b13e2020-06-24 06:41:14 -04001843
1844 resetc2: syscon-reset {
1845 compatible = "syscon-reset";
1846 #reset-cells = <1>;
1847 regmap = <&syscon0>;
1848 offset = <1>;
1849 mask = <0x27FFFFFF>;
1850 assert-high = <0>;
1851 };
1852
1853 syscon-reset-test {
1854 compatible = "sandbox,misc_sandbox";
1855 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1856 reset-names = "valid", "no_mask", "out_of_range";
1857 };
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301858
Simon Glass3a8ee3d2020-11-05 06:32:05 -07001859 sysinfo {
1860 compatible = "sandbox,sysinfo-sandbox";
1861 };
1862
Sean Anderson1cbfed82021-04-20 10:50:58 -04001863 sysinfo-gpio {
1864 compatible = "gpio-sysinfo";
1865 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1866 revisions = <19>, <5>;
1867 names = "rev_a", "foo";
1868 };
1869
Jean-Jacques Hiblot0ced26a2020-09-24 10:04:18 +05301870 some_regmapped-bus {
1871 #address-cells = <0x1>;
1872 #size-cells = <0x1>;
1873
1874 ranges = <0x0 0x0 0x10>;
1875 compatible = "simple-bus";
1876
1877 regmap-test_0 {
1878 reg = <0 0x10>;
1879 compatible = "sandbox,regmap_test";
1880 };
1881 };
Robert Marko1fad2cb2022-09-06 13:30:35 +02001882
1883 thermal {
1884 compatible = "sandbox,thermal";
1885 };
Sughosh Ganu873cf8a2022-10-21 18:16:05 +05301886
1887 fwu-mdata {
1888 compatible = "u-boot,fwu-mdata-gpt";
1889 fwu-mdata-store = <&mmc0>;
1890 };
Abdellatif El Khlificc89b7c2023-04-17 10:11:55 +01001891
1892 nvmxip-qspi1@08000000 {
1893 compatible = "nvmxip,qspi";
1894 reg = <0x08000000 0x00200000>;
1895 lba_shift = <9>;
1896 lba = <4096>;
1897 };
1898
1899 nvmxip-qspi2@08200000 {
1900 compatible = "nvmxip,qspi";
1901 reg = <0x08200000 0x00100000>;
1902 lba_shift = <9>;
1903 lba = <2048>;
1904 };
Svyatoslav Ryhel8b215e12023-04-25 10:57:21 +03001905
1906 extcon {
1907 compatible = "sandbox,extcon";
1908 };
Abdellatif El Khlifia09852d2023-08-04 14:33:41 +01001909
1910 arm-ffa-emul {
1911 compatible = "sandbox,arm-ffa-emul";
1912
1913 sandbox-arm-ffa {
1914 compatible = "sandbox,arm-ffa";
1915 };
1916 };
Sean Andersonbc8e8a42023-11-04 16:37:52 -04001917
1918 nand-controller {
1919 #address-cells = <1>;
1920 #size-cells = <0>;
1921 compatible = "sandbox,nand";
1922
1923 nand@0 {
1924 reg = <0>;
1925 nand-ecc-mode = "soft";
1926 sandbox,id = [00 e3];
1927 sandbox,erasesize = <(8 * 1024)>;
1928 sandbox,oobsize = <16>;
1929 sandbox,pagesize = <512>;
1930 sandbox,pages = <0x2000>;
1931 sandbox,err-count = <1>;
1932 sandbox,err-step-size = <512>;
1933 };
1934
1935 /* MT29F64G08AKABA */
1936 nand@1 {
1937 reg = <1>;
1938 nand-ecc-mode = "soft_bch";
1939 sandbox,id = [2C 48 00 26 89 00 00 00];
1940 sandbox,onfi = [
1941 4f 4e 46 49 0e 00 5a 00
1942 ff 01 00 00 00 00 03 00
1943 00 00 00 00 00 00 00 00
1944 00 00 00 00 00 00 00 00
1945 4d 49 43 52 4f 4e 20 20
1946 20 20 20 20 4d 54 32 39
1947 46 36 34 47 30 38 41 4b
1948 41 42 41 43 35 20 20 20
1949 2c 00 00 00 00 00 00 00
1950 00 00 00 00 00 00 00 00
1951 00 10 00 00 e0 00 00 02
1952 00 00 1c 00 80 00 00 00
1953 00 10 00 00 02 23 01 50
1954 00 01 05 01 00 00 04 00
1955 04 01 1e 00 00 00 00 00
1956 00 00 00 00 00 00 00 00
1957 0e 1f 00 1f 00 f4 01 ac
1958 0d 19 00 c8 00 00 00 00
1959 00 00 00 00 00 00 0a 07
1960 19 00 00 00 00 00 00 00
1961 00 00 00 00 01 00 01 00
1962 00 00 04 10 01 81 04 02
1963 02 01 1e 90 00 00 00 00
1964 00 00 00 00 00 00 00 00
1965 00 00 00 00 00 00 00 00
1966 00 00 00 00 00 00 00 00
1967 00 00 00 00 00 00 00 00
1968 00 00 00 00 00 00 00 00
1969 00 00 00 00 00 00 00 00
1970 00 00 00 00 00 00 00 00
1971 00 00 00 00 00 00 00 00
1972 00 00 00 00 00 03 20 7d
1973 ];
1974 sandbox,erasesize = <(512 * 1024)>;
1975 sandbox,oobsize = <224>;
1976 sandbox,pagesize = <4096>;
1977 sandbox,pages = <0x200000>;
1978 sandbox,err-count = <3>;
1979 sandbox,err-step-size = <512>;
1980 };
1981 };
Simon Glass2e7d35d2014-02-26 15:59:21 -07001982};
Przemyslaw Marczak9038cd52015-05-13 13:38:35 +02001983
1984#include "sandbox_pmic.dtsi"
Heinrich Schuchardt4a2a78c2021-02-18 13:01:35 +01001985#include "cros-ec-keyboard.dtsi"
Simon Glass8de98962022-10-20 18:23:15 -06001986
1987#ifdef CONFIG_SANDBOX_VPL
1988#include "sandbox_vpl.dtsi"
1989#endif
Simon Glass82cafee2023-06-01 10:23:01 -06001990
1991#include "cedit.dtsi"